Abstract: Disclosed is an electronic device including a power regulator; a processor; a connector comprising first power pins that electrically connect an external electronic device with the power regulator, and first data reception pins that are disposed adjacent to at least some of the first power pins and electrically connect second data transmission pins of a connector of the external electronic device with data reception terminals of the processor; and one or more first receiver capacitors that are electrically connected to the first data reception pins and to the processor in order to block power from leaking into the first data reception pins from the at least some of the first power pins.

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

Abstract: The present disclosure provides a circuit. The circuit includes a detection circuit, a correction circuit and an adjustment circuit. The detection circuit is configured to detect an initial logic state of an input signal, and to generate, in response to the initial logic state, a first signal with a first logic state. The correction circuit is configured to compare the first signal having the first logic state with a second signal having a second logic state, and to generate an enable signal according to the comparison. The adjustment circuit is configured to be enabled by the enable signal when the first logic state of the first signal is different from the second logic state of the second signal, to generate an adjustment signal to the detection circuit, in which the detection circuit is further configured to be adjusted according to the adjustment signal, to generate an adjusted first signal.

Abstract: A method for controlling operation of a comparator that includes an amplifier that is connected at an input of the comparator includes neutralizing any change of state of a signal output by the comparator starting from each moment in time at which the change of state of the output signal occurs and lasting for a duration of propagation to compensate for a duration of propagation of signals within the amplifier.

Abstract: In one embodiment, a current source is coupled to a channel input of a switch, and an output of the switch is coupled to a positive or negative data line in a USB 2.0 communication system. In addition, a first input of the voltage threshold comparator is coupled to the negative data line, a second input of the voltage threshold comparator is coupled to a positive data line, and an output of the voltage threshold comparator is coupled to a control input of the switch.

Abstract: A device includes a first transistor having a first source terminal, a first drain terminal, and a first gate terminal; and a second transistor having a second source terminal, a second drain terminal, and a second gate terminal. The second source terminal is coupled to the first gate terminal and the first source terminal is coupled to the second gate terminal. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage different from the first threshold voltage.

Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation and a high noise margin. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and a control signal and to generate an output signal based on the incoming signal. The first buffer exhibits a first hysteresis range while configured in a first hysteresis state and a second hysteresis range while configured in a second hysteresis state. The first buffer is configured to transition from the first to the second hysteresis state and vice versa in response to the control signal. The circuit includes a second buffer configured to receive the incoming signal and to generate the control signal based on the incoming signal. The second buffer exhibits a third hysteresis range with a lower threshold and an upper threshold.

Abstract: There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different.

Abstract: Transmitters for data communication can include a pattern generator configured to generate parallel data stream composed of k bits, k being a natural number greater than 2, a serializer configured to convert the parallel data stream into a serial data stream, a pre-emphasis circuit configured to pre-emphasize the serial data stream based on a pre-emphasis control value, to transmit the pre-emphasized serial data stream to a receiver via a first transmission line, and a pre-emphasis controller configured to receive measured values of transmission errors of the pre-emphasized serial data stream from the receiver via a second transmission line, and configured to set the pre-emphasis control value corresponding to a minimum measured value of the transmission errors, to an optimum pre-emphasis control value.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: System and method for deglitching an input signal. An output signal may be delayed to generate a delayed signal, the delayed signal determining a guard time interval following a desired transition in the input signal, and a logic circuit is used to keep the output signal unchanged during the guard time interval, and to allow the output signal to equal the input signal outside the guard time interval, based on a value of the delayed signal.

Abstract: System and method for deglitching an input signal. An output signal may be delayed to generate a delayed signal, the delayed signal determining a guard time interval following a desired transition in the input signal, and a logic circuit is used to keep the output signal unchanged during the guard time interval, and to allow the output signal to equal the input signal outside the guard time interval, based on a value of the delayed signal.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.

Abstract: A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: The Schmitt circuit includes a first logic circuit that receives an output signal of the input logic circuit and has a first threshold voltage. The Schmitt circuit includes a second logic circuit that receives the output signal of the input logic circuit and has a second threshold voltage lower than the first threshold voltage. The Schmitt circuit includes a variable resistance circuit that adjusts the threshold voltage of the input logic circuit in accordance with an output signal of the first logic circuit and an output signal of the second logic circuit.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.

Abstract: A system comprises signal paths. There are first through n signal paths, n being a positive integer. A critical one of the first through n signal paths is based on being a respective one of the first through n signal paths having a slowest signal propagation and/or a path in which a signal propagates slower than a clock cycle. The critical one of the first through n signal paths comprises a first size of a standard cell including corresponding logic devices. The non-critical ones of the first through n signal paths comprise a second size of a standard cell including corresponding logic devices, the second size being smaller than the first size.

Abstract: An electronic device designed to transport digital information (“0”, “1”) over long distances, including a transmitter generating current pulses and at least one assembly of receivers converting the received current pulses into logic pulses which are compatible with the operation of standard electronic logic circuits. Each receiver includes a pair of magnetoresistive stacks containing at least one hard ferromagnetic layer and one soft ferromagnetic layer separated by a non-ferromagnetic interlayer, the hard layer of each of the magnetoresistive stacks being pinned in a magnetic orientation perpendicular to an easy-magnetization axis which is used as a reference for the soft layer of the same stack. The soft layer of each magnetoresistive stack has a magnetic orientation which can be modulated by the magnetic field generated by current pulses delivered by the transmitter so as to cause modification of the transverse resistance of the stack sufficient to trigger an electrical signal.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: Methods, systems, computer readable media and means for reducing errors in data caused by noise are provided. In some embodiments of the present invention, circuitry of the device receives timing data from one or more other circuitries and identifies noiseless periods from the timing data. The circuitry then actively adjusts the trigger point threshold of data being transmitted to and/or from the circuitry only during the noiseless periods. The circuitry subsequently monitors the timing data to identify noise periods. In response to identifying a noise period, the device ceases to adjust the trigger point threshold until the noise period is over.

Abstract: An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.

Abstract: Predriver equalization is described. A predriver includes a predriver equalizer to provide equalization on outputs of predrivers. The predriver equalization causes the predrivers to drive the output driver and a preemphasis driver with signals equalized to reduce common mode noise on the output signal. The predrivers can be implemented as complementary semi-differential driver circuits or as complementary logic circuits with weak pull-downs. The driver complexity can be reduced to the use of a semi-differential driver with the use of the predriver equalization.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.

Abstract: A method of transmitting data can include pre-emphasizing data for transmission by a transmitter over a transmission line based on an error feedback signal provided to the transmitter from a receiver of the pre-emphasized data.

Abstract: A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2).

Abstract: A method of transmitting a signal on a bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.

Abstract: Noise reduction among conductors, the conductors disposed adjacent to one another, the conductors characterized as two or more aggressor conductors and one or more victim conductors, a least two of the aggressor conductors driven with at least two signals that induce unwanted crosstalk upon at least one of the victim conductors, a programmable delay device disposed in a signal path of each of the at least two signals that induce unwanted crosstalk, including programming a delay period into each programmable delay device; receiving, simultaneously at the programmable delay devices, the at least two signals that induce unwanted crosstalk; and transmitting, on two aggressor conductors, the at least two signals that induce unwanted crosstalk, with the at least two signals separated in time by the delay period.

Abstract: A pseudo differential current mode receiver includes a regulated cascode buffer for buffering a received data current to generate a buffered data current with cascode-reduced input impedance and cascode-increased output impedance. In addition, a signal converter generates an output signal indicating a difference between the buffered data current and a reference current. The reference current may also be received and buffered by a regulated cascode buffer with cascode-reduced input impedance and cascode-increased output impedance.

Abstract: A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.

Abstract: A filter circuit includes an input-signal processing section and a signal-level determining section. The input-signal processing section samples and holds a digital input signal input according to a clock signal, outputs the holding signal as a sampling input signal when a level of the digital input signal is constant between sampling points, and reverses the holding signal and outputs the reversed signal as the sampling input signal when the level of the digital input signal changes between the sampling points. The signal-level determining section sequentially delays the sampling input signal from the input-signal processing section into plural stages, outputs a first level signal at a first level when all the delayed signals are at the first level, and outputs a second level signal at a second level when all the delayed signals are at the second level.

Abstract: A bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.

Abstract: A method and apparatus for ameliorating the effects of noise generated by a bus interface provides improved performance of integrated circuits having other circuits sensitive to the transient noise introduced by bus signal switching. Additional signals are generated that equalize the frequency of occurrences of the transients, so that an effectively constant and non-data-dependent frequency is generated over the totality of the signals. The loading characteristics of the additional signals and interface signals are matched, and the interface and additional signals may be generated as complementary pairs, so that the net DC energy of the transients is also substantially made equal to zero. Any or all of the interface and additional signals may be used as data signals, or all but one of the signals may be supplied to an internal or external dummy load. A loading circuit may be calibrated by a circuit that senses the interface loading.

Abstract: A noise canceller circuit capable of suppressing power supply noise, produced by transition of a data signal, even in case a data signal is increased in speed. The noise canceller circuit includes an output buffer 20 for outputting a first binary signal that may undergo transition at a timing synchronized with clock signals, and a second output buffer 21 for outputting a second binary signal which has undergone transition in case the first binary signal does not undergo transition at the above timing and for outputting the second binary signal without transition in case the first binary signal has undergone transition at the above timing. The respective output circuits of the output buffers 20, 21 are the same and are constructed so that the respective power supply sources VDD and the ground GND are common to the buffer circuits. A capacitor 24 for absorbing the noise is provided across the power supply and the ground.

Abstract: Embodiments for controlling pre-emphasis driver circuits for electrical signal interconnects within a computer system are disclosed.

Abstract: A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connected to the common mode node, and exhibits a substantially zero output impedance. In so doing, the common mode control circuit provides a common mode voltage to the common mode node of the termination circuit that exhibits substantially ideal termination of common mode signals and negligible loading on the differential input nodes. In another aspect, selection circuitry is provided that selectively passes single-ended or differential test signals to the differential input nodes during a test mode of operation. The selection circuitry facilitates observation of signals within the receiver circuitry.

Abstract: A receive circuit having a sampling circuit and a threshold generating circuit. The sampling circuit generates a first sample value having either a first state or a second state according whether an incoming signal exceeds a first threshold level, the first threshold level corresponding to a first threshold value. The threshold generating circuit combines a first control value and a second control value to generate the first threshold value and provides the first threshold value to the sampling circuit.

Abstract: An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

Abstract: A data input buffer for use in a semiconductor device, including: a detection unit for receiving a reference voltage signal and an input data signal through a first input terminal and a second input terminal respectively in order to detect a voltage level of the input data signal based on a result of comparing the input data signal with the reference voltage in response to a clock enable signal inputted through a third input terminal; and a noise elimination unit connected between the first input terminal and the third input terminal for eliminating a noise of the reference voltage signal.

Abstract: Systems and methods for reducing variations in the timing of signal transitions which may result from interference with neighboring signal lines by adjusting the drivability of in-line buffers based upon the hostile/friendly condition of the neighboring lines. In one embodiment, a first inverter includes selectable current paths between the buffer output and Vdd/ground. A higher current is selected for one path and a lower current is selected for the other path so that the buffer output will be pulled more strongly in the direction (Vdd/ground) to which the neighboring signals may be hostile. In one embodiment, each selectable current path includes a plurality of parallel transistors, one of which is always switched on and the others of which are switched on or off according to the friendly/hostile states of the neighboring signals.

Abstract: Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper dumps charges at least one of from and to the circuit location, wherein the charge dumper comprises at least one gating transistor to dump the charges, the at least one gating transistor is directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.