Abstract: An apparatus is provided which comprises: an oscillator to generate a first clock having a first frequency; a divider coupled to the oscillator, wherein the divider is to generate a second clock having a second frequency; and a current reference generator comprising a switched capacitor circuitry which is to receive the second clock directly or indirectly.

Abstract: This application describes methods and apparatus for selectively clamping a signal path (106) for an analog audio signal to a clamp voltage, e.g. ground. Voltage clamping circuitry (200) is disclosed having a first switching device (201) in series with a second switching device (202) between a node of the signal path and the clamp voltage. The clamping circuitry is configured to be operable in: a first state where the first and second switching devices are both on to electrically connect the signal path to the clamp voltage; and also a second state to electrically disconnect the signal path from the clamp voltage. In the second state one of the first and second switching devices is configured to block conduction when the voltage at said node of the signal path is positive and the other switching device is configured to block conduction when the voltage at said node of the signal path is negative.

Abstract: A semiconductor switch is configured to conduct or cutoff a signal path from its first terminal to its second terminal. An enhancement-type first transistor is arranged between the first terminal and the second terminal. A first bias circuit is connected to apply a gate voltage VG that corresponds to a control signal VCNT to the gate of the first transistor when the power supply voltages VDD and VSS are supplied. A second bias circuit is connected such that a voltage that corresponds to the lower voltage of the voltages at the first terminal and the second terminal is applied to the gate of the first transistor when the power supply voltages VDD and VSS are not supplied.

Abstract: An inter-line switching element formed of a MOSFET is provided between a pair of signal lines. When the level of a differential signal changes from high to low, a control circuit turns on the FET for a fixed period thereby to suppress ringing by decreasing the impedance between the signal lines when the level of the differential signal transitions, and causing the energy of the distortion of the differential signal waveform to be absorbed by the on-resistance of the FET.

Abstract: A system includes analog supply circuitry providing first and second analog potentials. A switch module assumes first or second states to enable and inhibit transfer of an analog electrical signal from a source module to a user module based upon a driving electrical signal. A driving device drives, based upon the driving electrical signal, a control terminal of the switch module, allowing the switch module to assume the first or second state. The driving device allows the switch module to make a first driving transition from the first state to the second state, and a second driving transition from the second state to the first state. The driving device alternately connects the control terminal to a first reference potential, during the first state, and to a second reference potential, during the second state.

Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Abstract: The Schmitt circuit includes a first logic circuit that receives an output signal of the input logic circuit and has a first threshold voltage. The Schmitt circuit includes a second logic circuit that receives the output signal of the input logic circuit and has a second threshold voltage lower than the first threshold voltage. The Schmitt circuit includes a variable resistance circuit that adjusts the threshold voltage of the input logic circuit in accordance with an output signal of the first logic circuit and an output signal of the second logic circuit.

Abstract: A method for converting a repeater circuit from a dynamic repeater circuit to a static repeater circuit. The method includes disconnecting a feedback path coupled to a first stage of the dynamic repeater circuit and electrically shorting gate terminals of first and second transistors of a second stage to each other, wherein the transistors of the second stage are configured to drive an output signal on an output node. Disconnecting the feedback path and electrically shorting the gate terminals is performed by reconfiguring a plurality of selection devices in the repeater circuit from a first configuration to a second configuration. The repeater circuit includes at least one keeper configured to provide an output signal on the output node.

Abstract: Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another embodiment, switches are set to a second switch position to operate the circuit in the normal mode.

Abstract: An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coupled to said output signal line for changing state of said output stage subsequent to a delay after a transition of said output signal. The delay is due to transmission line effects of said output signal line.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state to assist in the rising transition. The circuit also includes a second subcircuit that causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and then turn off. The second transistor drives the output to a low state to assist in the falling transition.

Abstract: Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another embodiment, switches are set to a second switch position to operate the circuit in the normal mode.

Abstract: A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The first PFET is configured to convert a low level signal at the input terminal to a high level signal at the output terminal, and the BJT is configured to convert a high level signal at the input terminal to a low level signal at the output terminal. The radiation hardened inverter includes a second PFET disposed in the second electrical path. The second PFET is configured to provide a path for bleeding excess current away from the BJT. The radiation hardened inverter also includes a current limiting PFET disposed in the second electrical path. The current limiting PFET is configured to limit current flowing into a base of the BJT. The radiation hardened inverter is free-of any NFETs.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.

Abstract: Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability, is provided and described. In one embodiment, switches are set to a first switch position to operate the repeater circuit in the high performance repeater mode. In another embodiment, switches are set to a second switch position to operate the repeater circuit in the normal repeater mode.

Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device such as a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the automated testing procedure terminates, and the programmed IC begins to function according to the user design as determined by the last programmed bitstream.

Abstract: An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coupled to said output signal line for changing state of said output stage subsequent to a delay after a transition of said output signal. The delay is due to transmission line effects of said output signal line.

Abstract: A floating CMOS input circuit is disclosed that does not draw direct current. The floating CMOS input circuit comprises a first inverter circuit that is capable of being coupled to an input voltage (Vin) and an n-channel pull-down transistor (N1) that is coupled to the first inverter circuit. The n-channel pull-down transistor (N1) pulls the input voltage (Vin) on the first inverter circuit to a hard ground when the input voltage (Vin) is not driven high. This eliminates the leakage of direct current in the first inverter circuit. The floating CMOS input circuit also powers up in a known state.

Abstract: An over-voltage tolerant input stage in a semiconductor device is disclosed. The input stage includes: an input pad for receiving an input signal to the semiconductor device, a buffer coupled to the input pad for buffering the input signal, a pullup circuit for limiting current in the input signal, a switching circuit coupled to the input pad for controlling the pullup circuit, and a voltage supply coupled to the input pad, the pullup circuit and the switching circuit. In operation, the switching circuit is enabled to cause the pullup circuit to stop current flow between the input signal and voltage supply in the event of an over-voltage condition.

Abstract: Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability, is provided and described. In one embodiment, switches are set to a first switch position to operate the repeater circuit in the high performance repeater mode. In another embodiment, switches are set to a second switch position to operate the repeater circuit in the normal repeater mode.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state to assist in the rising transition. The circuit also includes a second subcircuit that causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and then turn off. The second transistor drives the output to a low state to assist in the falling transition.

Abstract: A logic-keeping apparatus including a logic judgment unit and a noise-event detection unit is disclosed. When the level at the input terminal of the logic judgment unit is larger than a first level, the output terminal thereof outputs a first logic state; when the level at the input terminal is smaller than a second level, the output terminal thereof outputs a second logic state; when the level at the input terminal is between the first level and the second level, the output terminal thereof keeps the previous logic state. The noise-event detection unit is for detecting whether a noise-event occurs (for example, an ESD event). Wherein, when a noise-even occurs in the system, the noise-event detection unit keeps the level at the input terminal of the logic judgment unit between the first level and the second level.

Abstract: The present invention relates to a delay-insensitive DI data transfer circuit based on a current-mode multiple-valued logic for transferring data regardless of a delay time of transmission according to a length of wire. The delay-insensitive data transfer circuit of the present invention, in a delay-insensitive data transfer circuit transferring an input request signal and a data signal from a data transmission unit to a data receiving unit, comprises: an encoder for outputting a signal which has been converted to current-level signals in response to voltage-level input of data signal and request signal from the data transmission unit; and a decoder for restoring the voltage-level signals from the current-level signals of the encoder, abstracting a data signal and a request signal from the restored voltage-level signals, and outputting the data signal and the request signal to the data receiving unit.

Abstract: Systems and methods for circuits with substantially equal propagation delay while providing different drive strengths are disclosed. These systems and methods may allow for a circuit with a drive strength that is some ratio of an arbitrary strength full drive strength circuit. Additionally, these circuits may have substantially the same input capacitance and feedback current as the baseline drive circuit. The input of such a circuit may be coupled to three nodes, one of which is an inverter coupled to the logic to be driven, the second of which is dummy logic, and the third of which is an inverter the output of which is left floating.

Abstract: There is provided a data acceleration device comprising a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a second node which is electrically coupled with the first node, in response to an output signal from the pull-up driver, a first pull-down circuit for pull-down driving the second node, in response to an output signal from the pull-down driver, a delay circuit for delaying a signal from the second node by a preset time to output a delayed signal, a first switch for switching an operation of the first pull-up circuit in response to an output signal from the delay circuit, and a second switch for switching an operation of the first pull-down circuit in response to the output signal from the delay circuit. Also, there is presented a data transmission apparatus including the data acceleration device.

Abstract: An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes undershoot-blocking and overshoot-blocking modules that are configured to be coupled to overshoot-insensitive and undershoot-insensitive nodes of the logic circuitry, respectively. The undershoot-blocking module is operable to (i) receive from a first node of the logic circuitry a first signal event having a undershoot condition impressed thereon, and (ii) block it from passing to the overshoot-insensitive node. The overshoot-blocking module is operable to (i) receive from the first node a second signal event having an overshoot condition impressed thereon, and (ii) block it from passing to the undershoot-insensitive node. As such, further propagation of the overshoot and undershoot conditions are prevented.

Abstract: A data input buffer for use in a semiconductor device, including: a detection unit for receiving a reference voltage signal and an input data signal through a first input terminal and a second input terminal respectively in order to detect a voltage level of the input data signal based on a result of comparing the input data signal with the reference voltage in response to a clock enable signal inputted through a third input terminal; and a noise elimination unit connected between the first input terminal and the third input terminal for eliminating a noise of the reference voltage signal.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.

Abstract: Systems and methods for reducing electrical noise generated during bus turnaround in signal transfer systems are provided. These systems include differential drivers having current sources continuously coupled to a signal bus during all operating modes of the drivers. A first transistor of the driver couples a first signal line of the bus to the driver current source and a second transistor of the driver couples a second signal line of the bus to the driver current source. Each transistor receives control signals in accordance with the operating mode of the driver. These control signals continuously and selectively couple the current source to the bus lines in a manner which provides uniform current distribution across the bus during all driver operating modes. The uniform current distribution across the bus minimizes interruptions in driver current dissipation and any effects from self-induced supply noise during signal transfers.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state to assist in the rising transition. The circuit also includes a second subcircuit that causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and then turn off. The second transistor drives the output to a low state to assist in the falling transition.

Abstract: When an output voltage output from a buffer approaches a ground voltage, a MOS transistor turns off, so that clamp for a gate of the MOS transistor is released.

Abstract: Repeater circuit with high performance repeater mode and normal repeater mode is provided and described. In one embodiment, switches are set to a first switch position to operate repeater circuit in the high performance repeater mode. In another embodiment, switches are set to a second switch position to operate the repeater circuit in the normal repeater mode.

Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.

Abstract: Provided is an input buffer whose input capacitance presented to input signals can be reduced. The input buffer includes a first differential amplifier which compares the sizes of a first input signal and a second input signal and outputs an output signal as the result of the comparison; a second differential amplifier which compares the sizes of the first input signal and a reference voltage and outputs a second output signal as the result of the comparison; and a third differential amplifier which compares the sizes of the second input signal and the reference voltage and outputs a third output signal as the result of the comparison, wherein the first differential amplifier shares transistors, to which the first and second input signals are input, with the second and third differential amplifiers. The first differential amplifier operates only in a differential operation mode, and the second and third differential amplifiers operate only in a single operation mode.

Abstract: The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

Abstract: A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair Q5 and Q6 having a tail current source I56; a first buffer Q3 providing a first input to the differential pair; a second buffer Q4 providing a second input to the differential pair; a first current absorbing device Q7 coupled to the tail current source I56 and having a control node SP capacitively coupled to the first buffer Q3; and a second current absorbing device Q8 coupled to the tail current source I56 and having a control node SM capacitively coupled to the second buffer Q4.

Abstract: An apparatus and method for reducing leakage current of transistors used in an integrated circuit, which selectively switch a processor circuit in the integrated circuit to a standby state. A cooling device is included and selectively located in an area of the integrated circuit that is in close proximity to a transistor used to switch a processor circuit between active and standby states. The cooling device cools the transistor in order to improve both its leakage and active current states, thereby increasing efficiency of the transistor and reducing its leakage current.

Abstract: A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.

Abstract: A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.

Abstract: A technique includes, in response to a first signal transitioning to a first logic state and first drive circuit being deactivated, activating a second drive circuit to provide a second signal. In response to the second drive circuit being deactivated and the first signal transitioning to a second logic state that is different from the first logic state, the first drive circuit is activated to provide the second signal.

Abstract: A technique to individually adjust noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network includes identifying precharge nodes of the dynamic circuit that require a reduction of noise. The technique further includes identifying NMOS transistor drains connected to respective precharge nodes, and creating a pull-up network of PMOS transistors for the identified precharge nodes. After creating a pull-up network of PMOS transistors, the technique includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve noise immunity and performance of the dynamic circuit. After arranging the order of the PMOS transistors, the technique can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes.

Abstract: An apparatus and method for reducing leakage current of transistors used in an integrated circuit, which selectively switch a processor circuit in the integrated circuit to a standby state. A cooling device is included and selectively located in an area of the integrated circuit that is in close proximity to a transistor used to switch a processor circuit between active and standby states. The cooling device cools the transistor in order to improve both its leakage and active current states, thereby increasing efficiency of the transistor and reducing its leakage current.

Abstract: A method of testing field programmable gate array (FPGA) resources and identifying faulty FPGA resources during normal on-line operation includes configuring an FPGA into a working area and an initial self-testing area. The working area maintains normal operation of the FPGA throughout testing and identifying of the resources. Within the initial and subsequent self-testing areas, the FPGA resources are initially tested for faults. Upon detection of a fault in the FPGA resources, the initial self-testing area resources are reconfigured or subdivided and further tested in order to identify the faulty resource. Dependent upon the further test results, the FPGA resources may be further subdivided and tested until the faulty resource is identified. Once the faulty resource is identified, the FPGA is reconfigured to replace unusable faulty resources or to avoid faulty modes of operation of partially faulty resources diagnosed during further testing.

Abstract: A noise suppression circuit for suppressing above-ground noise is disclosed. The noise suppression circuit for suppressing noises includes a first inverter, a second inverter, and a one-shot circuit. The first inverter, connected to an input line, switches at a first voltage value above which a noise-coupling event is suspected. The second inverter, also connected to the input line, switches at a second voltage value above which a full-switch input is assumed. A first transistor is coupled to the input line. A second transistor passes an output of the second inverter to a gate of the first transistor when an output of the one-shot circuit is high. The third transistor holds the gate of the first transistor low when the output of the one-shot circuit is low.

Abstract: A fail-safe circuit for a pair of differential input lines detects when one or both lines are open. Each line has a pull-up of a switched p-channel transistor in series with a resistor or another p-channel transistor that has its effective resistance controlled by a gate bias. The gate of the switched p-channel transistor is driven to ground when power is applied to the gate of a grounding n-channel transistor. When power is off, a p-channel connecting transistor charges the gate node from the differential input line when a positive voltage is applied to the input line, such as during a leakage test. Charging the gate node prevents the switched p-channel transistor from turning on, blocking a leakage current path through the pull-up. An N-well bias circuit can be added, which connects the N-well under p-channel transistors to power or the gate node or the input line.

Abstract: A method for calculating the P/N ratios of static gates based on the voltages presented at the inputs of these static gates. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, a maximum and minimum P/N ratio is calculated. A maximum and minimum P/N ratio is determined in order provide more accurate models for simulating problems, for example, noise on the inputs. Using the P/N ratios created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in and most likely reduce the probability that the particular integrated circuit they are designing will have design errors.

Abstract: A method for calculating the P/N ratios of static gates based on the voltages presented at the inputs of these static gates. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, a maximum and minimum P/N ratio is calculated. A maximum and minimum P/N ratio is determined in order provide more accurate models for simulating problems, for example, noise on the inputs. Using the PIN ratios created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in and most likely reduce the probability that the particular integrated circuit they are designing will have design errors.

Abstract: A receiver circuit in a communication system receives a complementary potential signal having a ground level or a floating level from a transmitter circuit through a pair of transmission lines. The receiver circuit includes first and second switching transistors for supplying a complementary current signal based on the complementary potential signal, a current detection transistor for detecting the current flowing through the switching transistors, and a potential control unit for controlling the gate potentials of the switching transistors based on the detected current for implementing a negative feedback loop. The negative feedback loop compensates the influence by a fluctuation of the potential of the transmitter circuit or the receiver circuit.

Abstract: A programmable linear transconductor circuit is disclosed. The programmable linear transconductor circuit includes a first current source and a second current source, a first group of transistors and a second group of transistors, a first load coupled to the first group of transistors, and a second load coupled to the second group of transistors, and a first group of switches and a second group of switches. Each switch in the first group of switches is selectively connected to a transistor from the first group of transistors to the first current source or the second current source. Similarly, each switch in the second group of switches is selectively connected to a transistor from the second group of transistors to the first current source or the second current source, accordingly.

Abstract: The small swing output buffer of the present invention comprises, for example, four transistors or FETs; P1, P2, N1, and N2. The source of P2 is connected to Vcc and the drain of P2 is connected to the source of P1. The drain of PI is connected to the source of N1. The drain of N1 is connected to the source of N2. The drain of N2 is connected to ground. The input signal to the output buffer is fed into input IN which is connected to the gates of P1 and N1. The output of the output buffer is output OUT which is connected to the drain of P1 and the source of N1. For the small swing output buffer, when the input signal is at a high potential, P1 and P2 are turned off and N1 and N2 are turned on which pulls down the potential of OUT towards ground potential. Since FETs have a threshold voltage, the potential of the output OUT cannot be completely pulled to ground potential. Therefore, the potential of the output OUT when the input signal applied to IN is a high potential, is the threshold voltage (Vt) of N2.