Abstract: An apparatus for controlling an on die termination (ODT) includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a comparing control unit for comparing the counted toggle number of the external clock signal with that of the DLL clock signal in response to an ODT command signal, and outputting an ODT enable signal for controlling the ODT based on the compared result.

Abstract: An on die termination (ODT) control device includes a latency block for buffering an ODT control signal to output a latency control signal by selecting one of a plurality of intermediate control signals, which are generated by sequentially delaying the buffered ODT control signal in synchronization with an internal clock, based on first latency information; an enable signal generation block for comparing a first control signal with a second control signal in response to the latency control signal to thereby produce an ODT enable signal based on the compared result; and an ODT block for controlling a termination impedance based on the ODT enable signal.

Abstract: An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external clock to output an internal clock; a unit delaying set for sequentially delaying the internal clock to output a plurality of delayed clocks; a phase detecting block for detecting logic levels of the delayed clocks at a rising edge of the internal clock to output phase detecting signals; a sampling pulse generator for outputting a sampling signal generated at a predetermined point of the internal clock; a latching block for outputting a phase detection latch signal by sampling and latching the phase detection signal at a point of the sampling signal being inputted; and a frequency detection block for outputting the frequency detection signal by logically combining the phase detection latch signal.

Abstract: A memory device includes a first termination unit coupled to a first pin for receiving a first signal having a first frequency component. The memory device also includes a second termination unit coupled to a second pin for receiving a second signal having a second frequency component higher than the first frequency component. The first termination unit is a different type from the second termination unit that provides less signal distortion than the first termination unit. For example, the first termination unit is of an open-drain type that has less power consumption, and the second termination unit is of a push-pull type that has less signal distortion.

Abstract: An on-DRAM termination resistance control circuit is capable of controlling resistance of an IC termination and minimizing area for the resistance control circuit by using a simplified circuit scheme. The on-DRAM termination resistance control circuit includes a push-up resistance adjusting unit, a pull-down resistance adjusting unit and resistance adjustment control unit. The push-up resistance adjusting unit adjusts resistances of a first and a second inner resistors based on an external reference resistor. The pull-down resistance adjusting unit adjusts a resistance of a third resistor based on the second inner resistor that is adjusted by adjustment of the push-up resistance control unit. The resistance adjustment control unit controls to alternatively repeat the operation of the push-up resistance adjusting unit and the pull-down resistance adjusting unit for a predetermined number of adjustment times.

Abstract: A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

Abstract: Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper dumps charges at least one of from and to the circuit location, wherein the charge dumper comprises at least one gating transistor to dump the charges, the at least one gating transistor is directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

Abstract: A semiconductor device capable of detecting and suppressing SSO noise after the semiconductor device has been mounted on a board. The semiconductor device includes an output circuit for outputting parallel output signals in accordance with a clock signal, an SSO noise generation circuit for activating the output circuit to generate SSO noise, and a clock control circuit for detecting the SSO noise and adjusting phase of the clock signal to suppress the SSO noise.

Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.

Abstract: A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set at 50 ohms which is equal to the characteristics impedance of the external signal transmission path. The matching impedance between a internal signal transmission path (13) and an input-side or output-side IC or intermediate IC is set at 200 ohms which is higher than the 50 ohms. The semiconductor device reduces the current dissipation and can operate at a higher speed.

Abstract: A low-power memory module has an active termination circuit at each end of critical signal traces. The dynamic termination circuit has a low-value resistor that is connected to a termination voltage by a transmission gate that is turned on by a switch signal. The switch signal is activated when the memory module is selected by a chip-select signal, and when a time window is open. The time window is generated from the clock to synchronous DRAMs on the memory module. The time window can be one-quarter of the clock period by ANDing the clock and a delayed clock that is delayed by one-quarter of a cycle. A static terminating resistor in parallel with the low-value resistor provides a much smaller terminating current that is not switched on and off. Traces can be impedance-matched at junctions to branches that each has a dynamic termination circuit at the far end.

Abstract: A circuit for performing an on-die termination operation includes a clock buffer for outputting first and second buffered clocks using an external clock and an external inverting clock applied thereto externally; an on-die termination buffer for comparing each other an ODT signal and a reference voltage, which are applied thereto from an external chip set, to generate an on-die termination comparison signal; a first flip-flop member for transferring the on-die termination comparison signal as a plurality of parallel output signals based on the first and second buffered clocks outputted from the clock buffer; and a plurality of second flip-flop members, which corresponds to each of the parallel output signals outputted from the first flip-flop member, for transferring the parallel output signals outputted from the first flip-flop member based on delayed lock loop clocks outputted from a delayed lock loop.

Abstract: Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.

Abstract: The open-drain type output buffer includes a first driver and at east one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and pulls the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the first state when a transition from a steady high voltage output data to a low voltage output data is determined.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A skew-free dual rail bus driver is provided. The dual rail bus driver includes a first driver outputting first dual signals of the same level, and outputting second dual signals of different levels when a level of a clock changes; a decoder receiving the second dual signals and outputting a single signal; a dual signal controller being triggered due to a change in the level of the second dual signals and outputting third dual signals of different levels in response to the single signal at the same time; and a second driver inverting the levels of the third dual signals output from the dual signal controller and outputting fourth dual signals in accordance with a change in the level of the clock. Accordingly, it is possible to obtain dual rail bus driving signals in which skew does not occur. Also, changes in the phases of dual signals are detected and used as a trigger signal input to an edge trigger flip-flop which is a dual signal controller.

Abstract: A semiconductor integrated circuit device is provided with a diagnosis circuit, which does not increase the delay of a logic element in normal operation. In a latch provided at the output of a memory or at the input of a logic stage, a signal selector is provided in the feedback loop of the latch. The selector is switched in correspondence with the operation mode, such that it transfers the feedback signal in normal operation, while it transfers the test signal in a test mode, in order to prevent the delay from increasing in the signal selector on the main path in normal operation.

Abstract: An apparaus is disclosed which includes a converter circuit and a noise suppression circuit. The converter circuit has a dynamic logic input, and is configured to generate a static logic output on an output node responsive to the dynamic logic input. The noise suppression circuit is coupled to receive a clock signal and is coupled to the output node. Responsive to a first phase of the clock signal, a precharge of a dynamic logic circuit generating the dynamic logic input occurs. The noise suppression circuit is configured to actively drive the static logic output on the output node responsive to the first phase. In some embodiments, the noise suppression circuit may reduce the noise sensitivity of the static logic output during the precharge phase, and may not impede operation of the converter circuit during the evaluate phase.

Abstract: Clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. In addition, the clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function.

Abstract: Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or “dip” experienced by prior art half-rail differential logic circuits and is therefore more power efficient.

Abstract: Clocked full-rail differential logic circuits with shut-off include a shut-off device. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.

Abstract: A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal.

Abstract: A precompensation cutback differential driver includes a main buffer, a set of secondary buffers, and control logic circuitry. The main buffer is arranged to drive a first input differential signal for output as a differential output signal over a differential output line. The set of secondary buffers is arranged to receive second input differential signals, tristate signals, and mode signals with each secondary buffer receiving one second input differential signal, one tristate signal, and one mode signal. The secondary buffers are further configured to operate in a normal slew rate or a slow slew rate. Each tristate signal is configured to drive the associated secondary buffer to high impedance to turn off the associated secondary buffer when the tristate signal is asserted. Additionally, each secondary buffer is configured to operate in a slow slew rate in response to the associated mode signal.

Abstract: A random logic circuit comprises an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.

Abstract: Methods and apparatus for controlling critical races in sequential circuits so that the there are no conflicts when two or more different data signals exists on shared circuit paths. This enables the design and implementation of sequential circuits having fewer gates than conventional circuit designs of equivalent function that translates into smaller area and power consumption. The control of the critical race is accomplished by adjusting the relative delay of the individual sections of one or more loops.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and &agr; particle noise and noises due to charge redistribution effect or leakage current can be prevented.

Abstract: A threshold amplifier receives a logic supply voltage and a ground voltage and includes a Schmitt trigger comprising an inverter stage and a hysteresis stage connected to the inverter stage for setting a high and a low hysteresis threshold. A disabling circuit disables the hysteresis stage as a function of a level of the logic supply voltage. The threshold amplifier further includes a detection circuit for detecting the level of the logic supply voltage with respect to a detection threshold, and for activating the disabling circuit for disabling the hysteresis stage when the level of the logic supply voltage is below the detection threshold.

Abstract: A method for reducing the noise associated with a clock signal for a latch based circuit has been developed. The method includes storing a charge at a pre-determined time of the clock cycle and releasing the stored charge also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.

Abstract: One clock is selected from a plurality of clocks by a selector through programming. Clock lines are connected to the outputs of clock buffers connected to the selector. Programmable connector elements are connected onto these lines, and flip-flops and regulation loads are connected thereto. The programmable connector elements are selected through programming. This construction can realize a clock distributing circuit in a programmable logic device, which can suppress an increase in skew and can reduce a clock line wiring area.

Abstract: A glitch filter includes a storage element for storing a current state, which is the output of the filter. An output of the storage element is-connected to one input of a state comparator. Another input of the state comparator is connected to an input signal. A programmable clock delay is connected between the state comparator and the storage element. The programmable clock delay may provide a programmed duration independent of the technology used for implementation. The glitch filter is arranged such that the input signal is stored as the new current state in the storage element only if the input signal changes and then remains unchanged for the programmed duration.

Abstract: A system of individually adjusting noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network comprises identifying precharge nodes of the dynamic circuit requiring a reduction of noise. Then further identifying NMOS transistor drains connected to the respective precharge nodes, then creating a pull-up network of PMOS transistors for the precharge nodes, respectively. After creating a pull-up network of PMOS transistors, the system further includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve the noise immunity and performance of the dynamic circuit. After completing the arranging of the order of the PMOS transistors, the system can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes, respectively.

Abstract: A method for reducing the noise associated with a clock signal for a latch based circuit has been developed. The method includes storing a charge at a pre-determined time of the clock cycle and releasing the stored charge also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A logic cell capable of realizing a high speed logic operation without using a pipeline register and capable of realizing a simplification of the circuit structure and a lowering of the power consumption, and a logic circuit using the same, wherein an input register converts an input data to a two-wire code synchronous to a clock signal and supplies the same to a logic cell array, each logic cell of the logic cell array performs a predetermined logic operation, when an output code of a monitor cell changes to a valid logic code, an early completion detection signal output from a NOR gate becomes “L”, the input register is reset in accordance with this, and the output becomes a blank code, the blank code is propagated by the logic cell array, and when the output of the monitor cell changes to the blank code, the output of the NOR gate becomes “H”, the reset is released, and the input register supplies the input data to the logic cell array.

Abstract: Current pulse matchers monitor the wires of a static or precharge-pulldown bus. Each current pulse matcher monitors the wire that it is connected to. For a precharge-pulldown bus, if the wire has been discharged during the pulldown cycle of the bus, the precharge current pulse matcher does not consume any current. If, however, the wire was not discharged during the pulldown cycle of the bus, then the precharge current pulse matcher consumes an amount of current that approximates the amount of current used to precharge that wire had it been discharged. For a static bus, the current pulse matcher does not shunt current if the wire has not just made transition. Otherwise, the static bus current pulse matcher shunts an amount of current that may approximate the amount of current used to transition the bus signal from one logic state to another.

Abstract: A structure and method for reducing bipolar current in of a SOI circuit by alternating precharge low and precharge high methodologies comprises a reset signal source coupled to an inverter and a primary node, further coupled to a first and second PFET device; a clock signal source; coupled to a first NFET device and a third PFET device; a first input signal source coupled to a second NFET device and a fourth PFET device; a first NFET stack node coupled to the third PFET device, the first NFET device, the primary node, and the second NFET device; a second input signal source coupled to a third NFET device; a fifth PFET device coupled to the fourth PFET device; a power supply voltage source coupled to the fifth PFET device; and a second NFET node coupled to the fourth PFET device, the second NFET device, and the third NFET device.

Abstract: A new self clocking family of dynamic logic gates which replace footless or subsequent stage dynamic logic gates in multi-stage domino logic circuits. In a preferred embodiment, a multi-stage logic circuit is designed having a first stage which utilizes a traditional dynamic logic gate and a second stage which includes a new self-clocking dynamic logic gate. The output from the first stage is coupled to the input of the second stage such that the second stage is not dependent upon any type of clock signal for precharging. Instead, the second stage includes a dual transistor arrangement on the inter-stage inputs (i.e. the outputs from one stage which are input to subsequent stages) in order to precharge the output node at the second stage such that no type of clock signal is needed during precharge. Accordingly, the output from the second stage is efficiently precharged without using a delayed clock signal or any customized delay circuitry while minimizing through current by design.

Abstract: A latch having a pass gate, multiple clock paths connected to the pass gate, and a data path connected to the pass gate, wherein the data path and the multiple clock paths have the same number and types of elements.

Abstract: A technique for reducing such ground bounce using phased outputs and package de-skewing for source synchronous buses is described. In one embodiment, the output buffers of an integrated circuit (“IC”) are phased so that half of the buffer outputs are driven first and the remaining half are driven a slight time delay later. The outputs are then de-skewed by package routing so that the earlier signals reach the package pins at the same time as the later signals. This deskewing is accomplished by serpentining and length-matching the bank of non-delayed outputs so that these trace-induced delays match an optimized fixed clock delay used to delay the bank of delayed outputs, the traces of which are length-matched and routed as short as possible.

Abstract: A random logic circuit comprises an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.

Abstract: A clock driver for an integrated circuit reduces electro-magnetic interference (EMI) induced in nearby metal traces yet also reduces jitter due to noise at the switching threshold. A weak driver using small n-channel and p-channel transistors initially drives the clock line. Then a pulse generator produces a short pulse to a gate of a large driver transistor. The large driver transistor is pulsed on for a very short period of time. The large driver transistor is turned off by the end of the pulse before the clock line completes its transition. The weak driver then finishes the clock-line transition. Since only the weak driver is on during the start and end of the transition, a slow voltage-slew rate occurs at the beginning and end of the transition. The large driver transistor is on only in the middle of the transition, producing a fast voltage-slew rate in the middle. A triple-slope waveform results.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is provided. The noise suppression circuit for suppressing noises includes a clamping transistor, a feedback circuit, and a presetting means for presetting an internal latch of the noise suppression circuit to a predetermined state. The predetermined state is a high state or a low state depending upon the type of noise suppression accomplished by the circuit. After the occurrence of a noise coupling event, the clamping transistor restores the state of a data input of a circuit to which the suppression circuit is providing protection. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: An apparatus for high speed signal propagation across a net in an integrated circuit operates with a driver that is coupled to the net, for driving signals across the net. A first transition assist driver (TAD) is coupled to a first node in the net and is capable of pulling the voltage level of the first node in response to the voltage level of the first node reaching a threshold value. The threshold value can be adjusted in order to increase the switching speed or, alternatively, the noise immunity of the first TAD. A second TAD is coupled to a second node in the net and is capable of pulling the voltage level of the second node in response to the voltage level of the second node reaching the threshold value. The apparatus is used for increasing the propagation speed of signals that are transmitted in a microprocessor block or other stages in an integrated circuit.

Abstract: An output driver circuit of a clocked integrated semiconductor memory of the DRAM type is driven by a circuit for generating an output signal as a function of two input signals. A validity signal, which is supplied to the circuit, ensures that the data to be output are in a valid state before the output driver is activated. As a result, a situation in which different propagation times of input signals of the output driver circuit lead to multiple switching operations within an access cycle of a memory access is prevented. An event-oriented control of the enabling process of the output driver ensures a proper function even in the case of variable frequencies of the clock control.

Abstract: A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word.

Abstract: A signal transition accelerating driver circuit firstly charges a signal line to a precharging level, thereafter, maintains the precharging level or discharges the signal line depending upon the potential level of the data/bus status signal, for this reason, any gate circuit is required, and the circuit configuration is simple.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is disclosed. The noise suppression circuit for suppressing noises includes a means for generating a power-on-reset signal, a clamping transistor, and a feedback circuit. The means for generating a power-on-reset signal presets an internal latch of the noise suppression circuit to a predetermined state, such as a logical high state. The clamping transistor restores the state of a data input of a circuit to which the noise suppression circuit is providing protection, after the occurrence of a noise coupling event. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: A domino logic circuit having output noise elimination is disclosed. A compound domino logic circuit includes at least two trees of logic devices arranged in parallel, with each tree having a precharge transistor connected to a power supply, and one or more input transistors coupled between the precharge transistor and ground. The precharge transistor receives a clock input while each of the one or more input transistors receives a signal input. The compound domino logic circuit also includes a logic gate coupled to the precharge transistor to produce a signal output. The logic gate includes at least two transistors connected in series. Further, an adjustment transistor is coupled to a node between the two transistors to ground.

Abstract: A bridge circuit uses active feedback to control drive phase turn on to substantially eliminate shoot-through current. Voltage sensor 66 senses H-bridge transistor voltage turn off levels and causes control circuit 64 to latch which causes enable circuit 62 to allow the next phase of H-bridge transistor turn on. A critical aspect of the invention is to ensure all H-bridge transistors are off before the enable circuit allows the next phase to turn any H-bridge transistors on.