Abstract: An anti-charge share device and method for operation ensure that charge share protection is provided for nodes in a logic circuit during an evaluate stage with low costs in terms of power and circuit performance. The anti-charge sharing device includes a transistor coupled between pre-charge node and a second node being evaluated. By coupling the charge share device between the pre-charge node and the node to be evaluated, operation of the charge share device is dependent upon a node which no longer requires a charge-sharing protection.

Abstract: Output stage with self calibrating slew rate control. An output stage comprising a first (1) and a second (2) supply terminal for receiving a supply voltage (SV); a pre-drive circuit (PDS) coupled to an input terminal (IP) for receiving an input signal (V.sub.i), the pre-drive circuit (PDS) comprising a series transistor (TS) with a control electrode (TS.sub.g) for receiving a control voltage (V.sub.cntrl) for controlling a maximum current from an output (PDS.sub.OUT) of the pre-drive circuit (PDS), and a capacitor (C) for retaining the control voltage (V.sub.cntrl); an output-drive circuit (ODS) for delivering an output signal (V.sub.o) at an output terminal (OP) in response to the input signal (V.sub.i); and a control circuit (CC) for delivering the control voltage (V.sub.cntrl). The output stage further comprises a control circuit (CC) which is coupled between the output terminal (OP) and the control electrode (TS.sub.g).

Abstract: A CMOS driver circuit minimizes a pass-through current flowing from a first voltage terminal to a second voltage terminal during transitions of an input signal. At least two transistors are connected in series between two voltage terminals. One transistor turns off when the input signal transitions from a low logic state to a high logic state. Another transistor turns off when the input signal transitions high-to-low. During either input signal transition, one of the transistors is off, thereby cutting the path between the voltage terminals to reduce or eliminate the pass-through current. The two transistors are controlled by the output of the circuit through a feedback loop. This feedback loop can include a delay element, one transistor controlled by a single synchronizing clock signal, or two transistors controlled by two complementary clock signals. The driver circuit can be used as a building block to provide conventional combination logic functions.

Abstract: Disclosed is a low power consuming logic circuit to restrain a short circuit current which flows within an inverter circuit of an inverter having a clock input connected behind a pass-transistor logic circuit. In the logic circuit, the inverter having a clock input is provided on the output of a pass-transistor logic circuit. The inverter having a clock input includes the inverter circuit and write control means. A data holding circuit is connected to the output of the write control means. In the logic circuit, a clock is input to the inverter having a clock input after the output of the pass-transistor logic circuit is stabilized. Thus, the short circuit current which flows in the inverter circuit is restrained. In addition to the logic circuit, a positive feedback circuit for supplying an inverted signal from the inverter circuit to the output of the inverter having a clock input can be provided.

Abstract: A synchronous differential logic system is provided for implementation of pipelined computational structures capable of hyperfrequency operation. An individual logic circuit has a differential cascode switch and a synchronous sense amplifier which operates as a latch. A plurality of differential inputs are connected to the differential cascode switch which produces complementary signals at first and second nodes. The cascode switch is connected to the synchronous sense latch which provides complementary output signals of the logic circuit. The synchronous sense latch comprises an equalization transistor and two cross-coupled inverters, each connected to first and second power supply buses. The equalization transistor is connected to the first and second outputs, of the logic gate and to a global system clock.

Abstract: A novel zero delay regenerative circuit is presented. The circuit, when connected to a data bus, suppresses noise, reduces time delay and provides sharper edge rates. A first input of a NOR gate is connected to an input node. A second input of the NOR gate is connected to the precharge clock of the bus. The output of the NOR gate is connected to the gate terminate of a field-effect transistor (FET). With the drain terminal connected to ground, the source terminal of the FET is connected to an output node. The input and output nodes are shorted together.

Abstract: A dynamic latch circuit or a dynamic flip-flop circuit of the present invention includes a transfer gate to be controlled by a clock and provided with a complementary configuration using a P-channel and an N-channel MOS (Metal Oxide Semiconductor) transistor. The transfer gate allows the individual node included in the circuit to fully swing between a high potential power source and a low potential power source. This causes a minimum of decrease to occur in an ON current for driving the respective node and thereby realizes high-speed operation. Further, the balance of the rising time and falling time of an output signal is improved, reducing the deviation of the duty of the output signal from 50%. The circuit is therefore operable with sufficient operation margins at positive- and negative-going edges. Consequently, the entire macrocircuit using the circuit of the present invention can have its operation frequency and therefore power consumption lowered.

Abstract: A staticized flop circuit converts a dynamic signal appearing across the output of a logic circuit into a static signal, and includes a dynamic-to-static convertor which minimizes glitching in the static output. The dynamic-to-static convertor includes a pull-down device, operatively coupled between an output node and a ground, which is closed while an input node is at a precharge potential and which is open while the input node is at a ground potential, and a pull-up device, operatively coupled between a source voltage and the output node, which is closed while the input node is at the ground potential and which is open while the input node is at the precharge potential.

Abstract: Disclosed is a circuit for removing noise components included in a signal which an oscillator generates by using an integrator and hysteresis characteristic. The signal is oscillated by an oscillator. A square-wave generating inverter receives a sine wave signal including noise components oscillated by a quartz crystal oscillator circuit and then generates a square-wave signal having improved RC and integrator characteristics, and provides the generated square-wave signal to a Schmitt trigger. The Schmitt trigger receives the square-wave signal including the noise components from the square-wave generating inverter and removes the noise components included in the received square-wave signal. The circuit can remove noise components included in a signal oscillated by an oscillator due to a surrounding influence such as a temperature. Therefore, state clocks which is used in a microprocessor and a microcontroller, may be generated.

Abstract: A data output buffer for a memory device having a memory chip includes a detection unit for detecting an external output data and outputting a detection data, a clock signal adjusting unit coupled to the detection unit for comparing the detection data from the detection unit and a data outputted from the memory chip in accordance with an externally applied clock signal and outputting a first signal and a second signal, and an output buffer unit coupled to the clock signal adjusting unit and outputting a data in accordance with the first signal and the second signal.

Abstract: The present invention is intended to provide a conventional circuit apparatus which is highly tolerant to noises and operates at a higher speed than a completely complementary static CMOS circuit. To achieve this, circuit apparatus according to the present invention is provided with a plurality of CMOS static logic circuits which are series-connected and potential setting means which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore circuit operation is speeded up and .alpha. particle noise and noises due to charge redistribution effect or leakage current can be prevented.

Abstract: A novel precharge circuit is provided for dynamic CMOS logic circuits which are immune to leakage currents and reduce overall power consumption. The circuit comprises a precharge transistor for precharging a node to a high voltage level indicting a first logic state during a standby mode. Thereafter, during an active mode, the node may or may not be discharged by connected logic circuitry. If the node is discharged, then an additional transistor is provided to inhibit the precharging of the already charged node during a subsequent standby mode. Similarly, if the node is not discharged, a small keeper transistor is provided to keep the node at a fully precharged level.

Abstract: A logic circuit comprises an output line, a first switch having an end connected to the output line and another end connected to a power source potential, a second switch having an end connected to the output line and another end connected to a ground potential, and a switching/rectifying circuit, which has an end connected to the output line and another end connected to an intermediate power source potential, for switching/rectifying, in which said intermediate power source potential is higher than the ground potential and lower than the power source potential. With this configuration, said switching/rectifying circuit includes a third switch and a rectifier connected in series.

Abstract: A low slew rate buffer is described. The low slew rate buffer comprises an output pad. A first transistor is coupled to the output pad. The first transistor drives the output pad to a first state when the first transistor is switched on. A second transistor is coupled to the output pad. The second transistor drives the output pad to a second state when the second transistor is switched on. A predriving unit is coupled to the first and second transistors. The predriving unit switches the first transistor off and supplies a staged biasing voltage which gradually turns on the second transistor.

Abstract: In a semiconductor device in which power is supplied from an external power supply system, a first power supply system is connected to first terminals of power supply and ground and a digital inner circuit. The inner circuit includes a clock signal generating circuit, a driver for the clock signal, and circuits operating in response to the clock signal. A second power supply system is connected to second terminals of power supply and ground, the input terminal, the output terminal, and a digital interface circuit. The second power supply system is independent of the first power supply system. The interface circuit includes a MOS transistor for pulling up or down the input terminal and an output circuit which includes a MOS transistor driving an output terminal. The first power supply system is separated from the second power supply system, and the inner circuit is connected to the interface circuit through only signal lines.

Abstract: A semiconductor integrated circuit device has a data selecting circuit connected to a first power supply terminal, a precharge circuit, connected to a second power supply terminal, for receiving a precharge signal, and a wiring line connected to a common connection point between the data selecting circuit and the precharge circuit. The data selecting circuit includes at least two, i.e., first and second data transmission circuits. A first input data signal and a first selecting signal are supplied to the first data transmission circuit. A second input data signal and a second selecting signal are supplied to the second data transmission circuit.

Abstract: An integrated circuit output section has a controller that controls a plurality of drivers to transmit data signals over output lines in a group staggered manner to substantially reduce the generation of inductive noise or ground and power bounce. The controller staggers the transmission of the data signals in each group relative to the other groups to achieve a reduction in inductive noise of greater than 25% using relatively short total staggering times of less than five times the transition switching time of a driver for the groups of data signals. Also, an enhanced reduction in inductive noise is achieved with a total staggering time equal to or less than a driver transition switching time, wherein at least one group has a different number of data signals than the other groups.

Abstract: A tri-state synchronous bus driver avoids contention between succeeding cycles by shutting off each device's output enable early, so that it is guaranteed to no longer drive the line by the time any other device begins to drive. Enable activation occurs on a leading edge of the bus clock, and deactivation occurs at a delayed half phase clock edge. A low current bus holding cell is coupled to each bi-directional line to maintain the driven signal value until it can be sampled by a receiving device. This has the advantages that set up time is not eroded by the technique, and that the disable timing is relatively non-critical. The technique is particularly useful in gate array technology as process, temperature, and voltage variation can cause considerable fluctuation in the actual timing of circuits.

Abstract: A DRAM includes an output terminal, a memory cell array having a plurality of memory cells, a row decoder, a column decoder, an input/output circuit, a data extending circuit, an output buffer circuit, and a control circuit. The data extending circuit extends each data read out from the input/output circuit until a subsequent data is read out. The output buffer circuit responds to the extended data from the data extending circuit for providing output data sequentially to the output terminal. In response to an output control signal provided from the control circuit, the output terminal is set to a high impedance state before each output data is provided from the output buffer circuit.

Abstract: A data input/output sensing circuit of a semiconductor memory device including a plurality of memory cells, the circuit comprises: input/output lines of the memory cell; data input/output terminals connected to outside of the memory cells; a single data input/output line connected between the input/output lines and the data input/output terminals; a sensing unit for sensing whether or not effective data is provided in the data input/output lines to thereby generate a sensing signal; an output driving unit for transmitting data of the data input/output lines to the data input/output terminals in response to the sensing signal; and a writing driving unit for inputting data of the data input/output terminals in response to the sensing signal.

Abstract: The noise from the effects of currents through distributed capacitances between electrical circuitry on an integrated circuit chip and the chip substrate is minimized, especially for analog circuitry mixed on the chip with digital circuitry. The invention separates a plurality of bits in each digital word into a plurality (e.g. 2) of segments. A first register off the chip latches the first bits in each word with a first clock signal. A second register off the chip latches the second bits in each word with a second clock signal delayed from the first clock signal. The first register bits are latched on the chip with the first clock signal by a third register. The delayed second register bits are latched on the chip by a fourth register with the second clock signal or with a delayed first clock signal having the same delay as the second clock signal. Substrate ties for the third and fourth registers may be connected to at least one, preferably a plurality, of bonding pads on the chip.

Abstract: A switching array is formed with a plurality of switches each having an input and an output. The switches are associated with a digital bus, such as an address or data bus, and transfer the values on their inputs to their outputs when a control signal is received. When the switches undergo a transition from a logical value of "1," which is about the supply voltage down to a logical value of "0," which is about the ground potential, the switches produce a load current which is discharged to ground. In a first embodiment, the load current is divided into two parts and discharged to ground at two different times by using switches which have two different speeds. The faster switches will discharge the load current first followed a time later by the second slower group of switches. In a second embodiment, the switches all have the same speed and the control signal is delayed to half of the switches. Thus, the switches receiving a delayed control signal will discharge a load current later than the other switches.

Abstract: A DRAM includes an output terminal, a memory cell array having a plurality of memory cells, a row decoder, a column decoder, an input/output circuit, a data extending circuit, an output buffer circuit, and a control circuit. The data extending circuit extends each data read out from the input/output circuit until a subsequent data is read out. The output buffer circuit responds to the extended data from the data extending circuit for providing output data sequentially to the output terminal. In response to an output control signal provided from the control circuit, the output terminal is set to a high impedance state before each output data is provided from the output buffer circuit.

Abstract: The output signal and control signal from an internal circuit are supplied to a control circuit via an output signal line and a control signal line. The output signal from the control circuit is supplied to a first and second independent output buffer sections via control circuit output signal lines, respectively. The outputs of the first and second output buffer sections are selectively supplied from an output terminal to an external circuit via an output signal line. With this invention, it is possible to selectively use the output buffer sections having an ability according to use. Another semiconductor integrated circuit device comprises an internal circuit, a plurality of output buffers, a control circuit for selectively actuating the output buffers, and a sequential select circuit for sequentially selecting the plurality of output buffers.

Abstract: In an output circuit for driving a load connected to an output terminal in accordance with an input signal input to an input terminal, the output circuit connects to the input and output terminals, a first output buffer which operates when activated; connects in parallel to the first output buffer, a second output buffer which, when activated, operates with driving ability higher than the first output buffer; and activates the second output buffer for a predetermined period when the input signal is input and, after the period, activates the first output buffer.

Abstract: A low-power inverter (53) reduces power consumption over known inverter designs and is especially well-adapted for serving as a buffer in a Pierce crystal oscillator with a large load capacitance. The inverter (53) includes P- and N-side source-follower stages (310, 320) driving CMOS output transistor pairs (350, 360). The source followers are current-limited through current sources (311, 313, 321, 323) which are biased by a stable reference voltage such as a bandgap reference voltage. Clamping devices (331, 332) are provided to limit the voltages on the gates of the output transistors (350, 360), thereby limiting maximum currents thereof. In addition, a helper device (332) is connected to the gate of a P-channel output transistor (350). The P-channel output transistor (350) typically has a large gate area and thus a large capacitance, and the helper device (332) quickly increases the voltage at the gate when an input signal changes to a high voltage.

Abstract: A single-phase clock and an output signal of a second delay circuit are inputted to a first NAND gate and a first NOR gate. The output signal of the first NAND gate is inputted to a gate of a first PMOS transistor of a first clock driver. The output signal of the first NOR gate is inputted to a gate of a first NMOS transistor of the first clock driver. Meanwhile, an inverted clock outputted from an inverter and an output signal of a first delay circuit are inputted to a second NAND circuit and a second NOR circuit. The output signal of the second NAND gate is inputted to a gate of a second PMOS transistor of a second clock driver. The output signal of the second NOR gate is inputted to a gate of a second NMOS transistor of the second clock driver.

Abstract: A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor.