Abstract: A semiconductor device includes a magnetic switch provided on a semiconductor substrate. The magnetic switch includes: a Hall element, first and second power supply terminals; a current source driving the Hall element; a switch circuit switching a differential output voltage supplied from two electrodes of the Hall element to a first or second state based on a control signal supplied from a control terminal; an amplifier amplifying a signal from the switch circuit; a reference voltage circuit generating a reference voltage based on a reference common mode voltage and a control signal; a comparator receiving an output signal of the amplifier and the reference voltage; and a latch circuit latching an output voltage of the comparator. The reference voltage of the reference voltage circuit is controlled by switching from a reference value to a voltage with a high or low adjustment value according to the output voltage of the comparator.

Abstract: Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.

Abstract: An electronic device includes a drive control signal generation circuit and an internal voltage drive circuit. The drive control signal generation circuit detects a level of an internal voltage to generate a drive control signal that adjusts a level of the internal voltage. The internal voltage drive circuit drives the internal voltage based on the drive control signal.

Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.

Abstract: A bias circuit includes a current generating circuit generating a first compensation current and a second compensation current, in which an ambient temperature change is reflected, based on a reference current, a first temperature compensation circuit generating a first base bias current, based on the first compensation current, to output the first base bias current to a base node of an amplifying circuit, and a second temperature compensation circuit generating a second base bias current, based on the second compensation current, to output the second base bias current to the base node of the amplifying circuit.

Abstract: A crystal oscillator circuit comprises: a crystal oscillator; and an injection frequency generating circuit, the injection frequency generating circuit being configured to sense a signal of the crystal oscillator and amplify the sensed signal, the injection frequency generating circuit being further configured to inject the amplified signal to the crystal oscillator; wherein the crystal oscillator circuit is configured such that the crystal oscillator receives the amplified signal during an initial start-up period of the crystal oscillator and stops receiving the amplified signal at an end of the initial start-up period.

Abstract: Computing devices are now used for various purposes ranging from monitoring a refrigerator to driving automobiles. Protecting the data and logic within the chips of the computing devices is essential to ensure reliable operation. When a particular partition of a chip is powered-up but the logic of the partition is not reset, the logic will be in an unpredictable random state. To operate in a secure environment, it is necessary to start the operation of the logic from a known state and not a random state. To ensure the logic is operating in a secure environment, a digital reset detector circuit (DRDC) is provided that indicates if the logic was reset after power-up. The DRDC can ensure chips are secure from attacks involving reset deprivation upon power-up and help protect various secure and secret assets in a chip, including customer keys.

Abstract: A nonvolatile memory apparatus may include a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines. The nonvolatile memory apparatus may include and a resistance compensation circuit configured to generate a compensation resistance value according to a position of a memory cell to be accessed.

Abstract: A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion.

Abstract: A shift register, a driving method, a gate driving circuit and a display device.

Abstract: To reduce power consumption of a shift register. A semiconductor device includes a shift register. The shift register includes a plurality of stages. Any one of the stages includes first to fourth switches and a sequential circuit. The first switch and the second switch are electrically connected to each other in parallel between a first wiring and a second wiring. The third switch and the fourth switch are electrically connected to each other in series between a third wiring and the second wiring. The first wiring has a function of transmitting a clock signal. The third wiring has a function of transmitting a potential corresponding to a high or low level of the clock signal. A signal of the second wiring or a signal in accordance with the signal of the second wiring is input to a sequential circuit.

Abstract: An embodiment relates to a device comprising a high-side semiconductor, a low-side semiconductor, a first sensing element arranged adjacent to the high-side semiconductor. The first sensing element is isolated from the high-side semiconductor and the first sensing element is directly connectable to a processing device.

Abstract: According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes an over-temperature protection circuit configured to reduce current through the power switches based on multiple temperature threshold values of the power switches and a sensed temperature of the power switches. The over-temperature protection circuit can be configured to enter first and second modes based on the multiple temperature threshold values and the sensed temperature, where the second mode reduces current through the power switches to a greater extent than the first mode.

Abstract: Provided herein are apparatus and methods for a variable gain passive attenuator with multiple layer attenuation devices. In certain configurations, at least two rows of stacked FETs are layered in blocks, namely H (horizontal) blocks in a hierarchical schematic representation of the variable gain passive attenuator. Each stack of FETs receives a control signal, and by delaying a second control signal with respect to a first control signal, performance and linearity can be enhanced while insertion loss is reduced.

Abstract: A reference voltage source comprises a bandgap voltage reference circuit having a first node and an output node, the output node being arranged for providing a reference voltage. A curvature correction circuit has an input node connected to the output node and/or to a base of a first bipolar device of the bandgap voltage reference circuit and/or to a base of a second bipolar device of the bandgap voltage reference circuit. The curvature correction circuit has an output node connected to the first node of the bandgap voltage reference circuit. The curvature correction circuit comprises a current source for providing a current having a different temperature dependency than a temperature dependency of a first current through the first bipolar device of the bandgap voltage reference circuit.

Abstract: An Integrated Circuit, a system, and a method are provided. The disclosed Integrated Circuit may include a plurality of pads exposing internal components of the Integrated Circuit to external circuits, a digital interface connectable to the plurality of pads, an analog interface connectable to the plurality of pads, and sensing circuitry configured to detect whether a digital circuit or an analog circuit is externally connected to the plurality of pads and based on such detection selectively connect at least one of the digital interface and analog interface to the plurality of pads.

Abstract: A method for testing an LDMOS transistor by measuring leakage current between the source and drain in the presence of a bias voltage. The leakage current is indicative of defects in the structure of the transistor.

Abstract: Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.

Abstract: A voltage-mode differential driver is disclosed. The differential driver includes two driver arms, each driver arm including a variable-impedance driver for driving a single-ended output signal. Each variable-impedance driver comprises multiple driver slices, where each driver slice includes a pre-driver circuit and a driver circuit. Advantageously, it has been determined that the disclosed voltage-mode driver design requires less power than conventional current-mode drivers. In one implementation, the disclosed voltage-mode driver design provides the capability of independently programming the delay of the two single-ended outputs so as to compensate for differential skew. Other embodiments and features are also disclosed.

Abstract: A load limiting circuit includes a transistor switch, for providing current to a load and a latching circuit having a control input, and a latch output driving the transistor switch. A current sensing transistor interconnects with the transistor switch, to sense current in excess of a threshold to the load. The current sensing transistor drives the control input to the latching circuit. An external controller may drive and monitor the control input. The controller may thus turn the transistor switch on and off, and be notified of an over-current condition. The latching circuit may turn the transistor switch off permanently. As well, the controller may attempt to set the load limiting circuit after an over-current condition.

Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.

Abstract: A system for calibrating impedance of an input/output (I/O) buffer on a semiconductor die includes: the I/O buffer; a temperature sensor on the semiconductor die; and a supply sensor on the semiconductor die. The temperature sensor is configured to acquire temperature information for calibrating the I/O buffer. The supply sensor is configured to acquire voltage information for calibrating the I/O buffer. The I/O buffer comprises: a memory component coupled to the temperature and supply sensors and configured to store the acquired temperature or voltage information; a logic component coupled to the memory component; and a driver with driver legs. The driver is coupled to the logic component. The logic component is configured to generate driver control signals representing an on/off configuration for the driver legs of the driver based at least in part on the acquired temperature information or the acquired voltage information stored in the memory component.

Abstract: There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.

Abstract: Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror that supplies a PVT current (IPVT) to driver bit cells and a proportional mirrored control current (ICNTL) to a current controlled oscillator (CCO), which generates FOSC. The digital section may be used in combination with a frequency variable resistor and beta multiplier connected to the CCO to calibrate the capacitance of the CCO to tune out the process variation of the CCO capacitance and render FOSC to be linearly dependent on ICNTL.

Abstract: Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror that supplies a PVT current (IPVT) to driver bit cells and a proportional mirrored control current (ICNTL) to a current controlled oscillator (CCO), which generates FOSC. The digital section may be used in combination with a frequency variable resistor and beta multiplier connected to the CCO to calibrate the capacitance of the CCO to tune out the process variation of the CCO capacitance and render FOSC to be linearly dependent on ICNTL.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to toggle the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described.

Abstract: An input buffer which includes an amplification circuit configured to amplify a difference between a first input signal and a second input signal; and an inverter configured to invert an output signal of the amplification circuit. The amplification circuit provides the inverter with a bias voltage generated on the basis of one of the first and second input signals, and the inverter operates responsive to the bias voltage.

Abstract: An input buffer includes a first buffer circuit to amplify a difference between a first input signal and a second input signal; a second buffer circuit formed of a replica circuit of the first buffer circuit to generate a common mode output signal in response to the first input signal; and a detector to compare the common mode output signal with a reference output signal and to control the first and second buffer circuits according to the comparison result such that a level of the common mode output signal coincides with a level of the reference output signal.

Abstract: Methods of adjusting a centerline voltage of a data signal are described, along with apparatuses to adjust the centerline voltage. In one such method, portions of a termination circuit coupled to a node are selectively programmed to adjust an impedance of the termination circuit to adjust the centerline voltage of the data signal driven to the node. One such apparatus includes pull-up impedances and pull-down impedances that can be programmed to adjust the centerline voltage of the data signal. Additional embodiments are also described.

Abstract: Variations of the impedance of each output driver of a semiconductor device can be reduced, and high-speed calibration is achieved. A calibration circuit including a replica circuit having the same configuration as each pull-up circuit or pull-down circuit included in an output driver of a semiconductor device is provided within a chip. During a first calibration operation, the replica circuit is provided with voltage conditions that allow the maximum current to flow through the output driver so that an impedance of the replica circuit is equal to a value of an external resistor. During a second calibration operation, table parameters obtained in the first calibration operation are used to adjust the impedance of the output driver without use of the replica circuit.

Abstract: An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

Abstract: A data driving impedance auto-calibration circuit includes: a detection block configured to calibrate a characteristic voltage generated by detecting an operation characteristic variation of an element, according to a code signal, and generate a calibrated characteristic voltage; a comparison block configured to compare the calibrated characteristic voltage with a reference voltage and output a comparison result signal; and a code calibration block configured to calibrate the code signal according to the comparison result signal.

Abstract: The transition frequency of an inverter can vary with the transconductance of its internal transistors as a function of temperature and bias level. To maintain consistent transition frequency across temperatures, and therefore reduce the phase noise variation introduced by the inverter, systems, methods, and circuits are disclosed for biasing the inverter with a temperature varying current such that the transconductance of transistors remains constant across temperatures, while maintaining the lowest possible power consumption to do so. Various embodiments can include using current sources that have proportional-to-absolute-temperature (PTAT) devices.

Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: Some embodiments of the present invention provide a programmable transmitter which includes a set of drivers and one or more chains of configuration registers. Each driver is capable of being configured to perform a transmission function from a predetermined set of transmission functions. Each configuration register can correspond to a driver, and can store configuration data which is used to configure the corresponding driver. The programmable transmitter can include configuration circuitry which serially shifts configuration data into the one or more chains of configuration registers. The programmable transmitter can also include programming circuitry which can determine configuration data for each driver based partly or solely on a desired transmitter behavior.

Abstract: Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.

Abstract: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.

Abstract: In at least some embodiments, an electronic device includes a first data endpoint and differential data transceiver coupled to the first data endpoint. The differential transceiver provides a communication interface between the first data endpoint and a second data endpoint. The differential transceiver compensates for variations in a series impedance and/or a parallel impedance for a differential data line between the differential transceiver and the second data endpoint.

Abstract: The temperature dependence of an inrush current suppression circuit comprising a MOSFET having an input terminal coupled to a direct current input voltage can a transistor electrically coupled to the MOSFET can be reduced by matching the temperature coefficient of a transistor to a component electrically coupled to the transistor.

Abstract: To include a first X decoder constituted by a transistor whose off-leakage current has a first temperature characteristic, a pre-decoder circuit and a peripheral circuit constituted by a transistor whose off-leakage current has a second temperature characteristic, a power supply control circuit that inactivates the X decoder when a temperature exceeds a first threshold during a standby state, and a power supply control circuit that inactivates the pre-decoder and the peripheral circuit when a temperature exceeds a second threshold during the standby state. According to the present invention, whether power supply control is performed on a plurality of circuit blocks is determined based on different temperatures, therefore optimum power supply control can be performed on each of circuit blocks.

Abstract: The invention relates to an interfacing device for pseudo-differential transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention includes signal terminals and a common terminal distinct from the reference terminal (ground). A transmitting circuit receiving the input signals of the transmitting circuit coming from a source delivers, when the transmitting circuit is in the activated state, currents to the signal terminals. A receiving circuit delivers, when the receiving circuit is in the activated state, output signals of the receiving circuit determined each by the voltage between one of the signal terminals and the common terminal, to the destination. A termination circuit is such that, when it is in the activated state, it is approximately equivalent, for the signal terminals and the common terminal, to a network consisting of 4 branches, each branch being connected to the common terminal and to one of the signal terminals.

Abstract: A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer wiring structure and a heat conduction part. The semiconductor element is formed on a support substrate. The multi-layer wiring structure is formed in an insulation film on the support substrate and includes at least one connection hole and at least one metal wiring layer. The heat conduction part is formed of the same conductive materials as the connection hole and the metal wiring layer and extends toward an upper layer side along a path different from a wiring path including a connection hole and a metal wiring for signal transmission.

Abstract: In one embodiment, an apparatus includes a driver and a receiver. The driver has an output, wherein the output of the driver has an associated output termination. In addition, the receiver has an input, wherein the input of the receiver has an associated input termination. An interface between the output of the driver and the input of the receiver operates according to a set of one or more timing parameters, wherein the input termination, the output termination, and the set of timing parameters correspond to a bandwidth for data transfer or frequency for data transfer across the interface between the output of the driver and the input of the receiver.

Abstract: A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

Abstract: In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.