Abstract: The present invention relates to a resistance calibration circuit to correct a resistance variation in an output terminal of a semiconductor device. The resistance calibration circuit according to the present invention includes: a correction code generator for generating a plurality of push-up code signals and a plurality of pull-down code signals based on an external reference resistor, wherein a reference voltage is applied to the correction code generator; a push-up decoder for decoding the plurality of push-up code signals from the correction code generator; a pull-down decoder for decoding the plurality of pull-down code signals from the correction code generator; and a resistance adjustor for receiving a push-up signal from the push-up decoder and a pull-down signal from the pull-down decoder and for turning on/off a plurality of inner transistors.

Abstract: According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the devices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.

Abstract: There is provided an apparatus for generating an input signal for a cable that is mismatched on an output side. The apparatus has a line driver for connecting to an input of the cable via a resistor. The line driver includes a controller that, depending on a data input signal, is for triggering (a) a first switch to apply a supply voltage at an input of the resistor, (b) a second switch to apply a reference potential at the input of the resistor, and (c) a third switch to apply an auxiliary voltage at the input of the cable, all of them at predeterminable points in time, in order to minimize power dissipation in the resistor.

Abstract: Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time characteristics, over a range of PVT variations. In an embodiment, a PVT compensating circuit senses one or more circuit and/or signal characteristics at an output pad or terminal. When the one or more circuit and/or signal characteristics are affected by PVT variations in the IC and/or load, the PVT compensating circuit controls a variable output drive to maintain the one or more circuit and/or signal characteristics within a desired or predetermined range. The PVT compensating circuit is designed to compensate over a range of PVT variations. In an embodiment, the PVT compensating circuit senses a rate of voltage change over time (i.e., dV/dt), of an output signal at the output terminal. During state transitions of the output signal, the output signal is adjusted as needed to maintain a desired, or pre-determined, rate of voltage change.

Abstract: Circuits may provide series on-chip termination impedance to one or more input/output pins. In one embodiment, two off-chip reference resistors in combination with internal calibration circuitry are used to control termination transistors coupled to several input/output (I/O) pins. The termination transistors behave as programmably adjustable termination resistors that match the impedance of external resistors. By using only a small number of reference resistors (e.g., 2 resistors) for a large number of I/O pins, the present invention eliminates the external components that would otherwise be needed to provide resistance termination. The effective series termination resistance may be programmed, enabling the termination resistance to meet different I/O standards. Further, the resistance termination techniques of the present invention are not sensitive to process, voltage supply, and temperature (PVT) variations.

Abstract: A correction circuit for generating a control signal for correcting a characteristic change of a first transistor includes a control signal adjusting section including a constant voltage reduction element for determining either one of a maximum voltage and a minimum voltage of the control signal and a second transistor for determining a characteristic of the control signal, a gate electrode of the second transistor receiving a prescribed voltage; and a resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The constant voltage reduction element, the second transistor, and the resistor section are connected in series between a supply terminal and a ground terminal. The control signal is output from a connection point between the control signal adjusting section and the resistor section.

Abstract: A system and method of terminating signals are described. In one embodiment, the termination system of the present invention comprises a receiver for receiving a signal from a transmission line, a termination node, a resistive element disposed between the receiver and the termination node, and a termination voltage controller for changing the voltage level of the termination node, in response to the detected signal voltage level. In another embodiment, the present invention includes a method of adaptively terminating a signal. The method of this embodiment comprises detecting the voltage level of a signal, selecting the termination voltage level of a termination node in response to the detected signal voltage level, and terminating the signal, through a resistive element, at the selected termination voltage level.

Abstract: A method of providing a constant current drive to a driver circuit (40) in a compensating bias circuit (10) includes the steps of providing a constant current source insensitive to process, supply voltage, and temperature variations and mirroring the constant current source to the driver circuit while adding no sensitivity to process, supply voltage, and temperature variations.

Abstract: A circuit and method for calibrating an active termination resistor irrespective of changes in process, voltage, or temperature is provided. The method includes the steps of (a) calibrating a first variable resistor to have the same resistance as that of an external resistor; (b) at the same time calibrating a second variable resistor to have the same resistance as that of the first variable resistor; and (c) calibrating the active termination resistor to have the same resistance as that of the external resistor. The step of calibrating the first variable resistor to have the same resistance as that of the external resistor is in response to a first control code, and at the same time the step of calibrating the second variable resistor to have the same resistance as that of the first variable resistor is in response to a second control code.

Abstract: Various apparatuses and methods are described that include a variable-impedance matched termination pair coupled to differential signaling bus pair. In an embodiment, the differential signaling bus pair includes a first bus and a second bus. The variable-impedance matched termination pair includes a first variable-impedance component and a second variable-impedance component. The impedance value of each variable-impedance component depends on the voltage level sensed by that variable-impedance component. The first variable-impedance component couples to the first bus. The second variable-impedance component couples to the second bus. The first variable-impedance component is electrically isolated from the second variable-impedance resistor.

Abstract: Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time characteristics, over a range of PVT variations. In an embodiment, a PVT compensating circuit senses one or more circuit and/or signal characteristics at an output pad or terminal. When the one or more circuit and/or signal characteristics are affected by PVT variations in the IC and/or load, the PVT compensating circuit controls a variable output drive to maintain the one or more circuit and/or signal characteristics within a desired or predetermined range. The PVT compensating circuit is designed to compensate over a range of PVT variations. In an embodiment, the PVT compensating circuit senses a rate of voltage change over time (i.e., dV/dt), of an output signal at the output terminal. During state transitions of the output signal, the output signal is adjusted as needed to maintain a desired, or pre-determined, rate of voltage change.

Abstract: The disclosure presents a device comprising a driver configured to transmit a signal on a bus line, including a driver element configured to pull against termination impedance. The impedance of the driver element is dynamically adjustable. The disclosure also presents a method of electronically adjusting the impedance of the driver element to regulate the swing voltage on the bus line.

Abstract: Edge rates for output driver transistors are increased for slower conditions such as caused by supply-voltage, temperature, and process variations. The edge rates are increased by increasing charging and discharging currents to the gates of the driver transistors. Process-sensing transistors have gates tied to power or ground. Current through the process-sensing transistors changes with supply-voltage, temperature, and process variations. The currents through process-sensing transistors are used to generate process-compensated voltages that bias current sources and sinks to adjust process-dependent currents. Process-independent or fixed current sources and sinks use process-independent reference voltages ultimately generated from reference currents that are not sensitive to process variations. The process-dependent-currents are subtracted from the fixed currents to produce the charging and discharging currents.

Abstract: A method and system for high speed bussing in microprocessors and microelectronic devices is disclosed. The method and system implement a type of differential bus with distributed bus pre-charge units designed to decrease bus pre-charge time. The method and system utilize a universal self-tracking clock signal to determine the minimum required bus pre-charge time. The time saved by decreasing the bus pre-charge time can be directly applied to the bus evaluation period thereby increasing system performance and reliability.

Abstract: A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by adjusting the source resistance of the pre-drive devices to generate a slew-controlled pre-drive signal for driving the output drive devices.

Abstract: Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time characteristics, over a range of PVT variations. In an embodiment, a PVT compensating circuit senses one or more circuit and/or signal characteristics at an output pad or terminal. When the one or more circuit and/or signal characteristics are affected by PVT variations in the IC and/or load, the PVT compensating circuit controls a variable output drive to maintain the one or more circuit and/or signal characteristics within a desired or predetermined range. The PVT compensating circuit is designed to compensate over a range of PVT variations. In an embodiment, the PVT compensating circuit senses a rate of voltage change over time (i.e., dV/dt), of an output signal at the output terminal. During state transitions of the output signal, the output signal is adjusted as needed to maintain a desired, or predetermined, rate of voltage change.

Abstract: A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the OCD to be varied to match the impedance of a driven load. A plurality of PFET and NFET finger selection devices are used to select various combinations of output FETS and ballast resistor finger combinations to drive an output signal at a desired impedance level. The ballast resistors are scaled in ohmic value to the size of the output finger it is connected to. In this configuration, a constant ratio of FET impedance to ballast resistance is maintained in each drive stage (finger). By selecting various combinations of fingers various driver impedances can be selected.

Abstract: A device and method that adjust data due to temperature variations is disclosed. The data is captured in a multi-stage delay line. A first controller parses the data and identifies an Edge1 value and an Edge2 value for bits in the delay line. The edge values are used to generate signals that set a Multiplexer 1 (MUX1) and a Multiplexer 2 (MUX2) to select bits from the delay line. A second controller processes an edge sample from bits in the delay line to determine if the data has shifted in the delay line relative to the current multiplexer settings. An edge sample is a snapshot of the delay line values. The new edge values generated by the second controller are selectively filtered and integrated with initial edge values to generate new settings for the MUX1 and MUX2.

Abstract: An output driver of a semiconductor integrated circuit having low power consumption and reduced layout area transmits internally generated data of the circuit to pads responsive to clock signals, and is controlled by control signals indicative of changes of process, voltage, and temperature. The output driver includes a data selector, an output driver enabler, a first driver that transmits an output of the output driver enabler to the pads, and a second driver that includes a data delay having a plurality of inverters connected in series to an output of the output driver enabler and being activated responsive to the control signals. The second driver transmits an output of the data delay to the pads. The output driver reduces a load on the clock signal line, so that power consumption and a layout area can be reduced.

Abstract: A circuit configured to match an impedance of a first pin and a second pin coupled to a transmission line. A resistor configured to match a resistance of the transmission line across the first and second pins and provide a voltage level independent of process corner and temperature variation. The voltage swing of the differential buffer generally has less sensitivity to variation in load resistor value.

Abstract: A voltage-boosting generator for reducing the effects due to operating voltage variation and temperature change. The generator comprises a delay line circuit and a voltage boosting circuit. The delay line circuit is used to perform a time delay according to an initial boosting signal and to produce a control signal. The voltage boosting circuit is used to boosted voltage according to the control signal.

Abstract: A compensated driver for maintaining constant impedance during data transfer from an integrated circuit comprises an output portion having an output device to transfer data from the integrated circuit and a mimic circuit portion having a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A mimic circuit portion has a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A differential amplifier portion is adapted to generate a control voltage in response to a reference voltage and the sample voltage. A predrive portion applies either a ground or the predetermined control voltage from the differential amplifier portion to the output stage portion in response to an input, the control voltage regulating the output device in the output stage portion to achieve a more constant impedance.

Abstract: Controlling the common mode impedance for a circuit, conductor, or multiple conductor cable by incorporating the circuit or conductor into the primary of a transformer. The secondary of the transformer is coupled to a secondary impedance selected so that the desired impedance is obtained. A capacitive shunt may be added to buffer the intrinsic primary impedance. The intrinsic impedance of a conductive antenna structure is controlled by deploying a portion of the antenna structure as the primary of a transformer and coupling the secondary of the transformer to a selectable secondary impedance.

Abstract: An adaptive impedance matching arrangement has an adaptive impedance circuit and a control circuit. The adaptive impedance circuit matches the impedance of a bus and is controlled according to control bits supplied by the control circuit. The control bits are updated according to a signal indicating the state of a queue maintaining transactions for the bus.

Abstract: A pad calibration circuit with on-chip resistor. An integrated circuit with an impedance terminated output terminal is disclosed. A source is provided for sourcing current to the output terminal of the integrated circuit, which output terminal interfaces with a load having a finite impedance associated therewith. An on-chip source impedance is disposed internal to the integrated circuit and between the source and the output terminal to define the input impedance of the output terminal.

Abstract: In one embodiment, a driver impedance control mechanism is adapted for a circuit board. The driver impedance control mechanism comprises (i) an integrated circuit including at least one driver circuit operating as a pull-up driver and a pull-down driver, (ii) a link coupled to an interface pin of the integrated circuit, the interface pin receiving signals from the at least one driver circuit, and (iii) a single resistive element terminating the link and separately compensating the at least one driver when operating as the pull-up driver and the pull-down driver and supplying the same impedance control bits to all driver to have good signal quality over the interface.

Abstract: An impedance adjustment circuit achieves impedance matching between a terminal resistor in a reception-side semiconductor device and a transmission line. A reference resistor has a first resistance proportional to characteristic impedance of the transmission line. This reference resistor is external to the reception-side semiconductor device. Furthermore, the terminal resistor includes a resistor having a second resistance and an ON resistance of an MOS transistor. The resistance of the terminal resistor is adjusted by referring to the reference resistor.

Abstract: An impedance controller comprises impedance control logic outputting an adjustable impedance and a comparator comparing the adjustable impedance with a reference voltage. The impedance control logic recalibrates said adjustable impedance only when said comparator indicates a change in impedance.

Abstract: A configuration for protecting an integrated circuit against over-temperature conditions is described. The configuration has at least one detector device, which identifies a disturbance situation of the integrated circuit, at least one temperature sensor, which detects the temperature of at least one part of the integrated circuit, and a logic device. The logic device ascertains a disturbance mode in dependence a detected disturbance situation and/or the detected temperature and which allocates a first temperature switching stage to the temperature sensor in the normal mode and allocates a second, lower temperature switching stage to the temperature sensor in the disturbance mode. Furthermore, the invention relates to an integrated circuit having such a configuration and also to a method for protecting an integrated circuit against over-temperature conditions.

Abstract: A voltage-boosting generator for reducing the effects due to operating voltage variation and temperature change. The generator comprises a delay line circuit and a voltage boosting circuit. The delay line circuit is used to perform a time delay according to an initial boosting signal and to produce a control signal. The voltage boosting circuit is used to boosted voltage according to the control signal.

Abstract: An input buffer having a stable trip point over at least process skew and supply voltage variations includes a first inverter stage; a second inverter stage; and an arrangement for compensating for process skew and supply voltage variations. The compensating arrangement is disposed both in the pull-up and pull-down paths, and increases the conductivity of the pull-up path and decreases the conductivity of the pull-down path when the DC trip point of the input buffer falls below nominal. The compensating arrangement also decreases the conductivity of the pull-up path and increases the conductivity of the pull-down path when the DC trip point rises above nominal. The compensating arrangement may include at least one device disposed in each of the pull-up and pull-down paths. The conductivity of these devices may then be controlled by a reference signal that swings about the DC trip point responsive to at least process skew corners and variations in supply voltage.

Abstract: A circuit configured to match an impedance of a first pin and a second pin coupled to a transmission line. A first resistor is generally coupled to the first pin and a second resistor is generally coupled to the second pin. The first and second resistors may be coupled to a common node to provide an output voltage level independent of process corner and temperature variation.

Abstract: A binary weighted thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit. The driver circuit includes an impedance network comprising a plurality of resistive devices each programmably electrically connectable in parallel between a first voltage source and the signal pad. The resistive devices are partitioned into a plurality of sets. A first set of the resistive devices may be programmed in a binary incremental manner to electrically connect one or more of the resistive devices in the first set between the first voltage source and the signal pad. Only if all of the resistive devices in the first set are activated may a second set of the resistive devices be programmed in a binary incremental manner. Additional sets of the resistive devices may be likewise programmed only after all of the resistive devices in the previously programmed sets are activated.

Abstract: A current mirror type bandgap reference voltage generator which can reduce variations of a reference voltage due to temperature variations, by separately generating a current proportional to an emitter-base voltage and a current proportional to a thermal voltage, and which also can reduce variations of the reference voltage due to variations of a power voltage, by using a current mirror. The current mirror type bandgap reference voltage generator includes: a first current generator for generating a first current proportional to the emitter-base voltage; a second current generator for generating a second current proportional to the thermal voltage; and a reference voltage generator for adding the first and second currents, and generating a constant reference voltage regardless of variations of the temperature and the power voltage. As a result, the constant voltage is generated regardless of variations of the temperature and the power voltage.

Abstract: A multiple-bit digital attenuator with improved frequency response and reduced insertion loss characteristics is provided. The multiple-bit digital attenuator comprises at least one 2-bit digital attenuator. The 2-bit digital attenuator includes a single series switching transistor located between a first terminal and a second terminal and controllable by a reference control signal, a temperature compensation circuit placed in parallel with the series switching transistor and including two temperature compensation transistors, a pair of first shunt circuits located at the first and second terminals and controllable by a first bit control signal, and a second shunt circuit located between the two temperature compensation transistors and controllable by a second bit control signal.

Abstract: The invention relates to a compensation circuit for driver circuits having a current reference source which generates at least one reference signal which is modulated with respect to an input signal, having a current-comparison source which generates at least one comparison signal which is modulated with respect to the input signal, the modulated comparison signals having an inverse characteristic to that of the modulated reference signals in respect of the parameters to be modulated, having a comparison unit to which the modulated reference signals and the modulated comparison signals are fed and which generates from a comparison of these modulated modulating signals at least one digital output signal which can be fed to driver circuits connected downstream.

Abstract: A circuit for evaluating electrical signals having a programmable adjustment is described. The circuit includes an analog output for signals that have been evaluated which can be used to program the adjustment.

Abstract: A configuration for protecting an integrated circuit against over-temperature conditions is described. The configuration has at least one detector device, which identifies a disturbance situation of the integrated circuit, at least one temperature sensor, which detects the temperature of at least one part of the integrated circuit, and a logic device. The logic device ascertains a disturbance mode in dependence a detected disturbance situation and/or the detected temperature and which allocates a first temperature switching stage to the temperature sensor in the normal mode and allocates a second, lower temperature switching stage to the temperature sensor in the disturbance mode. Furthermore, the invention relates to an integrated circuit having such a configuration and also to a method for protecting an integrated circuit against over-temperature conditions.

Abstract: The invention relates to a circuit of which the operating rate varies according to temperature, supply voltage and intrinsic quality of the transistors of the circuit, associated to a compensating circuit which comprises a constant current source (26) that produces a substantially constant current which is independent of temperature, supply voltage and intrinsic quality of the transistors of the circuit, a variable current source (28) producing a current that increases in an inverse proportion to temperature, supply voltage and intrinsic quality of the transistors of the circuit, and means for decreasing the operating rate of the circuit when the difference of the currents produced by the first and second sources increases.

Abstract: In the present semiconductor integrated circuit device, a buffer is provided between a constant-current source circuit and an internal circuit that becomes a source of noise. The buffer controls the potential of an output node such that the potential of the output node becomes the bias potential. Even when noise is generated on the bias potential line when the internal circuit is in operation, the buffer dampens the noise. Thus, the noise generated in the internal circuit is prevented from adversely affecting the constant-current source circuit, and a stable operation of the internal circuit itself is achieved.

Abstract: A buffer circuit includes a delay circuit which is interposed between a signal source and a following circuit. The delay circuit propagates a signal from an input to an output; the signal has associated desired timing relationships between its rising and falling edges. The delay circuit controls the propagation delays of the signal's rising and falling edges such that when the signal arrives at a selected downstream node, it has the desired timing relationships. The delay circuit adjusts the propagation delays in accordance with two correction signals: one which reduces errors induced by imperfections in the signal path through which the test signal propagates, and one to reduce errors due to thermal effects that arise when propagating a periodic test signal having a duty cycle other than 50% through the signal path.

Abstract: A configuration and a method for matching output drivers of integrated circuits to specified conditions include parameters to be taken into account when matching output drivers and/or control signals based on the parameters for matching the output drivers, to be provided in digital form. The configuration and method may additionally or alternatively perform matching by taking into account a level or waveform of a supply voltage of an integrated circuit and/or a technology used in the integrated circuit and/or technical data on a load to be driven and/or demands placed on the output drivers by the load to be driven.

Abstract: A method of controlling impedance of a driver capable of launching signals at a driving end of a transmission line and capable of terminating signals at the receiver end of the transmission line controls the impedance of the driver across process, voltage, and temperature (PVT) variations by selectively enabling and disabling at least one of a plurality of output elements according to an impedance control code. The impedance control code compensates for variations in output impedance due to PVT variations.

Abstract: In accordance with one embodiment of the invention, a system includes an integrated circuit that has a compensation value generator. The compensation value generator processes multiple compensation values to generate a compensation value that may be used by compensation circuitry.

Abstract: A bus driver circuit includes a diode, a resistor, a constant voltage source, a constant voltage comparing circuit, the first output buffer circuit, the second output buffer circuit. An anode of the diode is connected to a power source, whereas a cathode thereof is connected to an end of the resistor. The other end of the resistor is connected to the ground. The constant voltage source applies, to the voltage comparing circuit, a reference voltage, which is substantially identical with a voltage of the cathode included in the diode when a temperature of the first output buffer circuit becomes a temperature Tcr at which a ringing event occurs in an output signal from the bus driver circuit. The voltage comparing circuit compares the reference voltage and the voltage of the cathode. The voltage comparing circuit outputs a control signal to the first output buffer circuit in accordance with the compared result.

Abstract: A voltage adjusting circuit includes a reference voltage generator generating a reference voltage, a differential amplifier comparing the reference voltage with a distribution voltage, and compensating for a variation of the reference voltage, and a voltage divider dividing a power supply voltage and generating a constant output voltage according to an output from the differential amplifier.

Abstract: An apparatus and method for controlling the power consumption of a logic device are implemented. The power dissipation, and consequently, the speed of a complementary metal oxide semiconductor (CMOS) logic device is substantially proportional to the speed of the device. The temperature of the logic device is controlled by controlling the device speed by adjusting the threshold voltage of the metal oxide semiconductor (MOS) devices forming the logic device under control. The threshold voltage of the devices is controlled by applying a back bias voltage between the bulk material in which each device under control is fabricated, and the most positive electrode of the device. The back bias voltage value is regulated in response to the logic device temperature, thereby closing a feedback loop.

Abstract: An analog process/voltage/temperature (PVT) compensated buffer includes a differential amplifier providing a first output signal indicative of a difference between an input signal and a reference signal. The input signal is compatible with a first type of logic. An active gain stage is coupled to translate the first output signal to a second output signal. The second output signal is compatible with a second type of logic. The differential amplifier and the active gain stage are coupled to receive a process/voltage/temperature (PVT) compensation signal. In one embodiment, the first type of logic is Gunning Transceiver Logic (GTL) and the second type of logic is complementary metal oxide semiconductor (CMOS) logic.

Abstract: A programmable variable impedance output driver circuit uses analog biases to match driver output impedance to load input impedance. A current mirror is used to obtain a measurement of an external resistance value for matching the impedance of a driven load. The mirrored current generates the voltage "NBIAS" when passed through the resistively connected NFET. Similarly, the current is again mirrored and passed through a resistively connected PFET resulting in the voltage "PBIAS". The analog bias voltages, NBIAS and PBIAS are used to vary the impedance of complementary FETs in an impedance matched driver for a high degree of dI/dt control. The driver provides a high degree of flexibility because its turn-on and turn-off characteristics do not depend on a combination of digital control signals connected directly to the driving FETs as in the prior art.

Abstract: A high-speed SCSI input receiver has separate high and low level input buffers, each operating in response to a control voltage that conditions their respective high and low level switching threshold voltages to remain stable about their design values without regard to temperature and process parameter variations. Each of the input buffers includes an input invertor with n-channel and p-channel current source transistors coupled between the output and the respective supply rails. A master circuit includes circuitry that substantially matches the operative circuitry of the input buffer, except that the input and output of the master circuit's invertor element are coupled together so as to define the elements actual switching threshold voltage. This threshold voltage is compared to a design threshold voltage defined by a resistor divider in a comparator.