Temperature Compensation Patents (Class 326/32)
-
Patent number: 7902859Abstract: Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wherType: GrantFiled: October 15, 2009Date of Patent: March 8, 2011Assignee: STMicroelectronics S.A.Inventors: Nicolas Ricard, Laurent Jean Garcia
-
Patent number: 7902861Abstract: An integrated circuit comprising a plurality of CMOS modules (10) connected in series with each other, each module (10) being connected between first and second reference lines (Vdd, Vss). A first transistor (54) is provided between at least one of the modules (10) and the first reference line (Vdd) and a second transistor (52) is provided between one of the modules (10) and the second reference line (Vss) and capacitors (C25, C26) are provided in parallel with the transistors (52, 54) such that they are driven as current sources (I1, I2). As a result power dissipation and leakage current is reduced.Type: GrantFiled: November 8, 2005Date of Patent: March 8, 2011Assignee: NXP B.V.Inventor: Mart Coenen
-
Patent number: 7898289Abstract: A transmission circuit includes a plurality of transmission lines connected in a ring to propagate signals among a plurality of devices. The plurality of transmission lines have a predetermined same propagation delay, and a predetermined transmission line impedance, and the predetermined transmission line impedance is a half or less of an output impedance of each of the plurality of devices. When a signal outputted from a first optional one of the plurality of devices is propagated to the plurality of devices other than the first optional device, the signal outputted from the first optional device exceeds a predetermined threshold of a signal voltage at a same time.Type: GrantFiled: June 18, 2009Date of Patent: March 1, 2011Assignee: Renesas Electronics CorporationInventor: Tsuyoshi Oono
-
Patent number: 7868653Abstract: According to one embodiment, a clock supply apparatus according to one embodiment of the invention includes a first transmission line connected to a clock generator that generates clock signals, a second transmission line connected to a clock supply destination having input impedance different from output impedance of the clock generator, a capacitor that capacitively couples the first and second transmission lines, a pull-up resistor that is provided on the first transmission line to suppress reflection of the clock signal, and a pair of voltage divider resistors that apply potential obtained by voltage division to the second transmission line as a reference potential of the clock signal. The impedance of the pair of voltage divider resistors on the second transmission line is set to match the input impedance of the clock supply destination.Type: GrantFiled: December 14, 2009Date of Patent: January 11, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hiroaki Komaki
-
Patent number: 7859297Abstract: Disclosed in various embodiments are a circuit and method for driving a signal. In one embodiment, the circuit includes a passive impedance conversion network and at least two signal drivers coupled to the passive impedance conversion network. Each of the signal drivers includes a signal input coupled to a common signal input node.Type: GrantFiled: January 27, 2009Date of Patent: December 28, 2010Assignee: Mindspeed Technologies, Inc.Inventor: Wim F. Cops
-
Patent number: 7855573Abstract: A terminator for a CAN bus includes an electronic relay and a termination impedance. The electronic relay has first and second control input conductors and switched output conductors. The electrical connection between the switched output conductors is normally closed. The first control input conductor is connected to the power conductor and the second control input conductor is connected to a fifth terminal of the first CAN bus connector. The termination impedance is connected in series at the end node of the CAN bus with the switched output conductors across the high data conductor and the low data conductor. By this arrangement, the termination impedance is effectively connected across the high data conductor and the low data conductor at the end node of the CAN bus until an extension of the CAN bus is plugged into the first CAN bus connector. When an extension of the CAN bus is plugged into the first CAN bus connector, the fifth terminal of the CAN bus connector is connected to the ground conductor.Type: GrantFiled: December 14, 2009Date of Patent: December 21, 2010Assignee: Caterpillar Trimble Control Technologies LLCInventor: Jerald Wayne Yost
-
Patent number: 7843213Abstract: A memory device is coupled to a subset of lines of a data input/output (I/O) bus. The memory device includes an on-die active termination circuit for terminating the subset of lines of the data I/O bus with a selected impedance being one of a plurality of selectable impedances; a termination value register being coupled to the on-die active termination circuit for storing a value representing the selected impedance; and a termination value setting circuit being coupled to the termination value register, for setting the value representing the selected impedance in the termination value register.Type: GrantFiled: May 21, 2009Date of Patent: November 30, 2010Assignee: Nanya Technology Corp.Inventors: Peter Linder, Jeffrey Eldon Johnson, James Sanford Wallace
-
Patent number: 7834657Abstract: An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output.Type: GrantFiled: January 12, 2010Date of Patent: November 16, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Sunny Arora, Mukesh Bansal, Dipesh K. Gupta, Ankesh Jain, Gaurav Jain, Ritika Singh
-
Patent number: 7830168Abstract: The temperature dependence of an inrush current suppression circuit comprising a MOSFET having an input terminal coupled to a direct current input voltage can a transistor electrically coupled to the MOSFET can be reduced by matching the temperature coefficient of a transistor to a component electrically coupled to the transistor.Type: GrantFiled: February 9, 2009Date of Patent: November 9, 2010Assignee: Rantec Power Systems, Inc.Inventor: Ethan Beck Newman
-
Patent number: 7825681Abstract: A common module for a double data rate-synchronous II synchronous dynamic random access memory (DDRII SDRAM) and a DDRIII SDRAM applied in a computer is provided. The common module includes a first bus, a termination circuit card, a first slot, and a second slot. The first bus transmits a plurality of signals. The termination circuit card comprises a plurality of termination resistors. The first slot is disposed on the common module and coupled to the first bus. The DDRII SDRAM is installed in the first slot. The second slot is disposed on the common module and coupled to the first bus. The DDRIII SDRAM or the termination circuit card is installed in the second slot. When the DDRII SDRAM is installed in the first slot, the termination circuit card is installed in the second slot.Type: GrantFiled: June 25, 2007Date of Patent: November 2, 2010Assignee: Giga-Byte Technology Co.Inventors: Chin-Hui Chen, Hou-Yuan Lin
-
Patent number: 7821292Abstract: An impedance calibration period setting circuit includes a command decoder and an impedance calibration activation signal generator. The command decoder combines external signals to generate a refresh signal. The impedance calibration activation signal generator is configured to generate an impedance calibration activation signal in response to the refresh signal and an address signal. The impedance calibration period setting circuit prevents abnormal changes in an impedance calibration code and reduces current consumption.Type: GrantFiled: June 29, 2009Date of Patent: October 26, 2010Assignee: Hynix Semiconductor Inc.Inventors: Ji Yeon Yang, Dong Uk Lee
-
Patent number: 7804322Abstract: An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transistors have a common conduction terminal connected to an output terminal of the output buffer. An input terminal of the buffer is connected to control terminals of the transistors of the first stage through a first open loop driving circuit. A second feedback driving circuit is connected between the input terminal and the control terminals of the transistors of the second stage. The second feedback driving circuit includes a current detector operating to detect a maximum in the value of the current drawn by and supplied to the output buffer. A comparison block, having a threshold value, detects current in excess of the threshold value and processes information coming from the current detector to regulate an output impedance value of the output buffer.Type: GrantFiled: October 30, 2008Date of Patent: September 28, 2010Inventors: Michele Bartolini, Pier Paolo Stoppino, Paolo Pulici, Gian Pietro Vanalli
-
Patent number: 7795902Abstract: An integrated circuit device includes an output buffer having a capacitance circuit configurable in a slew rate configuration or a decoupling configuration. In the slew rate configuration, the capacitance circuit electrically couples a capacitor of the capacitance circuit in a feedback path for reducing a slew rate of a buffered output signal generated by the output buffer. In the decoupling configuration, the capacitance circuit electrically couples the capacitor between a power potential and a ground potential of the output buffer for increasing power noise immunity of the output buffer. The output buffer may have more than capacitance circuit, each of which is individually configurable into the slew rate configuration or the decoupling configuration.Type: GrantFiled: July 28, 2009Date of Patent: September 14, 2010Assignee: Xilinx, Inc.Inventor: Anitha Yella
-
Patent number: 7791368Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply. The circuit includes a PVT detector configured to generate a control signal and an adjustable resistance device configured to adjust its resistance in response to the control signal.Type: GrantFiled: February 5, 2008Date of Patent: September 7, 2010Assignee: Agere Systems Inc.Inventors: Kouros Azimi, Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith
-
Patent number: 7791367Abstract: An integrated circuit is configured to be in a calibration mode of operation to establish a desired output impedance of a driver circuit. A predetermined constant voltage is established at a circuit node within the integrated circuit. A calibration current is conducted through a transistor connected in series with a variable value resistance in the integrated circuit at the circuit node. A resistance value of the variable value resistance is varied to establish a value of the calibration current which establishes the desired output impedance. The calibration mode is exited and a functional mode is entered. A calibrated resistance value is used during the functional mode of operation. The calibration current is conducted as a calibrated current through the transistor and calibrated resistance value. Variation of the calibrated current is corrected in response to voltage and process variations to maintain the calibrated current and output impedance of the driver circuit.Type: GrantFiled: June 5, 2009Date of Patent: September 7, 2010Assignee: Freescale Semiconductor, Inc.Inventor: Perry H. Pelley
-
Patent number: 7728619Abstract: An improved circuit and method for programmable cascading of impedance matching in a multi-chip configuration are disclosed. Handshaking is implemented in cascaded chips by defining a master-slave configuration, and impedance is evaluated in cascaded chips in a non-overlapping manner. The circuit includes a plurality of chips arranged in a cascading configuration. A cascade output pin of a chip is coupled to a cascade input pin of a cascaded chip to enable handshaking between the plurality of chips. The plurality of chips are coupled to a common precision resistor via a common impedance line to enable each chip to calibrate impedance of the chip. Each of the plurality of chips includes a control circuit. Each control circuit includes a state machine circuit. The control circuit is configured to control a non-overlapping clock cycle of each chip during which the impedance of the chip is evaluated.Type: GrantFiled: March 31, 2008Date of Patent: June 1, 2010Inventors: Joseph Jengtao Tzou, Suresh Parameswaran, Thinh Dinh Tran
-
Patent number: 7724026Abstract: An integrated circuit has a differential I/O buffer (102) capable of being operated in a single-ended mode. The I/O buffer includes circuitry (114 or 112) for reducing leakage current between the differential I/O pins (P, N) when an undershoot event occurs on a pin when operated single-ended mode. In one case, a differential termination circuit (114, 200) includes a differential termination isolation circuit (202) that isolates the termination load (201) and termination load switch (208) from the single-ended pin. Alternatively or additionally, a differential output driver (300) of the I/O buffer switches a common bias voltage (ncom) to a supply voltage (VCOO) in single-ended mode to insure the transistors (A2, B1) in the driver legs remain OFF during an undershoot event.Type: GrantFiled: November 12, 2008Date of Patent: May 25, 2010Assignee: Xilinx, Inc.Inventor: Sing-Keng Tan
-
Patent number: 7714608Abstract: In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.Type: GrantFiled: February 12, 2009Date of Patent: May 11, 2010Assignee: Lattice Semiconductor CorporationInventors: Mou C. Lin, William B. Andrews, John A. Schadt
-
Patent number: 7715249Abstract: An output driver of a semiconductor memory apparatus comprises a voltage dividing block configured to generate divide voltages by dividing an internal voltage, a threshold voltage detecting block configured to generate a detecting voltage corresponding to a change in a threshold voltage of a transistor, a drive capability control signal generating block 300 configured to generate a compare signal by comparing the levels of the detecting voltage with the divide voltage and generate a control signal in response to an input signal when the compare signal is enabled, and a drive capability controlling block comprising a driver configured to perform a driving operation in response to the input signal, and a control driver configured to perform a driving operation in response to the control signal.Type: GrantFiled: July 8, 2008Date of Patent: May 11, 2010Assignee: Hynix Semiconductor Inc.Inventor: Byung-Deuk Jeong
-
Patent number: 7696777Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.Type: GrantFiled: October 15, 2008Date of Patent: April 13, 2010Assignee: MOSAID Technologies IncorporatedInventor: Yehuda Binder
-
Patent number: 7696778Abstract: Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.Type: GrantFiled: January 16, 2009Date of Patent: April 13, 2010Assignee: Micron Technology, Inc.Inventors: Raghu Sreeramaneni, Vijay Vankayala, Greg Blodgett
-
Patent number: 7675326Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.Type: GrantFiled: June 27, 2008Date of Patent: March 9, 2010Assignee: Altera CorporationInventors: Mei Luo, Sergey Shumarayev, Wilson Wong, Chong H. Lee
-
Patent number: 7671622Abstract: On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down mode, and transfer the on/off control signal as received without delay in a power-down mode, a power-down delay configured to delay the on/off control signal in the power-down mode, and not to delay the on/off control signal in the non-power-down mode and a controller configured to control enabling/disabling of an on-die-termination operation according to information about enable/disable timing of an on-die-termination operation provided by the on/off control signal that have passed through the shift register and the power-down delay.Type: GrantFiled: June 9, 2008Date of Patent: March 2, 2010Assignee: Hynix Semiconductor Inc.Inventors: Seung-Min Oh, Ho-Youb Cho
-
Patent number: 7663397Abstract: A semiconductor device according to example embodiments that may include an on-die termination (ODT) control circuit having a pipe line structure which changes in response to a frequency of a clock signal and a termination resistance generator for generating termination resistance in response to a termination resistance control signal.Type: GrantFiled: December 27, 2007Date of Patent: February 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong Suk Yang, Jin Ho Ryu
-
Patent number: 7663399Abstract: An output driver for use in a semiconductor memory device includes a pull-up metal oxide semiconductor (MOS) transistor for pulling-up a voltage loaded on an output node in response to a pull-up control signal; a pull-up linear element connected between the pull-up MOS transistor and the output node for increasing a linearity of an output current; a pull-down MOS transistor for pulling-down the voltage loaded on the output node in response to a pull-down control signal; and a pull-down linear element connected between the pull-down MOS transistor and the output node for increasing the linearity of the output current, wherein the pull-up MOS transistor and the pull-up linear element are different typed MOS transistors and the pull-down MOS transistor and the pull-down linear element are different typed MOS transistors.Type: GrantFiled: July 5, 2005Date of Patent: February 16, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Kwang-Myoung Rho
-
Patent number: 7646229Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.Type: GrantFiled: November 3, 2006Date of Patent: January 12, 2010Assignee: Micron Technology, Inc.Inventor: Shizhong Mei
-
Patent number: 7646214Abstract: In various embodiments of the invention, a power-harvesting termination circuit may be used to 1) match the impedance of a signal line being terminated, and 2) recover a portion of electrical power from a signal on the signal line and provide the recovered power as an electrical voltage to be used to power other circuits. The power may be harvested at either the receiving device or at the transmitting device.Type: GrantFiled: November 28, 2007Date of Patent: January 12, 2010Assignee: Intel CorporationInventor: Joshua R. Smith
-
Patent number: 7633310Abstract: A semiconductor integrated circuit includes an output driver, a replica driver, a replica resistor, and an impedance adjustment circuit. The output driver is configured to be capable of changing current driving capability. The replica driver is configured to be capable of changing current driving capability. The replica resistor is connected to an output of the replica driver. The impedance adjustment circuit is configured to adjust the current driving capability of the output driver and the replica driver, based on an output voltage of the replica driver. In addition, the output driver, the replica driver, the replica resistor, and the impedance adjustment circuit are mounted in an integrated circuit package.Type: GrantFiled: October 26, 2007Date of Patent: December 15, 2009Assignee: NEC Electronics CorporationInventor: Tetsuo Fukushi
-
Patent number: 7626417Abstract: On-die-termination control circuit includes a clock generator configured to generate shift clocks in response to an on/off control signal; and a shift register configured to delay the on/off control signal in synchronization with the shift clocks to control on/off timing of an ODT operation.Type: GrantFiled: June 9, 2008Date of Patent: December 1, 2009Assignee: Hynix Semiconductor Inc.Inventors: Seung-Min Oh, Ho-Youb Cho
-
Patent number: 7619439Abstract: When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values.Type: GrantFiled: June 5, 2008Date of Patent: November 17, 2009Assignee: NEC Electronics CorporationInventor: Shuji Suenaga
-
Patent number: 7602210Abstract: A two-wire transmitter for receiving power supply from an external circuit through two transmission lines and also transmitting a current signal based on the measurement value of a sensor includes a current control section to which a voltage is supplied from an external circuit, for controlling the current value of the current signal based on an electric signal responsive to the measurement value of the sensor, if current consumption of the two-wire transmitter becomes smaller than the current value of the current signal, the current control section for charging and if the current consumption becomes larger than the current value of the current signal, the current control section for discharging; a computation control section for outputting the electric signal to the current control section and also outputting a setting signal based on predetermined computation processing information; a clock supply circuit for controlling the frequency of a clock signal based on the setting signal and supplying the clock sigType: GrantFiled: March 31, 2008Date of Patent: October 13, 2009Assignee: Yokogawa Electric CorporationInventor: Dai Katoh
-
Patent number: 7602208Abstract: An on die termination controls a terminal resistance value in accordance with a test signal. The one die termination device comprises an on die termination control unit and an on die termination resistor unit and can change the terminal resistance value in accordance with the test signal, so that the terminal resistance can be easily analyzed. The one die termination control unit comprises a resistance control enable signal generating unit and a resistance control signal generating unit and generates at least one resistance increment signal and at least one resistance decrement signal. The on die termination resistor unit comprises a resistor and a plurality of switch units that are connected in parallel and is driven by a driving signal and uses the resistance increment signal and resistance decrement signal to control the on die termination resistance value.Type: GrantFiled: December 26, 2007Date of Patent: October 13, 2009Assignee: Hynix Semiconductor Inc.Inventor: Jong Ho Jung
-
Patent number: 7595656Abstract: An interface circuit includes a driver circuit (12) made up of a combination of a plurality of transistors, a calibration circuit (14) for performing selection of on and off of one or more of the plurality of transistors for adjusting on-resistance thereof, and a terminating resistor (13) that is connected to an output side of the driver circuit (12). One or more of the transistors are turned on based on an output of the calibration circuit (14), so that a combination resistance value of the on-resistance and the terminating resistor matches characteristic impedance of the transmission line. The driver circuit (12), the calibration circuit (14) and the terminating resistor (13) are formed on the same semiconductor integrated circuit SK, and the calibration circuit (14) detects process variation and temperature variation of the transistor and the resistor formed on the semiconductor integrated circuit (SK).Type: GrantFiled: November 29, 2007Date of Patent: September 29, 2009Assignee: Fujitsu LimitedInventors: Kazunori Hayami, Tetsuya Ohtani
-
Patent number: 7586325Abstract: In one embodiment, an integrated circuit has configurable application circuitry that operates at any one of multiple available power supply voltages. PT-control circuitry, operating at a PT reference voltage, generates a PT-control signal indicative of variations in process and temperature. Application-control circuitry controls the configuration of the application circuitry based on the selected power supply voltage for the application circuitry and the PT-control signal, where the selected power supply voltage is independent of the PT reference voltage.Type: GrantFiled: December 3, 2007Date of Patent: September 8, 2009Assignee: Lattice Semiconductor CorporationInventors: William B. Andrews, Mou C. Lin, John Schadt
-
Patent number: 7560975Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.Type: GrantFiled: January 5, 2007Date of Patent: July 14, 2009Assignee: Renesas Technology Corp.Inventors: Kiyoo Itoh, Hiroyuki Mizuno
-
Patent number: 7550993Abstract: Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal.Type: GrantFiled: September 21, 2007Date of Patent: June 23, 2009Assignee: Texas Instruments IncorporatedInventors: Keerthinarayan P. Heragu, Rajat Chauhan, Chintamani Keshav Bhaktavatson
-
Patent number: 7521960Abstract: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.Type: GrantFiled: October 31, 2007Date of Patent: April 21, 2009Assignee: Actel CorporationInventors: Rabindranath Balasubramanian, Kurt Kolkind, Gregory Bakker
-
Patent number: 7511531Abstract: A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor. The supplemental pull-up circuit is configured to generate a supplemental pull-up output signal with the first pull-up output signal and the supplemental pull-up output signal, forming a pull-up output signal. The output buffer further includes a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal and a supplemental pull-down circuit in parallel with the first pull-down transistor. The supplemental pull-down circuit is configured to generate a supplemental pull-down output signal with the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal.Type: GrantFiled: September 11, 2006Date of Patent: March 31, 2009Assignee: Micron Technology, Inc.Inventors: Dong Pan, Leel S. Janzen
-
Publication number: 20090080276Abstract: A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the stand-by mode at any particular operating temperature. The disclosed circuit contains at least one monitor FET, which is kept in its off-state, and which has common properties with the large plurality of FET devices. The temperature dependent leakage current of the monitor FET is sensed, and used to generate the bias voltage in proportion to the leakage current. This bias voltage is received by the large plurality FET devices on their gate electrodes, or on their body terminals.Type: ApplicationFiled: September 23, 2007Publication date: March 26, 2009Inventors: Jin Cai, Randy William Mann, Harold Pilo
-
Patent number: 7501851Abstract: Configurable voltage mode transmitter architectures are based on combinations of drive cells and parallel termination cells connected in parallel across an external load to provide configurable output characteristics. Each drive cell and parallel termination can be individually enabled, various configurations of enabled cells providing the output characteristics configurability. In some embodiments, dedicated or configured pre-emphasis drive cells with individual enablement capability are added. In some embodiments, pull-down and pull-up cells with individual enablement capability are added to provide additional configurability options. When present, the pre-emphasis, pull-down and pull-up cells are connected in parallel across the external load to provide pre-emphasis features to the output.Type: GrantFiled: May 24, 2007Date of Patent: March 10, 2009Assignee: PMC Sierra Inc.Inventors: Michael Ben Venditti, William Michael Lye
-
Patent number: 7498834Abstract: A semiconductor memory device according to the present invention can change adjusting timing of ODT operation in convenience and have an optimized ODT timing whether the semiconductor memory device is putted on ether rank of a module. The present invention includes an impedance adjusting unit for adjusting an impedance value of an input pad in response to an impedance selecting signal; an ODT operating control unit for controlling the impedance adjusting unit as generating the impedance selection signal using an decoding signal and an ODT timing signal; a delay adjusting unit for delaying an internal control clock for a predetermined timing to thereby generate the ODT timing signal; and an ODT timing control unit for controlling the delay adjusting unit to decide the value of the predetermined timing according to whether or not the semiconductor memory device is arranged to a first rank or a second rank in a module.Type: GrantFiled: December 30, 2005Date of Patent: March 3, 2009Assignee: Hynix Semiconductor Inc.Inventor: Yong-Mi Kim
-
Patent number: 7495467Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs.Type: GrantFiled: December 15, 2005Date of Patent: February 24, 2009Assignee: Lattice Semiconductor CorporationInventors: Mou C. Lin, William B. Andrews, John A. Schadt
-
Patent number: 7486105Abstract: A memory system includes a first memory unit, a transmission bus having an impedance, and a memory controller having a first on-die termination circuit, coupled to the first memory unit through the transmission bus. The first on-die termination circuit matches the impedance of the transmission bus in response to the memory controller writing data to the first memory unit.Type: GrantFiled: January 22, 2007Date of Patent: February 3, 2009Assignee: Mediatek Inc.Inventor: Ching-Chih Li
-
Patent number: 7482839Abstract: An apparatus includes a transmitter, receiver or transceiver to couple to a communication link. An input receives one or more signals for a desired power level of the transmitter, receiver or transceiver. A power supply provides power to the transmitter, receiver or transceiver depending on at least the one or more signals.Type: GrantFiled: December 13, 2006Date of Patent: January 27, 2009Assignee: Infineon Technologies AGInventor: Fan Yung Ma
-
Patent number: 7466601Abstract: According to one embodiment a semiconductor device is provided. The device includes a first compensator to generate a first compensated signal and a first limiter to control operation of the first compensator. Furthermore, a second compensator to generate a second compensated signal and a second limiter to control operation of the second compensator is provided. An output device is adapted to receive the first compensated signal and the second compensated signal to drive an output.Type: GrantFiled: December 1, 2006Date of Patent: December 16, 2008Assignee: Qimonda AGInventor: David Müller
-
Patent number: 7449914Abstract: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.Type: GrantFiled: June 26, 2006Date of Patent: November 11, 2008Assignee: Hynix Semiconductor Inc.Inventors: Yong-Ki Kim, Kyung-Hoon Kim
-
Publication number: 20080265935Abstract: An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad.Type: ApplicationFiled: July 16, 2008Publication date: October 30, 2008Applicant: Acetel CorporationInventors: Gregory Bakker, Rabindranath Balasubramanian
-
Patent number: 7439759Abstract: As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.Type: GrantFiled: May 17, 2004Date of Patent: October 21, 2008Assignee: NXP B.V.Inventors: Atul Katoch, Manish Garg, Evert Seevinck, Hendricus Joseph Maria Veendrick
-
Patent number: 7414426Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for time-multiplexed dynamic on-die termination. In an embodiment, an integrated circuit receives, during a first clock, an on-die termination (ODT) activation signal at its ODT pin. The integrated circuit also receives, during a second clock, an ODT value selection signal on its ODT pin. In an embodiment, the integrated circuit prevents a reset of the state of the ODT activation signal for a predetermined period of time to enable the multiplexing of signals on the ODT pin. Other embodiments are described and claimed.Type: GrantFiled: December 7, 2005Date of Patent: August 19, 2008Assignee: Intel CorporationInventors: Christopher Cox, George Vergis
-
Patent number: 7414427Abstract: An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad.Type: GrantFiled: November 21, 2006Date of Patent: August 19, 2008Assignee: Actel CorporationInventors: Gregory Bakker, Rabindranath Balasubramanian