Abstract: A pin state configuration circuit, a method for configuring pin states and an electronic device for configuring pin states are provided. The pin state configuration circuit includes a configured resistor load, a voltage sampling unit, and a comparator. The voltage sampling unit supplies a reference voltage to the configured resistor load by using a first or second configuration pin, and respectively samples voltages of the first and second configuration pins. The comparator calculates a first voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, calculates a second voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, and determines a corresponding pin configuration state based on the first and second voltage ratios. In this way, N×N pin configuration states may be obtained by configuring two configuration pins.

Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes an output node at which a voltage for transmission via a differential conductor is present. The circuit further includes a first pull-up network coupled between a voltage supply node and the output node and configured to include a first amount of resistance. The circuit further includes a second pull-up network coupled between a voltage supply node and the output node and configured to include a second amount of resistance. The circuit further includes a comparator having a first input terminal coupled to the output node, a second input terminal configured to receive a reference voltage, and an output terminal configured to output a comparison result.

Abstract: An object of the present invention is to efficiently reduce the number of signal lines of a control port and an input port of a sensor switch required for controlling a touch by supplying a programmable voltage from a touch drive IC TDI, not a separate external voltage source, as a voltage applied to a touch sensor. The present invention provides a touch screen which is capable of implementing low power consumption, low-resistance signal wiring, touch IC price reduction, and the like by forming a switching transistor of the sensor switch only with a P-type transistor manufactured in a Low Temperature Poly Silicon (LTPS) process, and driving the switching transistor without using a negative voltage (?V).

Abstract: A semiconductor apparatus may include logic circuits and a control logic. The control logic may be configured to monitor characteristics of the logic circuits to allow the semiconductor apparatus to perform at different operating speeds.

Abstract: Computationally efficient methods of determining a transient supply current in a circuit are disclosed. The methods include offline simulation of circuit models to obtain time series of signal currents which are used in a dynamic simulation to calculate equivalent capacitances for a cell model of the circuit. The equivalent capacitances may be used in the simulation to compute estimates of noise current in a power distribution network.

Abstract: A level shifter includes an input circuit configured to generate and output first and second intermediate signals based on an input signal that transitions between a first voltage level and a second voltage level. The level shifter includes a feed forward circuit configured to receive the first intermediate signal from the input circuit and generate and output a third intermediate signal enabled in a part of a period in which the first intermediate signal is enabled and to receive the second intermediate signal from the input circuit and generate and output a fourth intermediate signal enabled in a part of a period in which the second intermediate signal is enabled. Moreover, the level shifter includes a level shifting circuit configured to receive the first through fourth intermediate signals and to shift the input signal to an output signal that transitions between a third voltage level and the second voltage level.

Abstract: A power gating system may include a logic circuit area configured to perform a power-down operation according to at least one power-down control signal. The power gating system may also include a power gating control circuit configured to generate the at least one power-down control signal when a power-down request period is equal to or greater than a preset time according to a power-down mode signal.

Abstract: A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.

Abstract: Noise is reduced in a circuit that converts voltage. A voltage conversion circuit includes a conversion transistor, a current source transistor, and a control circuit. In this voltage conversion circuit, the conversion transistor converts a potential of an input signal, the potential being changed from one of two different potentials to the other, by using predetermined current, and outputs the converted signal as an output signal. Furthermore, the current source transistor supplies the predetermined current. Then, in a case where the potential of the input signal is changed to the other potential, the control circuit stops supplying the predetermined current.

Abstract: Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.

Abstract: The present technology relates to a charge pump circuit that enables reduction of a circuit area. Provided is a charge pump circuit including: a first transistor; a second transistor to which a constant current is supplied; a third transistor connected to the first transistor and a voltage source; a fourth transistor group including N transistors arranged in a cascade on the first transistor side, the N transistors all including control terminals connected to the second transistor; a fifth transistor group including N transistors arranged in a cascade on the second transistor side, the N transistors all including control terminals connected to the second transistor; a first switch that connects the first transistor to the second transistor; a second switch that connects the first transistor to a ground node; a third switch that connects the third transistor to the fifth transistor group; and a fourth switch that connects the third transistor to the ground node.

Abstract: Embodiments relate to a circuitry for digital data communication. The circuitry includes an inverter circuit connected between an input node and an output node. The inverter circuit has core circuits each of which includes a complementary metal-oxide-semiconductor (CMOS) transistor of a first type and a CMOS transistor of a second type having a first common gate node connected to the input node and a first common drain node connected to the output node. The circuitry further includes another inverter circuit of a switching threshold voltage different than that of the inverter circuit and connected between the input node and the output node. The other inverter circuit has core circuits each of which includes a CMOS transistor of a third type and a CMOS transistor of a fourth type having a second common gate node connected to the input node and a second common drain node connected to the output node.

Abstract: A level shifting circuit for a voltage level translator includes first and second cross-coupled level shifters, each coupled between an output supply voltage and a lower rail and further coupled to receive first and second input control signals and to provide an output control signal. The second cross-coupled level shifter includes a first PMOS transistor coupled in series with a first NMOS transistor and a second PMOS transistor coupled in series with a second NMOS transistor. When an input supply voltage is less than a VCCI trigger associated with the output supply voltage, only the first and second NMOS transistors are coupled to contribute to the output control signal and when the input supply voltage is equal to or greater than the VCCI trigger, only the first and second PMOS transistors are coupled to contribute to the output control signal.

Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit includes a first pulse generating circuit and a second pulse generating circuit. Each of the first pulse generating circuit and the second pulse generating circuit is configured to connect to a charge pump. The first pulse generating circuit is configured to provide the charge pump with a series of first pulse signals. The second pulse generating circuit is configured to generate a second pulse signal in response to and based on an address translation detection signal and provide the second pulse signal to the charge pump or to the first pulse generating circuit. The first pulse generating circuit generates an additional first pulse signals based on the second pulse signal.

Abstract: A bootstrap circuit including a receiving circuit, a switched capacitor module and a booting circuit is provided. The receiving circuit receives an input signal to selectively output an output signal according to a control signal. The switched capacitor module is coupled to the input signal, and is arranged for generating the control signal according to the input signal. The booting circuit is coupled to the receiving circuit, and is arranged for applying an initial voltage when the control signal starts to enable the transistor, to increase a voltage level of the control signal.

Abstract: Combining the functionality of sleep transistors with logic devices in power-gating circuits by utilizing fully depleted silicon-on-insulator (FDSOI) transistors. In an embodiment, a back gate of a FDSOI transistor controls the threshold voltage to eliminate the need for standalone sleep transistors.

Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.

Abstract: In an embodiment, an apparatus includes an input circuit coupled to a first power supply with a first voltage level, a power circuit coupled to a second power supply with a second voltage level, and an output driver. The input circuit may receive an input signal, and generate an inverted signal dependent upon the input signal. The power circuit may generate a power signal in response to first values of the input and the inverted signals, wherein a voltage level of the power signal may be dependent upon the second voltage level. The power circuit may also generate a third voltage level on the power signal in response to second values of the input and the inverted signals. The output driver may generate an output signal dependent upon the input signal. The output signal may transition between the voltage level of the power signal and the ground reference level.

Abstract: A transmitting device may include a logic circuit, a transmission controller, and a transmission driver. The encoder may generate transmission control signals based on control symbols. The transmission controller may generate driving control signals based on the transmission control signals. The transmission driver may drive a wire to one level among multiple levels, based on the driving control signals.

Abstract: An output driver includes a switching device having a first node coupled to a gate of a power switch and pulling down a voltage level of the gate of the power switch to prevent a premature turn-on of the power switch. A pull-down circuit is coupled to the switching device and keeping the switching device from being turned on to prevent the premature turn-on of the power switch.

Abstract: A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (CML) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.

Abstract: A rectifier device is described herein. In accordance with one exemplary embodiment, the rectifier device includes a semiconductor substrate doped with dopants of a first doping type and at least one well region arranged in the semiconductor substrate and doped with dopants of a second doping type. Accordingly, the at least one well region and the surrounding semiconductor substrate form a pn-junction. The rectifier device further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode connected parallel to the load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. The rectifier device further includes a control circuit and a biasing circuit. The control circuit is configured to switch on the first MOS transistor for an on-time period, during which the diode is forward biased.

Abstract: Systems and methods are described for compensating for variations in process, voltage, temperature, or combinations thereof in an apparatus. An example apparatus may be a memory circuit. A pre-driver circuit and driver circuit may be associated with the memory circuit. A reference generator may provide the pre-driver circuit with reference signals that are insensitive to process, voltage, and temperature. The pre-driver circuit may receive the reference signals and the pre-driver circuit output ramping rate may then be made less sensitive to variations in process, voltage, and temperature. The pre-driver circuit output may then be supplied to a driver circuit that may then output a final driver data output with reduced noise.

Abstract: According to one general aspect, an apparatus may include a power header and a logic circuit. The power header may include a gate terminal, a first channel terminal, a second channel terminal, and a bulk terminal coupled with a first voltage power signal. The power header may be configured to perform one of dynamically coupling or decoupling a logic circuit with the first voltage power signal. The logic circuit may include a bulk terminal coupled with a second voltage power signal and a power terminal that is either dynamically coupled or decoupled, as determined by the power header, with the first voltage power signal. A power sequencing signal may be included in the apparatus and may be configured to control the power header such that, when active, the power header couples the logic circuit with the first voltage power signal after the second voltage power signal is high.

Abstract: In accordance with an embodiment, method of controlling a switching transistor includes applying a first voltage to a first node of a switchable tank circuit, where the first node is coupled to a control node of the switching transistor, the first voltage has a first polarity with respect to a reference terminal of the switching transistor, and the first voltage is configured to place the switching transistor into a first state. After applying the first voltage, the switchable tank circuit is activated, where a voltage of the first node transitions from the first voltage to a second voltage that is configured to place the switching transistor in a second state different from the first state. The switchable tank circuit is deactivated after the voltage of the first node attains the second polarity.

Abstract: A power supply control circuit for controlling power supply or stop of power supply is provided between a power source and a circuit block such as a processor. The power supply control circuit not only performs power supply to the circuit block or intentionally stops power supply but also is able to hold the power supply potential when the power supply is suddenly stopped, so that a loss of data in the circuit block can be prevented. By utilizing the power supply potential held by the power supply control circuit, data in the circuit block is saved in the nonvolatile memory device, so that a loss of data in the circuit block can be prevented. As described above, the power supply control circuit functions as a power gating switch and a circuit for holding the power supply potential in the case where power supply is suddenly stopped.

Abstract: Memory cells and methods of forming thereof are disclosed. The memory cell includes a substrate and first and second select transistors. The first select transistor serves as a write selector and the second select transistor serves as a read selector. The gate of first select transistor is coupled to a write wordline (WL_w) and the gate of the second select transistor is coupled to a read/write wordline (WL_r/w). The source regions of the first and second select transistors are coupled to a source line (SL). A body well is disposed in the substrate. The body well serves as a body of the first and second select transistors. A back bias is applied to the body of the select transistors. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled with a bitline (BL) and the first and the second select transistors.

Abstract: Dynamic biasing circuits for low drop out (LDO) regulators are described. In some embodiments, an electronic circuit may include a low drop out (LDO) regulator; and a biasing circuit coupled to the LDO regulator, the biasing circuit configured to: monitor a first electrical current and a second electrical current; select a greater of the first or second electrical currents; and provide the selected electrical current to the LDO regulator. In other embodiments, a method may include: providing a digital core and a low drop out (LDO) regulator coupled to the digital core, wherein the digital core is configured to operate in an active mode and in a standby mode; monitoring, via a current selector circuit coupled to the LDO regulator, a first current and a second current; selecting a greater of the first or second electrical currents; and providing the selected current as a biasing current to the LDO regulator.

Abstract: A power gating circuit including a set of weak-strong switch cells and strong-only switch cells daisy chained together. Each of the weak-strong cell is layout (footprint) compatible with the strong-only cell such that swapping a weak-strong cell for a strong-only cell or vice-versa during the design phase of the power gating circuit does not affect routing to or the timing operation of the circuit to which the power gating circuit supplies power. This allows the ratio of weak to strong switches for minimizing in-rush currents to be optimally set during the design phase of an IC. Each of the weak-strong cells couples power rails together via a weak transistor in response to a weak enable signal, and via a strong transistor in response to a strong enable signal. Each of the strong-only cell couples the power rails together via weak and strong transistors in response to the strong enable signal.

Abstract: A semiconductor device includes a substrate including an active fin and an isolation layer thereon, a first gate structure on the active fin, the first gate structure including a first gate insulation layer pattern and a first metal pattern, and the first metal pattern having a first conductivity type and directly contacting the first gate insulation layer pattern, a first channel region at a portion of the active fin facing a bottom surface of the first gate structure, the first channel region including impurities having the first conductivity type, and first source/drain regions at upper portions of the active fin adjacent to opposite sidewalls of the first gate structure, the first source/drain regions including impurities having a second conductivity type different from the first conductivity type.

Abstract: An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a power collapse period and a collapsible power rail to cease providing power during the power collapse period. The IC also includes a positive-edge-triggered (PET) RFF and a negative-edge-triggered (NET) RFF. The PET RFF includes a master portion and a slave portion, with the slave portion coupled to the constant power rail and the master portion coupled to the collapsible power rail. The NET RFF includes master and slave portions, with the master portion coupled to the constant power rail and the slave portion coupled to the collapsible power rail. In another example aspect, a control signal based on a clock and a retention signal may be routed to both RFFs.

Abstract: A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.

Abstract: An electronic communication device includes an antenna configured to receive a radio frequency (RF) signal and generate a differential current signal. A mixer circuit is configured to downconvert a differential voltage to generate an output voltage. The differential voltage is generated from the differential current signal, and the output voltage is used for detecting the RF signal.

Abstract: Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Abstract: A pre-charge buffer for sampling input signals and generating a sampled output signal includes a coarse sampling circuit, a fine sampling circuit, and a sample and hold circuit. The coarse sampling circuit pre-samples the input signals during hold phases and for a first predetermined time interval during sample phases of the corresponding sample and hold cycles, and generates a first output signal. The fine sampling circuit samples the input signals during sample phases and generates a second output signal. The sample and hold circuit receives the first and second output signals, and generates a sampled output signal. The coarse sampling circuit provides the first output signal for a predefined time interval during the sample phases to reduce the effect of charge injection and charge sharing. The system uses bottom plate sampling to reduce charge injection caused by switches in the coarse sampling circuit.

Abstract: A semiconductor device includes a substrate; a first through-electrode penetrating the substrate and connected to a power source or a reference potential point; a second through-electrode penetrating the substrate; a power section connected between the substrate and the second through-electrode and configured to output a DC voltage between the substrate and the second through-electrode; a voltage control section configured to control the DC voltage to be output by the power section; and a measurement section connected to the first through-electrode and configured to measure a power impedance of the first through-electrode, wherein the voltage control section is configured to control a value of the DC voltage output by the power section, such that the power impedance of the first through-electrode measured by the measurement section is equal to or less than a predetermined value within a predetermined frequency range including a frequency of noise occurring in the first through-electrode.

Abstract: A transmitter, a common mode transceiver using the same, and an operating method thereof are provided. The transmitter includes a first transistor group and a second transistor group. The first transistor group includes a first transistor connected in series with a second transistor, wherein the second transistor is applied a first well-tracking control. The second transistor group includes a third transistor connected in series with a fourth transistor, wherein the third transistor is applied a second well-tracking control. There is an output node between the first transistor group and the second transistor group, and the second transistor and the third transistor are coupled to the output node. The present invention can effectively block leakage paths in common mode operation, and can enhance ESD protection capability.

Abstract: Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are “SET” flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are “RESET” flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.

Abstract: A power gating circuit in an integrated circuit, including a circuit block coupled to a virtual power supply line, includes a first transistor and a buffer. The first transistor is coupled between a first power supply line and the virtual power supply line, and has a body coupled to the first power supply line. The buffer buffers a control signal to apply the buffered control signal to the first transistor, and includes a second transistor having a source coupled to a second power supply line and a body coupled to the first power supply line.

Abstract: A data output device may include a driving control, a voltage supply unit, and an output driving unit. The driving control unit outputs a pull-up control signal and a pull-down control signal in response to a logic value of data when an output enable signal is activated. The voltage supply unit generates a driving voltage lower than a supply voltage. The output driving unit is driven in response to the driving voltage, and controls an amplitude and a slew rate of a voltage supplied to a global line according to the pull-up control signal and the pull-down control signal.

Abstract: A latch and a frequency divider are provided. The latch includes: a first logic cell coupled between a power supply and a ground wire, wherein the first logic cell has a first control terminal, a first input terminal and a first output terminal; a second logic cell having a structure symmetrical to that of the first logic cell; wherein the second logic cell has a second control terminal, a second input terminal and a second output terminal; and a feedforward control unit adapted to control the first logic cell or the second logic cell based on signals inputted into the first input terminal and the second input terminal. Accordingly, current loss under static working conditions of a latch can be eliminated, and current loss under dynamic working conditions of the latch can be reduced.

Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Abstract: Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode.

Abstract: Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power gate emulation circuit is inserted using a processor. The power gate emulation circuit is coupled to the isolation signal, the power gate signal, and the output of the first power domain.

Abstract: A semiconductor memory device is provided which includes a function block including a plurality of transistors; a body bias control unit configured to detect a command and to generate a body bias selection signal according to the detection result; and a body bias generator configured to generate a body voltage according to the body bias selection signal and to provide the body voltage to bodies of the plurality of transistors, wherein the body bias generator down-converts a power supply voltage supplied from an external device to generate the body voltage.