Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.

Abstract: The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.

Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

Abstract: An integrated circuit comprising a plurality of CMOS modules (10) connected in series with each other, each module (10) being connected between first and second reference lines (Vdd, Vss). A first transistor (54) is provided between at least one of the modules (10) and the first reference line (Vdd) and a second transistor (52) is provided between one of the modules (10) and the second reference line (Vss) and capacitors (C25, C26) are provided in parallel with the transistors (52, 54) such that they are driven as current sources (I1, I2). As a result power dissipation and leakage current is reduced.

Abstract: Apparatus and methods provide low voltage differential signaling (LVDS) driver with replica circuit biasing and protection for hot plugging. The replica biasing is non-intrusive in nature, and can control the voltage swing tightly over parametric variations. The absence of an explicit near-end driver termination improves efficiency, while replica biasing controls output voltage swing levels. Hot-pluggable compatibility is achieved by a reduction in power-off leakage current and short circuit current protection.

Abstract: A transmission circuit includes a plurality of transmission lines connected in a ring to propagate signals among a plurality of devices. The plurality of transmission lines have a predetermined same propagation delay, and a predetermined transmission line impedance, and the predetermined transmission line impedance is a half or less of an output impedance of each of the plurality of devices. When a signal outputted from a first optional one of the plurality of devices is propagated to the plurality of devices other than the first optional device, the signal outputted from the first optional device exceeds a predetermined threshold of a signal voltage at a same time.

Abstract: A driver circuit and method for generating two complementary output currents from a two-state logic input signal at two outputs for connecting a two-wire conductor provide the following actions: generating from the input signal, an output signal at each output, the amperage of one of the output currents being adjustable by a control signal; analyzing each voltage materializing at the outputs; generating an error signal as a function of the output voltages within each of at least two time slots subsequent to a change in state of the input signal; caching the error signals or signals derived therefrom and adjusting, as a function of cached error signals or of the cached signals as a function thereof, the output current in corresponding time slots subsequent to a resulting change in state of the input signal.

Abstract: A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

Abstract: A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.

Abstract: The invention discloses an active back-end termination circuit, which comprises a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor and the first transistor are connected in series for forming a first impendence unit. A first source of the first transistor is connected to a working voltage with VTT. The second resistor and the second transistor are connected in series for forming a second impendence unit. A second gate and a second drain of the second transistor are connected to the working voltage with VTT. Wherein, the first impendence unit and the second impendence unit are connected in parallel. The first transistor or the second transistor is switched on through a power source, and the first transistor and the second transistor change the impedance actively for matching a load according to the voltage source.

Abstract: An input and output circuit apparatus includes a signal generating circuit configured to generate a first signal, an input and output circuit configured to receive the first signal from the signal generating circuit and a second signal to generate an output signal responsive to the first signal and the second signal, an operation test circuit having substantially an identical circuit configuration to the input and output circuit, and configured to receive the first signal from the signal generating circuit and a third signal to generate an output signal responsive to the first signal and the third signal, a check circuit configured to generates a check signal indicative of an operating condition of the operation test circuit in response to the output signal of the operation test circuit, and an adjustment circuit configured to adjust the signal generating circuit in response to the check signal output from the check circuit.

Abstract: Disclosed in various embodiments are a circuit and method for driving a signal. In one embodiment, the circuit includes a passive impedance conversion network and at least two signal drivers coupled to the passive impedance conversion network. Each of the signal drivers includes a signal input coupled to a common signal input node.

Abstract: Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost signal. Additional apparatus, systems, and methods are disclosed.

Abstract: A terminator for a CAN bus includes an electronic relay and a termination impedance. The electronic relay has first and second control input conductors and switched output conductors. The electrical connection between the switched output conductors is normally closed. The first control input conductor is connected to the power conductor and the second control input conductor is connected to a fifth terminal of the first CAN bus connector. The termination impedance is connected in series at the end node of the CAN bus with the switched output conductors across the high data conductor and the low data conductor. By this arrangement, the termination impedance is effectively connected across the high data conductor and the low data conductor at the end node of the CAN bus until an extension of the CAN bus is plugged into the first CAN bus connector. When an extension of the CAN bus is plugged into the first CAN bus connector, the fifth terminal of the CAN bus connector is connected to the ground conductor.

Abstract: Methods and apparatus are provided for selectively setting a CM voltage for a transceiver, reducing the effect of current mismatch, and generating a voltage step that can be used for receiver detection. A circuit of the invention can include voltage generator circuitry operable to generate a plurality of voltage signals of substantially different voltages. The circuit can also include multiplexer circuitry with voltage inputs coupled to the voltage signals. The multiplexer circuitry can be operable to select a reference signal from among the voltage inputs. In addition, the circuit can include operational amplifier (“op-amp”) circuitry with a first input coupled to the reference signal and a second input coupled to an output signal of the op-amp circuitry.

Abstract: In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply node; and a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node.

Abstract: A memory device is coupled to a subset of lines of a data input/output (I/O) bus. The memory device includes an on-die active termination circuit for terminating the subset of lines of the data I/O bus with a selected impedance being one of a plurality of selectable impedances; a termination value register being coupled to the on-die active termination circuit for storing a value representing the selected impedance; and a termination value setting circuit being coupled to the termination value register, for setting the value representing the selected impedance in the termination value register.

Abstract: An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output.

Abstract: A two-wire transmitter is connected to two transmission lines which transmit an electric signal regarding a physical quantity detected by a sensor. The two-wire transmitter includes a current control section which controls a transmission current of the electric signal, and a starter circuit which starts at a starting time of the two-wire transmitter so that the transmission current flowing through the current control section under steady operation of the two-wire transmitter detours the current control section to flow through the starter circuit. The starter circuit stops when an output voltage of the current control section reaches a predetermined value or more after the two-wire transmitter starts.

Abstract: There is provided a current amount adjusting section adjusting a current amount flowing through a power supply line supplying power to an internal circuit which includes a circuit operating based on a clock signal and a ratio of consumed charge amounts by the current flowing at a rising edge of the clock signal and by the current flowing at a falling edge of the clock signal so that noise generated in the power supply line may be restrained.

Abstract: A common module for a double data rate-synchronous II synchronous dynamic random access memory (DDRII SDRAM) and a DDRIII SDRAM applied in a computer is provided. The common module includes a first bus, a termination circuit card, a first slot, and a second slot. The first bus transmits a plurality of signals. The termination circuit card comprises a plurality of termination resistors. The first slot is disposed on the common module and coupled to the first bus. The DDRII SDRAM is installed in the first slot. The second slot is disposed on the common module and coupled to the first bus. The DDRIII SDRAM or the termination circuit card is installed in the second slot. When the DDRII SDRAM is installed in the first slot, the termination circuit card is installed in the second slot.

Abstract: An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage.

Abstract: An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC.

Abstract: An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transistors have a common conduction terminal connected to an output terminal of the output buffer. An input terminal of the buffer is connected to control terminals of the transistors of the first stage through a first open loop driving circuit. A second feedback driving circuit is connected between the input terminal and the control terminals of the transistors of the second stage. The second feedback driving circuit includes a current detector operating to detect a maximum in the value of the current drawn by and supplied to the output buffer. A comparison block, having a threshold value, detects current in excess of the threshold value and processes information coming from the current detector to regulate an output impedance value of the output buffer.

Abstract: A semiconductor device according to an embodiment of the present invention includes an output stage circuit including a first conductive type first transistor and a second conductive type second transistor, the first conductive type first transistor being connected between a first power supply terminal and an output terminal, the second conductive type second transistor being connected between a second power supply terminal and the output terminal and having a leak current larger than that of the first transistor, and an input stage circuit outputting a logic value setting the first transistor to a non-conductive state and setting the second transistor to a conductive state in accordance with a logic circuit disable signal input when the output stage circuit is in a disable state.

Abstract: A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.

Abstract: A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply. The circuit includes a PVT detector configured to generate a control signal and an adjustable resistance device configured to adjust its resistance in response to the control signal.

Abstract: A semiconductor integrated circuit including on the same semiconductor substrate: a first circuit block including a switching transistor which is off when the first circuit block is inactive and on when the first circuit block is active, the first circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a first power line maintained at a low-level source voltage; a second circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a second power line maintained at a low-level source voltage; a power line switch section connected between the first and second power lines; and a control circuit adapted to control the power line switch section so that the first and second power lines are connected together at a later timing or gradually over a longer period of time than the switching transistor turns on.

Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

Abstract: Systems and methods of suppressing latchup. In accordance with a first embodiment of the present invention a latchup suppression system comprises a voltage comparator for comparing a voltage applied to a body terminal of a semiconductor device to a reference voltage. The voltage comparator is also for controlling a selective coupling mechanism. The selective coupling mechanism is for selectively coupling the body terminal to a respective power supply. The latchup suppressing system is preferably independent of a voltage supply for applying a voltage to the body terminal.

Abstract: A buffer circuit is provided between a gate terminal of a pull-down transistor and a threshold circuit receiving a gate signal as an input signal. A voltage applied to an output terminal of a power semiconductor element from an external battery power supply is supplied to the buffer circuit through a resistive element. The buffer circuit converts the level of an on-signal output from the threshold circuit into a voltage higher than the threshold of the pull-down transistor, so that the pull-down transistor operates surely to turn off the power semiconductor element even when the level of the gate signal is low. Thus, there is provided a semiconductor integrated circuit device having a power semiconductor element which can be turned off by sure operation of a pull-down semiconductor element.

Abstract: A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

Abstract: A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through the transistor to create a first supply current. The transistor is coupled to the digital logic cells and the capacitor. The first supply current is used to charge the capacitor while the digital logic cells are not switching. While the digital logic cells are switching, the capacitor discharges to the digital logic cells, thereby providing the digital logic cells with sufficient energy to implement high-speed switching. The capacitor minimizes voltage fluctuations within in the current limited voltage supply, such that analog circuitry can be reliably powered from a different branch of the same current mirror circuit.

Abstract: An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.

Abstract: A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell generates the virtual supply voltage from a second supply voltage and provides the standard cell with the virtual supply voltage in response to a control signal. The virtual supply voltage and the first supply voltage are provided by a first metal layer and the second supply voltage is provided by a third metal layer. The power gating cell may include at least one slice block and isolator blocks. The respective slice block has a transistor for switching current. The isolator blocks are arranged on both sides of the slice block and insulate the slice block from outside.

Abstract: An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive-feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A voltage generating circuit for a semiconductor memory apparatus according includes a data logic voltage generating unit that, when a data output unit outside a semiconductor memory apparatus outputs low-level data, generates an internal data logic voltage at the same potential level as the low-level data in response to an on-die termination signal. In addition, a reference voltage generating circuit for a semiconductor memory apparatus that uses the voltage generating circuit includes a reference voltage generating unit that can be configured to generate a reference voltage at an average potential level between a maximum potential and a minimum potential of input data.

Abstract: An integrated circuit is provided with logic blocks which draw their power from virtual supply rails. These virtual supply rails are connected by switch blocks to main supply rails. The switch blocks are subject to modulation to maintain the virtual supply rails at an intermediate voltage level such that a reduced voltage difference is applied across the logic block. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks fully conductive and then the clock is restarted. The switch blocks which are modulated by controllers which use feedback control based upon the sensed virtual rail voltages (VVdd and Vgnd) while drawing their own power from the normal supply rails (Vdd and gnd).

Abstract: A power sequencing method may use a state machine in a programmable sequencer to program relative timing of signals to activate different power rails attached to an integrated circuit. Input lines may specify the sequencing program. Alternatively, the programmable sequencer may use an EEPROM or other computer-readable medium to program itself with a particular image of the sequencing program. The programmable sequencer may be implemented by a Field Programmable Gate Array (FPGA).

Abstract: In one embodiment, a method of leakage control for a memory having an array of memory cells arranged into a plurality of sub-arrays is provided wherein each sub-array has a sleep mode of operation controlled by a sleep signal in which stored data is lost, and wherein each sub-array asserts a local clock if the sub-array is addressed. The method includes the act of asserting a sleep signal while addressing a given one of the sub-arrays such that only the given one of the sub-arrays is placed into the sleep mode.

Abstract: A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance.

Abstract: A semiconductor device includes a circuit section having an output impedance which changes in accordance with a switching signal for switching between drive capabilities, and transforming an input signal into an output signal in accordance with the output impedance, a reference voltage generating section generating a reference voltage in accordance with the switching signal and the input signal, and a comparing section comparing a voltage of the output signal to the reference voltage.

Abstract: A design structure for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.

Abstract: A semiconductor integrated circuit includes: a first boundary cell having a first power source wiring, a second power source wiring and a first pseudo power source wiring; a first circuit cell having a third power source wiring connected with the first power source wiring, a second pseudo power source wiring connected with the first pseudo power source wiring, and a first circuit formed of a first circuit transistor; and a first switching transistor having a first electrode connected with the second power source wiring, a second electrode connected with the first pseudo power source wiring, and a gate electrode, wherein the first switching transistor is operated to be turned “ON” and “OFF” according to a control signal inputted to the gate electrode of the first switching transistor and an absolute value of a threshold voltage of the first switching transistor is larger than an absolute value of a threshold voltage of the first circuit transistor.

Abstract: A method and apparatus is provided that facilitates low-power consumption during a suspend mode of operation of an integrated circuit (IC), while substantially eliminating current paths within the IC that may be created should any of the power supplies be deactivated during the suspend mode. Deactivation of one or more power supplies during a normal mode of operation is also facilitated, whereby current paths created by the deactivated power supplies are also eliminated. Voltage bias circuitry is added to certain voltage regulators within the IC, so as to maintain those voltage regulators inactive due to a drop in voltage magnitude that is sensed when one or more power supplies are disabled. In addition, a well bias circuit is employed to maintain the substrate bias potential of certain devices within the voltage regulators and associated amplifiers to a fixed potential depending upon the operational mode of the IC.

Abstract: The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal and responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series. Each enable qualifying circuit sets its output signal when both the enable signal provided to the associated power switching circuit is set and the at least one voltage line of the circuit portion associated with that power switching circuit has reached a predetermined voltage level.

Abstract: Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.