Abstract: A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETs) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.

Abstract: In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased.

Abstract: An output impedance bias compensation system for adjusting output impedance of at least one output including a reference impedance generator, an impedance matching controller, at least one output impedance generator, and a programmable bias controller. The reference impedance generator develops a reference impedance based on a reference value. The impedance matching controller continually adjusts an input of the reference impedance generator to match the reference value within a predetermined tolerance. Each output impedance generator is coupled to a corresponding output and is controlled by an output impedance control input. The programmable bias controller combines a bias amount with the value of the input of the reference impedance generator to provide the output impedance control input. The bias controller is programmable to provide a bias amount to compensate for any process variations between the reference impedance generator and each output impedance generator.

Abstract: A data output circuit which outputs data on an internal bus line onto an external bus line includes a comparator, inverter, and controller. The comparator compares data on the external bus line and data to be output on the internal bus line. The inverter outputs a signal obtained by inverting the data on the internal bus line when the number of changed bits exceeds half the total number of bits on the basis of an output result from the comparator. The controller outputs an inversion display signal representing that the data has been inverted. A data output method is also disclosed.

Abstract: Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.

Abstract: An active terminating device (30) for an electrical transmission line with optional line-receiving and line-driving capabilities. The basic device is a two-terminal unit, denoted as a Signal Canceling Unit (SCU), which sensesthe signal available at its terminals (34a, 34b), and applies negative feedback in order to cancel and absorb the signal. When applied to the end of a transmission line (15a, 15b) as part of wired communication network, the SCU functions as a terminator. When connected in the middle of such wired transmission line, the SCU splits the transmission line into two separate and isolated segments. In such a configuration, the SCU can be used to isolate a portion of a network from signal degradation due to noise or bridge-tap. Furthermore, the two isolated segments may each employ independent communications, such that no interference exists between the segments.

Abstract: A method and apparatus are provided for implementing power control in multi-voltage input/output (I/O) circuits. First current biasing devices are provided for creating a first constant bias current. Second current biasing devices are provided for creating a second bias current. The second current biasing devices are activated at a first voltage and are deactivated at a second voltage. The first voltage is less than the second voltage.

Abstract: Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted with respect to the input signals. The amplified level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted and amplified with respect to the input signals. These circuits may be utilized to form a detection circuit that detects a difference in the output signals.

Abstract: Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted with respect to the input signals. The amplified level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted and amplified with respect to the input signals. These circuits may be utilized to form a detection circuit that detects a difference in the output signals.

Abstract: According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the devices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.

Abstract: A circuit receives a first supply voltage on a first terminal where the first supply voltage is used to supply circuitry within the circuit. The circuit includes an input terminal receiving a first signal and an input circuit coupled to the input terminal. The first signal has a logical high value at a second voltage and a logical low value at a third voltage. The second voltage is used to establish a switching threshold of at least some of the input and output signals of the circuit. The input circuit provides a reset signal to circuitry within the circuit causing the circuitry to reset. The reset signal is asserted when the first signal on the input terminal has a logical low value and the third voltage comprises a voltage below a predetermined trigger threshold of the input circuit.

Abstract: A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node and the N channel MOS transistor and turned on/off in response to a control signal are provided. The input signal is at the L level in a standby state. The control signal is at the L level in the standby state and at the H level in the active state. This suppresses the effect of hot carriers in the active state and decreases a subthreshold current in the standby state.

Abstract: A circuit for controlling a bitline during a memory access operation is provided. The circuit includes a plurality of sub-arrays with each sub-array having a plurality of memory cells. Each of the memory cells is coupled to respective bitline columns. The circuit further includes a sensed output from one of the bitline columns, and a global bitline coupled to a same respective bitline column of each of the plurality of sub-arrays. Each global bitline includes a voltage swing limiter for limiting a voltage swing of the global bitline, and an n-type transistor. The n-type transistor has a gate, a first terminal, and a second terminal. The gate is coupled to the sensed output, the first terminal is coupled to the global bitline, and the second terminal is coupled to the voltage swing limiter.

Abstract: A driver circuit for switching an output voltage (Vout) at an output terminal 3 by using diode bridges 1 and 2 includes a first current mirror circuit 10 for letting flow a first balance current I2e and letting flow a first transition current I2f obtained by adding a first stationary current to a product of the first balance current I2e and a predetermined multiplier when switching from the low level to the high level, and a second current mirror circuit 20 for letting flow a second transition current I2h obtained by adding a second stationary current to a product of the second balance current I2g and a predetermined multiplier when switching from the high level to the low level. As a result, the power dissipation in the stationary state is reduced without lowering the slew rate at the time when switching the output voltage.

Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability.

Abstract: A semiconductor apparatus including programmability that may allow a SSTL interface or LVTTL interface is provided. A reference configuration circuit (100) may provide a primary reference potential VREF0 and secondary reference potential VREF. Reference configuration circuit (100) may include a bond pad (PAD1), a reference potential generation circuit (1), a control circuit (50), a reference selection circuit (60), and a secondary reference potential generation circuit (70). During a wafer test mode, primary reference potential VREF0 and secondary reference potential VREF may be provided from a potential that may be applied to bond pad (PAD1).

Abstract: A circuit configuration has a first driver stage for feeding in an input signal and for outputting an amplified signal. A second driver stage, which is connected in parallel with the first driver stage, is fed, on the input side, both the input signal and a control signal from a reference circuit connected upstream. The reference circuit compares the feedback level of an output signal, which level is present at one of its inputs, with the level of the input signal present at its other input and generates the control signal for driving the driver stage in the event that the level of the output signal is lower than the level of the input signal. As a result, the driver stage is connected for additional amplification of the input signal.

Abstract: To provide a semiconductor instrument for improving power added efficiency when a low power is outputted. In the semiconductor instrument in which a radio-frequency input signal (SRF) is supplied to input circuits of a plurality of transistors (1, 2), output circuits of the plurality of transistors (1, 2) are connected in parallel, and a radio-frequency output signal amplified with power is retrieved an amplifying operation of one part transistor (2) of the plurality of the transistors (1, 2) is turned off during a low-output operation.

Abstract: A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.

Abstract: A line driver selectively drives one of two transmission lines. The line driver includes a differential amplifier connected to first and second differential switches. The first differential switch is connected between an output of the differential amplifier and a first of two transmission lines. The second differential switch is connected to the output of the differential amplifier and to the second of two transmission lines. The first and second differential switches are controlled by respective first and second control signals. The output of the differential amplifier is connected to either the first or the second transmission line in response to the first and second control signals. The differential switches include loopback protection to an prevent an incoming signal from passing from one transmission line to another during power down mode.

Abstract: A method for producing a stable control signal for impedance matching is provided which is capable of suppressing variation in impedance matching data by adding a shift voltage to a voltage to be compared. A comparator compares the voltage to be compared with a reference voltage and an up-down counter performs a counting operation according to a result from the comparison. A code converting circuit converts a count value output from the up-down counter to a thermometer code used for changing an impedance of an impedance varying circuit. A change in the impedance is made in a manner that, even when the voltage to be compared gets closest to the reference voltage, a shift voltage for the comparator to make an exact comparison is fed to the voltage to be compared. An averaging circuit averages a count value and the code converting circuit converts a resulting average value to the thermometer code.

Abstract: A low-voltage drive circuit for driving a sensor coil in a coordinate input device at a constant current includes a DC coupling capacitor and a constant-current output bias circuit unit. The DC coupling capacitor is provided between an output of a constant-current output drive circuit unit and a sensor coil. The constant-current output bias circuit unit controls a DC bias voltage of the output of the constant-current output drive circuit unit to be a midpoint potential of an operating voltage range for the constant-current output drive circuit unit. The constant-current output drive circuit unit may include a drive source circuit segment and a drive sink circuit segment that function as a complementary constant-current circuit unit. Preferably, the drive source circuit segment and the drive sink circuit segment are connected to respective constant-current output bias circuit units.

Abstract: A circuit for detecting ground bounce and for using the detection information to reduce data error resulting therefrom is described. In one embodiment an on-chip ground bounce detector circuit detects large ground bounce events caused by the simultaneous switching of I/O buffers of the chip and notifies an on-chip logic circuit of the event The on-chip logic circuit can be implemented to take a variety of actions upon receipt of notification from the detection circuit that a ground bounce has been detected.

Abstract: A CMOS inverter capable of operating at low voltages is provided. The gate of a p-channel MOS transistor and the gate of an n-channel MOS transistor are AC coupled to an input terminal via first and second capacitors, respectively. Signals whose amplitude centers are optimized according to the threshold voltages of the p- and n-channel MOS transistors by bias voltages from first and second variable voltage sources, respectively, are supplied to the gates of these MOS transistors. In consequence, the CMOS inverter can operate at high speeds at low power supply voltages without being affected by the threshold voltages.

Abstract: A variable voltage tolerant input/output circuit, wherein a leakage current is not produced while having a high reliability, characterized in that the circuit includes a clamping circuit for clamping the N-well potential of M1. When the supply voltage VCC is higher than or equal to the input/output voltage VI/O, the N-well potential of M1 is clamped to the supply voltage VCC; when the supply voltage VCC is lower than the input/output voltage VI/O, the N-well potential of M1 is clamped to the input/output voltage VI/O.

Abstract: A system and method of terminating signals are described. In one embodiment, the termination system of the present invention comprises a receiver for receiving a signal from a transmission line, a termination node, a resistive element disposed between the receiver and the termination node, and a termination voltage controller for changing the voltage level of the termination node, in response to the detected signal voltage level. In another embodiment, the present invention includes a method of adaptively terminating a signal. The method of this embodiment comprises detecting the voltage level of a signal, selecting the termination voltage level of a termination node in response to the detected signal voltage level, and terminating the signal, through a resistive element, at the selected termination voltage level.

Abstract: A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data lines and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.

Abstract: Various apparatuses and methods are described that include a variable-impedance matched termination pair coupled to differential signaling bus pair. In an embodiment, the differential signaling bus pair includes a first bus and a second bus. The variable-impedance matched termination pair includes a first variable-impedance component and a second variable-impedance component. The impedance value of each variable-impedance component depends on the voltage level sensed by that variable-impedance component. The first variable-impedance component couples to the first bus. The second variable-impedance component couples to the second bus. The first variable-impedance component is electrically isolated from the second variable-impedance resistor.

Abstract: It is an object of the invention to provide a digital circuit which can operate normally regardless of binary potentials of an input signal. A semiconductor device having a correcting unit and a logic unit wherein the correcting unit includes a capacitor, first and second switches, wherein the first electrode of the capacitor is connected to the input terminal and the second electrode of the capacitor is connected to the gate of the transistor in the logic circuit, wherein the first switch controls the connection between a gate and drain of the transistor and the second switch controls the potential to be supplied to the drain of the transistor is provided.

Abstract: An output buffer switch-on control circuit includes several transistors and a discharge current control circuit. A first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. A second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. A third transistor is controlled by the output data source and has a first terminal connected to a common voltage. A fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor. The fourth transistor also has a second terminal connected to the common voltage. The discharge current control circuit is preferably actively-controlled and is connected between a second terminal of the first transistor and a second terminal of the third transistor.

Abstract: The invention relates to a circuit of which the operating rate varies according to temperature, supply voltage and intrinsic quality of the transistors of the circuit, associated to a compensating circuit which comprises a constant current source (26) that produces a substantially constant current which is independent of temperature, supply voltage and intrinsic quality of the transistors of the circuit, a variable current source (28) producing a current that increases in an inverse proportion to temperature, supply voltage and intrinsic quality of the transistors of the circuit, and means for decreasing the operating rate of the circuit when the difference of the currents produced by the first and second sources increases.

Abstract: A line driver selectively drives one of two transmission lines. The line driver includes a differential amplifier connected to first and second differential switches. The first differential switch is connected between an output of the differential amplifier and a first of two transmission lines. The second differential switch is connected to the output of the differential amplifier and to the second of two transmission lines. The first and second differential switches are controlled by respective first and second control signals. The output of the differential amplifier is connected to either the first or the second transmission line in response to the first and second control signals. The differential switches include loopback protection to an prevent an incoming signal from passing from one transmission line to another during power down mode.

Abstract: An output buffer circuit of a Pseudo Emitter Coupled Logic (PECL) uses a common level which is generated by a resistance division so that the common level is unstable to follow to a gradient of power source variation and an output signal level of the output buffer circuit is apt to be off from a level of the PECL.

Abstract: The disclosure presents a device comprising a driver configured to transmit a signal on a bus line, including a driver element configured to pull against termination impedance. The impedance of the driver element is dynamically adjustable. The disclosure also presents a method of electronically adjusting the impedance of the driver element to regulate the swing voltage on the bus line.

Abstract: A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines. A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an equal-voltage detector that generates a power-down signal when the differential lines are at equal voltages for a period of time. The period of time can be greater than the cross-over time during normal switching to prevent false power-downs during normal switching. Standard differential drivers can signal power-down using the high-impedance state, which is detected by equal voltages on the differential lines. A sensitive dual-differential amplifier and a simpler detector are disclosed.

Abstract: Pullup and/or pulldown transistors are electrically connected to the output of MTCMOS logic gates. The use of a pullup transistor pulls up the output to a known, non-floating voltage level when the circuit enters a sleep mode (e.g. the high voltage threshold headswitch and/or footswitch are de-asserted) eliminating crowbar current from being drawn by connected circuits having neither footswitches nor headswitches. Likewise, when a pulldown transistor is electrically connected to the output of the MTCMOS logic gates, the output is pulled down to ground, or other reference level, when the circuit is in a sleep mode. As a result of the addition of a pullup or pulldown transistor on the output of the logic gates, the output is pulled to a known, non-floating voltage level, and the drawing of crowbar current from components that are electrically connected to the output of the logic gates is prevented.

Abstract: An improved integrated bias reference provides a temperature and supply stable bias for devices such as radio frequency amplifiers with less complexity and expense than conventional bias references. The bias reference may be integrated onto a single GaAs die with other active circuitry such as an amplifier.

Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: An inverter circuit which is a representative example of the logic circuit includes a p-channel A-MOS transistor and an n-channel transistor. The gain coefficient &bgr; of the p-channel A-MOS transistor and n-channel transistor changes according to a voltage on a control gate. The control gate of the p-channel A-MOS transistor and n-channel MOS transistor is connected to an output node of the inverter circuit, and the normal MOS gate is connected to an input node of the inverter circuit. Thus, the ON resistance of the p-channel A-MOS transistor and n-channel transistor is automatically modulated to decrease as the source-drain voltage increases.

Abstract: The present invention provides a semiconductor integrated circuit device and a communication device incorporating same. Two MOS (strong and weak) devices are connected to each control input of a transceiver. Both MOS devices are turned on while the supply voltage is ramping from 0V. The strong device remains on for a period of 10-20 microseconds. The strong MOS device pulls the input to a disabled state against external capacitance which is attempting to pull the input to an enabled state. The weak MOS device remains on while pulling the input to a disabled state. The input is pulled to an enabled state when an external source overcomes the weak MOS device. Once the control input is pulled beyond the input voltage threshold to the enabled state, the weak MOS device will be turned off permanently and the input will revert to a standard CMOS input with infinite input resistance.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: A logic input circuit for an industrial equipment automatic control system supplied by a DC voltage source, in particular a battery (16), comprises a voltage step-up energy converter (12) composed of an inductance coil (L) and a switching transistor (TR), connected to the input (E1) of the circuit (10); a logic level detector (DL) having a optocoupler; and a clock circuit (H) controlling the transistor (TR) by adjusting the frequency or the duty cycle to perform voltage matching with the signals applied to the input (E1), and also the value of the voltage surge generated in logic high state (1) by the inductance coil (L) when switching of the transistor (TR) to the off state takes place.

Abstract: Even if a power supply potential VDD of a core section is set in an off state, a latch of a level conversion circuit holds a value corresponding to an output. It is, therefore, possible for a semiconductor device to hold an output state of an output node. Thereafter, an enable signal is deactivated, whereby the output node can be set in a high impedance state and a bus or the like can be released to the other device.

Abstract: A voltage-boosting generator for reducing the effects due to operating voltage variation and temperature change. The generator comprises a delay line circuit and a voltage boosting circuit. The delay line circuit is used to perform a time delay according to an initial boosting signal and to produce a control signal. The voltage boosting circuit is used to boosted voltage according to the control signal.

Abstract: In a semiconductor integrated circuit having an LVT (low threshold voltage) block and an HVT (high threshold voltage) block, a power switch controls power supply to the LVT block. An output wrapper fixes a level of an output signal from the LVT block to a predetermined level when no power is supplied to the LVT block, and an input wrapper fixes a level of an input voltage inputted into the LVT block to a predetermined level when no power is supplied to the LVT block. As a result, low current consumption can be realized and malfunctions can be prevented in a power-down mode.

Abstract: A multiple voltage supply switch is disclosed. The multiple voltage supply switch includes a plurality of switching device pairs. Each switching device pair is connectable between an associated one of a plurality of voltage supplies and an output of the switch. Each switching device pair includes a first switching device connected to the associated one of the plurality of voltage supplies and a second switching device connected in series between the first switching device and the output of the switch. Both the first and second switching devices are activated to connect the associated one of the voltage supplies to the output of the switch and at least one of the first or the second switching devices of each of the other switching device pairs are inactivated to disconnect the voltage supply associated with the other switching device pairs from the output of the switch.

Abstract: A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.