Abstract: The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least one source driver IC. In addition, a first terminal of the first resistor is electrically connected to a DC voltage and the first terminal of each of the remaining resistors is electrically connected to the second terminal of the previous resistor. The second terminal of the last resistor is grounded. The buffers and the resistors are correspondingly electrically connected, wherein the first terminals of the resistors are electrically connected to their corresponding input terminals of buffers. Moreover, the output terminals of the buffers are electrically connected to source driver ICs, wherein the buffers are one of the built-in buffers in each source driver IC.

Abstract: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage.

Abstract: A voltage level control device operable to control a voltage level supplied from a first voltage level source to circuitry, said circuitry being arranged between said first voltage level source and a second voltage level source, said first and second voltage level sources being operable to output different voltage levels; said voltage level control device comprising: a power transistor operable to be connected between said first voltage level source and said circuitry, said power transistor comprising a sleep signal input operable to receive a sleep signal; a switching device arranged in parallel with said power transistor and comprising a sleep signal input operable to receive a pseudo sleep signal; wherein said voltage level control device is operable in dependence upon said sleep signal and said pseudo sleep signal to output to said circuitry an output voltage said output voltage comprising one of three voltage levels, said three voltage levels lying between voltage levels output by said first and second v

Abstract: A system, method and device for managing power distribution on a shared bus system that interconnects multiple devices each containing a signal termination component are disclosed herein. In one embodiment, the method of the invention includes detecting and communicating thermal indicia of one or more of the devices in the shared bus system to a memory controller device. The memory controller includes an on-die termination control circuit for setting and resetting the enablement of the signal termination components of the one or more devices. In a preferred embodiment, the on-die termination control circuit sets and resets the enablement of the signal termination components in accordance with the determined thermal indicia.

Abstract: A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, and coupling second ends of the power switches to a power receiver of the logic circuit.

Abstract: A semiconductor device includes a transmitter, a termination resistance adjusting section, a transmitter control section and a control signal generating section. The transmitter has two output terminals and operates based on a control current. The termination resistance adjusting section is connected with the output terminals of the transmitter and applies a termination resistance adjusted in response to a control signal to each of the output terminals of the transmitter. The transmitter control section supplies the control current to the transmitter in response the control signal. The control signal generating section compares a first voltage corresponding to an external resistance and a second voltage corresponding to an internal resistance whose precision is lower than that of the external resistance, and outputs the control signal to the termination resistance adjusting section and the transmitter control section based on the comparing result.

Abstract: There is provided apparatus for connecting between a data source or a data receiver and a data line. The apparatus comprises an impedance and an impedance controller arranged to continually adjust the value of the active impedance so as to control the relative impedances of the total source, the total source comprising the data source and the impedance, and the data line or of the total receiver, the total receiver comprising the data receiver and the impedance, and the data line. There is also provided a semiconductor chip, connectable to a data line, the semiconductor chip comprising the apparatus together with a data source or data receiver, as appropriate. There is also provided a method for controlling impedance matching between a data source or data receiver and a data line.

Abstract: Apparatus and method for providing reference voltages for differential signaling with tracking of output differential voltage relative to output offset voltage are described. A swing reference voltage, an offset reference voltage, a swing feedback voltage, and an offset feedback voltage are obtained. Differences between pairs of these voltages are differentially amplified to produce first and second bias voltages. Pull-up and pull-down voltages are driven partially responsive to the first bias voltage and the second bias voltage to provide first and second control voltages. The first control voltage may be provided to a first resistance for the driving of the first pull-up and pull-down voltages. The second control voltage may be provided to a second resistance for the driving of the second pull-up and pull-down voltages. The first control voltage and the second control voltage may be provided to a third resistance.

Abstract: A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.

Abstract: An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

Abstract: An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance connection circuit connects a capacitance between the first and second differential output nodes. The capacitance connection circuit then adjusts the value of the capacitance in accordance with a control signal.

Abstract: The circuit arrangement comprises a driver stage and a control circuit coupled to the control input of a switching transistor. The driver stage provides a switching voltage for the operation of the switching transistor, and the control circuit provides a shaping of the switching voltage in the sense of delaying the switching through of the switching transistor. The control circuit comprises in particular a control transistor, which is coupled a control input via a high pass filter to the output of the driver stage and with an current input to the control input of the switching transistor. The switching transistor is for example a MOSFET being used for switching on and off a capacitive load.

Abstract: First and second transmission lines and are connected to each other in series. A first terminator is connected to the first transmission line in parallel, and is provided externally of a semiconductor device. A second terminator is connected to the second transmission line in parallel, and is provided inside the semiconductor device. The values of the first and second terminator are adjusted so that the combined resistance value of first and second terminator and the second transmission line matches with the impedance of the first transmission line. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted.

Abstract: A tristate operating mode setting device is proposed, which is designed for use with an electronic circuit unit for providing the electronic circuit unit with a tristate operating mode setting function, and which is characterized by the utilization of a specially-designed logic circuit and logic control signal generator to allow the electronic circuit unit to be selectively set to one of three different operating modes during startup through a connecting pad that can be externally connected in three different ways. This feature allows one single pad for the provision of three different operating mode settings, whereas prior art is only capable of providing two different settings. The electronic circuit unit is therefore able to use fewer number of pads to provide an increased number of operating mode settings, with the benefit of reducing layout space on circuit board.

Abstract: Circuits and methods are provided for producing a rail-to-rail output voltage. A circuit includes a level shifter, a source follower, and a current compensation circuit. The level shifter receives an input signal and applies a compensation voltage to the input signal relative to a voltage level of the input signal in steady-state. The source follower produces an output signal and, responsive to variations in the voltage level of the input signal, changes the voltage level of the output signal using a biasing current. The current compensation circuit, responsive to a difference between the voltage levels of the input and output signals, varies an amount of the biasing current.

Abstract: A programmable output buffer providing variable drive strength and slew rate for a given noise limit that includes a driver stage that generates the output of the buffer and a plurality of selectively enabled switching elements, at least a predriver stage providing a plurality of selectable switching elements that enables the selected drive stage switching elements, and a selection means that enables the required predriver switching elements in the desired sequence to provide the desired drive strength and slew rate.

Abstract: A current limiter of an output transistor comprises an output transistor, a current detection transistor monitoring a current flowing through the output transistor, a current mirror circuit, a protection transistor outputting a current having passed through the current mirror circuit, the current being proportional to the monitored current and dependent on a voltage between a drain and a source or between a collector and an emitter of the output transistor and an input terminal connected to an output of the protection transistor.

Abstract: An input signal is transmitted from a first device to a second device. At the second device the input signal method is received, and an output signal is generated in response to the input signal. The output signal is sensed, and the input signal is dynamically terminated in response to sensing the output data. In some embodiments, the receiving, generating and dynamically terminating occur within a single integrated circuit. In some embodiments, the method includes detecting a signal voltage level of the input signal and causing a termination voltage level to change from a first voltage level to a second voltage level in response to the signal voltage level.

Abstract: To transmit a high-speed digital signal of several tens GHz via a differential line by connecting a differential line referring to the ground to differential lines not referring to the ground, there is provided a signal transmission system which transmits a digital signal between circuit blocks via a signal transmission line, each of the circuit blocks basically including a functional circuit, a reception/transmission circuit formed separately from the functional circuit and an impedance-matched transmission line (115) formed between reception and transmission ends of the reception/transmission circuit; a differential line (105) referring to the ground (110), led out from a differential output driver, being formed from differential signal lines disposed symmetrically with respect to the ground (110) in the circuit block, only differential pair lines (111, 112) not referring to the ground being extended directly from the differential signal lines disposed symmetrically with respect to the ground in the signal

Abstract: A system and method is disclosed for providing a fast turn on bias circuit that permits a fast transition from an idle “power down” state to an active “power up” state in current mode logic (CML) transmitter output circuits. The invention comprises a capacitor coupled to a bias transistor and a charge switch circuit for controlling the operation of the capacitor. The capacitor has a value of capacitance that is equal in magnitude and opposite in sign to the Miller coupling capacitance in the bias transistor. The capacitor compensates for the Miller coupling capacitance within the bias transistor in less than ten nanoseconds. This permits a CML transmitter to more quickly restart the transmission of data after an active state has been initiated.

Abstract: Methods and apparatus for correcting for circuit self-heating replicate a thermal characteristic of a component that may be coupled to a bias circuit. A bias circuit may include replication component coupled to a reference cell. The replication component may be included in a feedback loop with the reference cell to improve accuracy.

Abstract: A power management circuit for logic cells. A logic cell is operated in normal or standby modes according to a power control signal. The logic cell includes an output terminal and a power input terminal. A switch is coupled between a power voltage, the power control signal and the power input terminal. That switch is turned off to disconnect the power voltage and the logic cell when the power control signal is at a predetermined level. This results in the logic cell operating in standby mode. A latch circuit is coupled between the power voltage and the output terminal to preserve the voltage level of the output terminal when the logic cell operates in standby mode.

Abstract: Apparatus and method of tuning a digitally controlled input/output (I/O) driver of an integrated circuit for parameter variation compensation, a bus impedance of the I/O driver being controlled by a first digital code comprises in one embodiment: controlling a bus impedance of a reference I/O driver network by a second digital code; monitoring a voltage potential of the bus and generating the second digital code based on the monitored bus voltage potential; and tuning the second digital code to generate the first digital code.

Abstract: System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.

Abstract: A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and selectively adjusted. The PVT controller permits selection between PVT sensing circuit-provided control signals and control signals stored in a hardware register for controlling drive strength. The PVT controller further provides the capability to offset the selected drive strength by a fixed amount and select whether or not the offset is applied and permits full testability and observability of the selected control signal, an offset value applied thereto, and the resulting output signal.

Abstract: Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper dumps charges at least one of from and to the circuit location, wherein the charge dumper comprises at least one gating transistor to dump the charges, the at least one gating transistor is directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

Abstract: System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.

Abstract: The present invention is a device and method to change the reflection time of a bidirectional signal so as to cause a false data value to be correctly seen as the proper data value when the bidirectional signal travels between a first semiconductor chip and a second semiconductor chip, through a transmission line between the two semiconductor chips. The reflection time is adjusted by coupling an electrical network to the transmission line to cause an early electrical reflection. In one embodiment, the network is coupled to establish an impedance discontinuity between the board trace and the package trace.

Abstract: A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of data signal outputs, a first PMOS transistor and a second PMOS transistor. A first switch is coupled between a power voltage, the power control signal and the logic cell. A latch circuit coupled between the power voltage and the data signal outputs preserves the voltage levels respectively of the complementary pair of data signal outputs when the logic cell operates in the standby mode.

Abstract: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf?Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

Abstract: When an output voltage output from a buffer approaches a ground voltage, a MOS transistor turns off, so that clamp for a gate of the MOS transistor is released.

Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

Abstract: An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).

Abstract: Power is gated from global terrain to a voltage island while controlling leakage and managing transient power supply noise. The voltage island includes a field effect transistor (FET) power gate, a first connection to a global voltage source and a second connection to a disable signal source, and an island voltage net for supplying voltage to devices on the island. A power gate control circuit is responsive to the disable signal source for generating a test signal for selectively turning off the FET power gate as the disable signal source goes to a logical ‘1’, and for turning on the FET power gate as said disable source goes to a logical ‘0’. The FET power gate is responsive to the disable signal source being off for connecting the island voltage net to the global voltage source.

Abstract: A GTL output structure having an active charging and discharging stage that actively restores internal nodes for slew rate control without the need to wait for a slow rise and fall RC time constant is disclosed herein. The novel GTL output structure includes an input stage connected to an RC network for providing slew rate control. The output stage connects between the RC network and a feedback network. The feedback network in includes an active charging stage for providing a charging current to the gate of the at least one transistor for a period of time to the value of a power supply rail and wherein the feedback network includes an active discharging stage for providing a discharge current from the gate of the at least one transistor to ground.

Abstract: A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node and the N channel MOS transistor and turned on/off in response to a control signal are provided. The input signal is at the L level in a standby state. The control signal is at the L level in the standby state and at the H level in the active state. This suppresses the effect of hot carriers in the active state and decreases a subthreshold current in the standby state.

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: The output of an open-collector comparator and a programmable logic device are connected to a high voltage differential device. In conjunction with the comparator output, the programmable logic device controls the diffsense prime signal sent to the high voltage differential device in order to switch it on or off.

Abstract: The power supply-voltage dependency of a current source current is reduced and the power supply voltage is lowered. The invention includes an emitter-coupled logic circuit 118 and a reference-voltage generating circuit 119 for generating a reference voltage VCSC for controlling a drain current (=current source current ICS) of a constant current-supplying n-type MOS transistor 110. The emitter-coupled logic circuit 118 comprises a current switch made up of a pair of emitter-coupled bipolar transistors 106 and 107, a constant current-supplying n-type MOS transistor 110 that is connected in series with the current switch, and resistor means 108 and 109 connected in series with the bipolar transistors 106 and 107 individually for obtaining an output voltage.

Abstract: Input circuit and method for setting a termination voltage. One embodiment provides a method for setting a termination voltage of an input circuit of an integrated circuit, the input circuit having an input terminal for receiving a signal, the termination voltage being applied to the input terminal, the received signal being driven with respect to the termination voltage and being evaluated by a comparison with a reference potential, the termination voltage being generated and being set in accordance with a control signal, the control signal being generated in a manner dependent on a comparison of one or more signal levels of the received signal with an assessment potential, the termination voltage being set by means of the control signal in such a way that the reliability of the signal reception is maximized.

Abstract: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

Abstract: An integrated circuit includes at least one main circuit 313 operable to perform one or more functions. At least one termination node DQ receives or transmits an operating signal. An active termination circuit 301 has first and second transistors of opposite type coupled in series between a Vdd node of a first source potential and a Vss node of a second source potential. The at least one termination node is coupled to a common node between the first and second transistors. A control circuit operates to bias the first and second transistors such that they exhibit a controlled impedance at the common node. Alternatively, the control circuit operates to bias the first and second transistors such that they provide a clamping function at the common node.

Abstract: A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.

Abstract: A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.

Abstract: Semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected by a bidirectional bus which is a transmission line. A driver is of a push-pull type and a reception side is CTT-terminated. If a terminating resistor is in conformity with the characteristic impedance of the transmission line, the on resistance of the driver is equal to or lower than the characteristic impedance. If the on resistance of the driver is in conformity with the characteristic impedance of the transmission line, the value of the terminating resistor is equal to or lower than the characteristic impedance of the transmission line. If the reception side is VTT-terminated, the value of the VTT is ½ of a lower one of power supply voltages that are supplied to the respective semiconductor integrated circuit devices. The value of the terminating resistor is in conformity with the characteristic impedance of the transmission line.

Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

Abstract: A transmission line circuit includes a line driver having first and second outputs coupled through a differential transmission line to first and second inputs of a line receiver. A first bias is provided between the first and second inputs of the line receiver. The second bias is applied between the first and second outputs of the line driver. As a result, the first and second biases substantially offset, and preferably cancel, each other. If the differential transmission line is not coupled to a line driver, the second bias associated with that line driver is not applied permitting the first bias to provide a relatively high noise margin.

Abstract: The invention provides a high-speed buffer that may used at the input of an integrated circuit, such as an input buffer. This buffer may be configured for use as a standard buffer with a single switching threshold, such as a TTL-to-CMOS buffer, or used as a Schmitt trigger with hysteresis, which as at least two switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: An apparatus and method thereof to correct a reference voltage, Vref, include a first digital device and a second digital device to input/output digital data via a bus, an adjustable resistor providing a main supply voltage VDD, a fixed resistor, wherein the adjustable resistor and the fixed resistor generate a Vref correction by dividing the main supply voltage VDD. A Vref setup selecting part of the apparatus and method selects the Vref correction and a Vref controller changes a resistance value of the adjustable resistor according to a selection of the Vref correction through the Vref setup selecting part, determines an optimum resistance value of the adjustable resistor, and outputs an optimum Vref correction.

Abstract: The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.