Abstract: An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage through a pull up transistor if the input signal at the input terminal is at a “low” level. Termination circuits are provided including on die termination circuits.

Abstract: A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination resistance circuit to provide a termination resistance for the I/O circuit. The integrated circuit may further include control logic to establish an initial termination resistance during a preamble associated with the command. Other embodiments are described and claimed.

Abstract: A receiver circuit arrangement includes a receiver circuit an input for receiving an input signal an output for outputting an output signal and an inverter circuit with switching transistors. The input signal is fed to the receiver circuit. At least one control transistor is connected in series with the switching transistors. A control circuit is connected on the input side to a terminal for a reference voltage and on the output side to the control terminal of the control transistor of the inverter circuit. The control circuit is designed such that the control transistor is driven by the regulating switching circuit in the event of deviations of the reference voltage from a voltage value in a reference operating state with a control voltage that deviates with respect to the reference operating state.

Abstract: A circuit for controlling impedance may include an impedance adjustment circuit and a control signal generation circuit. The impedance adjustment circuit may adjust an impedance value based on a control signal. The control signal generation circuit may provide the impedance adjustment circuit with a control signal that corresponds to one of an impedance value at a first clock cycle and an impedance value at a second clock cycle that approaches a target impedance.

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: A semiconductor integrated circuit with low power consumption is provided. In one embodiment, the semiconductor integrated circuit includes a logic circuit portion that is connected between a first power line and a virtual ground line. The logic circuit portion includes at least one NMOS transistor having a first threshold voltage and at least one PMOS transistor having a second threshold voltage. The semiconductor integrated circuit further includes a first MOS transistor, which is connected between the virtual ground line and a ground voltage, where the first MOS transistor has the first threshold voltage and applies the ground voltage to the virtual ground line in an active state.

Abstract: An on-DRAM termination resistance control circuit is capable of controlling resistance of an IC termination and minimizing area for the resistance control circuit by using a simplified circuit scheme. The on-DRAM termination resistance control circuit includes a push-up resistance adjusting unit, a pull-down resistance adjusting unit and resistance adjustment control unit. The push-up resistance adjusting unit adjusts resistances of a first and a second inner resistors based on an external reference resistor. The pull-down resistance adjusting unit adjusts a resistance of a third resistor based on the second inner resistor that is adjusted by adjustment of the push-up resistance control unit. The resistance adjustment control unit controls to alternatively repeat the operation of the push-up resistance adjusting unit and the pull-down resistance adjusting unit for a predetermined number of adjustment times.

Abstract: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.

Abstract: A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.

Abstract: An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance connection circuit connects a capacitance between the first and second differential output nodes. The capacitance connection circuit then adjusts the value of the capacitance in accordance with a control signal.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: First and second transmission lines and are connected to each other in series. A first terminator is connected to the first transmission line in parallel, and is provided externally of a semiconductor device. A second terminator is connected to the second transmission line in parallel, and is provided inside the semiconductor device. The values of the first and second terminator are adjusted so that the combined resistance value of first and second terminator and the second transmission line matches with the impedance of the first transmission line. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted.

Abstract: Circuits and methods are provided for producing a rail-to-rail output voltage. A circuit includes a level shifter, a source follower, and a current compensation circuit. The level shifter receives an input signal and applies a compensation voltage to the input signal relative to a voltage level of the input signal in steady-state. The source follower produces an output signal and, responsive to variations in the voltage level of the input signal, changes the voltage level of the output signal using a biasing current. The current compensation circuit, responsive to a difference between the voltage levels of the input and output signals, varies an amount of the biasing current.

Abstract: A programmable output buffer providing variable drive strength and slew rate for a given noise limit that includes a driver stage that generates the output of the buffer and a plurality of selectively enabled switching elements, at least a predriver stage providing a plurality of selectable switching elements that enables the selected drive stage switching elements, and a selection means that enables the required predriver switching elements in the desired sequence to provide the desired drive strength and slew rate.

Abstract: A current limiter of an output transistor comprises an output transistor, a current detection transistor monitoring a current flowing through the output transistor, a current mirror circuit, a protection transistor outputting a current having passed through the current mirror circuit, the current being proportional to the monitored current and dependent on a voltage between a drain and a source or between a collector and an emitter of the output transistor and an input terminal connected to an output of the protection transistor.

Abstract: Methods and apparatus for correcting for circuit self-heating replicate a thermal characteristic of a component that may be coupled to a bias circuit. A bias circuit may include replication component coupled to a reference cell. The replication component may be included in a feedback loop with the reference cell to improve accuracy.

Abstract: The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

Abstract: Apparatus and method of tuning a digitally controlled input/output (I/O) driver of an integrated circuit for parameter variation compensation, a bus impedance of the I/O driver being controlled by a first digital code comprises in one embodiment: controlling a bus impedance of a reference I/O driver network by a second digital code; monitoring a voltage potential of the bus and generating the second digital code based on the monitored bus voltage potential; and tuning the second digital code to generate the first digital code.

Abstract: An impedance matching circuit has comparator, counter, two current sources, semiconductor resistance device, and variable MOS impedance device. The current sources are respectively coupled to an internal impedance device and an external impedance device. The comparator has two input terminals and an output terminal. The input terminals of the comparator are coupled to the internal and external impedance devices. The output terminal of the comparator is coupled to the counter. The variable MOS impedance device is coupled between the counter and the semiconductor impedance, and is controlled by the counter. When the voltages of the internal impedance and the external impedance are not matched, the variable MOS impedance device can provide the compensating impedance by adjusting the counting value of the counter.

Abstract: A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.

Abstract: When an output voltage output from a buffer approaches a ground voltage, a MOS transistor turns off, so that clamp for a gate of the MOS transistor is released.

Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

Abstract: An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).

Abstract: An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage through a pull up transistor if the input signal at the input terminal is at a “low” level. Termination circuits are provided including on die termination circuits.

Abstract: Power is gated from global terrain to a voltage island while controlling leakage and managing transient power supply noise. The voltage island includes a field effect transistor (FET) power gate, a first connection to a global voltage source and a second connection to a disable signal source, and an island voltage net for supplying voltage to devices on the island. A power gate control circuit is responsive to the disable signal source for generating a test signal for selectively turning off the FET power gate as the disable signal source goes to a logical ‘1’, and for turning on the FET power gate as said disable source goes to a logical ‘0’. The FET power gate is responsive to the disable signal source being off for connecting the island voltage net to the global voltage source.

Abstract: A circuit module comprises a first circuit chip (102a) and a second circuit chip (102b). Each circuit chip comprises a signal input (104a, 104b) and a reference input (106a, 106b). A first termination resistance (112) connects the signal inputs (104a, 104b) and a second resistance (114) connects the reference inputs (106a, 106b). A first termination resistance (116) connects the second signal input (104b) to the termination voltage (120) and a second termination resistance (118) connects the second reference input (106b) to the termination voltage (120). A first ratio between the first resistance (112) and the first termination resistance (116) corresponds to a second ratio between the second resistance (114) and the second termination resistance (118).

Abstract: Disclosed is an output driver having an output port for outputting a data signal, a level shifter for driving a current to the output port in response to a current control input, an adjustable impedance controller for generating an impedance adjustment signal; an output impedance compensator for adjusting the impedance of the level shifter in accordance with the impedance adjustment signal and in accordance with a reference voltage, and a tracking circuit, including a process and temperature monitor responsive to manufacturing process and temperature variations of the output driver, a frequency monitor responsive to the frequency of an input clock signal, and a voltage supply monitor responsive to an internal power supply voltage. The process and temperature monitor, frequency monitor and voltage supply monitor are interconnected so as to generate the reference voltage.

Abstract: A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

Abstract: An integrated circuit provides dynamic, on chip resistor trimming, including a digital control loop for stabilizing impedance matching among multiple devices communicatively linked over a data transmission line. The digital control loop stabilizes input/output impedance matching of various devices to within a precise ohmic range that is far narrower than standard process variations, such as sheet resistance, within the components themselves. The impedance matching circuit also overcomes EMI problems normally associated with digital control and thus provides dynamic on-chip digital control without non-linearity and with tighter tolerance than is presently possible. Accordingly, the circuit boosts performance of peripheral devices that communicate over a standard USB port, without the need for a computer as a go between or intermediate interface. This makes device to device communication possible as between USB On-the-Go capable devices.

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: Input circuit and method for setting a termination voltage. One embodiment provides a method for setting a termination voltage of an input circuit of an integrated circuit, the input circuit having an input terminal for receiving a signal, the termination voltage being applied to the input terminal, the received signal being driven with respect to the termination voltage and being evaluated by a comparison with a reference potential, the termination voltage being generated and being set in accordance with a control signal, the control signal being generated in a manner dependent on a comparison of one or more signal levels of the received signal with an assessment potential, the termination voltage being set by means of the control signal in such a way that the reliability of the signal reception is maximized.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.

Abstract: A variable keeper strength based process-compensated dynamic circuit and method provides a robust digital way to overcome the intrinsic parameter variation present in manufactured die. Using a process-compensated dynamic circuit, the wide robustness and delay distribution becomes narrower which improves performance without sacrificing worst-case robustness. The strength of the keeper is programmed depending on the amount of die leakage. The keeper will have an optimal strength for the best and worst case leakage, allowing better performance with improved worst-case robustness.

Abstract: An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Abstract: The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be selected such that strength of the output buffer matches the then existing load. In other words, the strength may be only as much as needed to drive the then existing load. As a result, effects such as switching noise may be considerably reduced.

Abstract: In an output buffer apparatus including a main-buffer circuit including a plurality of first transistors each connected between a first power supply terminal and an output terminal and a plurality of second transistors each connected between a second power supply terminal and the output terminal, and a pre-buffer circuit including a plurality of first pre-drivers each driving one of the first transistors in accordance with a data signal and a plurality of second pre-drivers each driving one of the second transistors in accordance with the data signal, a plurality of first sequential circuits are provided for receiving first impedance adjusting signals in synchronization with the data signal to turn ON the first pre-drivers, and a plurality of second sequential circuits are provided for receiving second impedance adjusting signals in synchronization with the data signal to turn ON the second pre-drivers.

Abstract: An input level translator circuit is provided. The translator circuit is configured to convert a full-range signal into a low-range signal and a high-range signal. A first pass transistor is configured to restrict the voltage of the full-range signal to provide a high-range voltage at a high-range node when the full-range signal corresponds to a logic 0. A second pass transistor is configured to restrict the voltage of the full-range signal to provide a low-range voltage at a low-range node when the full-range signal corresponds to a logic 1. A first switch circuit is configured to couple the high-range to a first cascode bias signal when the full-range voltage corresponds to a logic 1. A second switch circuit is configured to couple the low-range node to a second cascode bias signal when the full-range voltage corresponds to a logic 0.

Abstract: A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.

Abstract: A semiconductor package contains at least one electrically isolated channel. The isolated channel is minimally susceptible to crosstalk from other channels in the package. Specifically, the level of crosstalk that may impinge on the isolated channel is below an acceptable threshold so as to permit the isolated channel to function correctly. The semiconductor package may be a FET switch assembly and the isolated channel may be used for a clock signal to prevent crosstalk contamination caused by the data signals.

Abstract: One embodiment of the present invention provides a system that amplifies capacitively coupled inter-chip communication signals. During operation, the system transmits a signal through a capacitive transmitter pad and receives a corresponding input signal through a capacitive receiver pad. The system amplifies the input signal by feeding it through a number of cascaded CMOS inverters operating from ever-increasing power supply voltages from the first to the last inverter.

Abstract: A low voltage differential signal driver that generates a differential signal using a switching sequencer for ensuring uniform transitions of the output signals, and a driver that includes a network of matched resistors for generating the output signals. The network of matched resistors can be configured based on one or more sequencing signals generated by the switching sequencer.

Abstract: An output impedance bias compensation system for adjusting output impedance of at least one output including a reference impedance generator, an impedance matching controller, at least one output impedance generator, and a programmable bias controller. The reference impedance generator develops a reference impedance based on a reference value. The impedance matching controller continually adjusts an input of the reference impedance generator to match the reference value within a predetermined tolerance. Each output impedance generator is coupled to a corresponding output and is controlled by an output impedance control input. The programmable bias controller combines a bias amount with the value of the input of the reference impedance generator to provide the output impedance control input. The bias controller is programmable to provide a bias amount to compensate for any process variations between the reference impedance generator and each output impedance generator.

Abstract: A method to establish an adjustable on-chip impedance within a predetermined range that involves establishing a reference current for the adjustable on-chip impedance and applying this reference current to the adjustable on-chip impedance. A voltage produced by applying the reference current to the adjustable on-chip impedance is sensed and compared with the comparator or other similar processor to a reference voltage. This comparison allows the adjustable on-chip impedance to be tuned when the comparison of the sense voltage and the reference voltage is unfavorable. Tuning the impedance results in an impedance value within a predetermined range that accounts for variances of both the reference current and reference voltage.

Abstract: A method and apparatus are provided for implementing power control in multi-voltage input/output (I/O) circuits. First current biasing devices are provided for creating a first constant bias current. Second current biasing devices are provided for creating a second bias current. The second current biasing devices are activated at a first voltage and are deactivated at a second voltage. The first voltage is less than the second voltage.

Abstract: An integrated circuit is disclosed that includes one or more blocks of switching logic (comprised of transistors) connected between a power supply and a common node. A control transistor connects the common node to ground. The control transistor has a higher threshold voltage level than the voltage threshold level(s) of the transistors that comprise the switching logic blocks. A bias generator provides a positive bias to the body of the control transistor when the control transistor is “on.” Further disclosed is an integrated circuit comprising a first plurality of serially connected transistors establishing a first current path from a voltage source to ground and a second plurality of serially connected transistors establishing a second current path from the voltage source to ground. The first and second plurality of transistors each includes at least one high-threshold transistor.

Abstract: The present invention relates to a resistance calibration circuit to correct a resistance variation in an output terminal of a semiconductor device. The resistance calibration circuit according to the present invention includes: a correction code generator for generating a plurality of push-up code signals and a plurality of pull-down code signals based on an external reference resistor, wherein a reference voltage is applied to the correction code generator; a push-up decoder for decoding the plurality of push-up code signals from the correction code generator; a pull-down decoder for decoding the plurality of pull-down code signals from the correction code generator; and a resistance adjustor for receiving a push-up signal from the push-up decoder and a pull-down signal from the pull-down decoder and for turning on/off a plurality of inner transistors.