Abstract: This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

Abstract: A CMOS delay cell with feedback circuitry to ensure that the delay cell is operating in saturation mode. A voltage controlled oscillator (VCO) comprising a loop of an odd number of delay cells, where the VCO is operating in a saturation mode. Under normal operation any intermediate node in the VCO will generate an output signal from a delay cell with reduced supply noise. The output signal can be used to generate a PLL clock signal with a lower phase jitter than prior art VCO's operating at low supply potentials.

Abstract: A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

Abstract: A device for driving a load controllable by current capable of increasing speed to turn on an output stage transistor is provided. The device includes: (a) a power source terminal; (b) a switching circuit for switching flow of current and non-flow; and (c) a current mirror circuit connected between an output terminal of the switching circuit and the power source terminal.

Abstract: This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks.

Abstract: A memory device includes a plurality of PMOS transistors and a voltage regulator circuit. Each transistor has a gate, a source region, a drain region, and a well containing the source and drain regions. Each transistor is characterized by a threshold voltage which is dependent on temperature and on a body-source bias voltage. Each transistor is also characterized by a sub-threshold current which is dependent on the transistor's threshold voltage. The voltage regulator circuit is operatively coupled to each well to provide the body-source bias voltage to each well. The voltage regulator circuit temperature-compensates the body-source bias voltage to maintain the threshold voltage of each transistor approximately constant despite changes in temperature. The memory device thus advantageously has a relatively constant stand-by current despite temperature variations.

Abstract: An input buffer circuit is implemented in a compound semiconductor technology such as Gallium Arsenide and converts silicon semiconductor logic levels such as those produced by CMOS and TTL integrated circuits and converts them to logic levels compatible with circuits manufactured in compound semiconductor technology. The input buffer employs a balanced input circuit designed to produce an output voltage representing the switch-point of the compound semiconductor technology when the voltage received from a silicon semiconductor circuit equals the switch-point of the silicon semiconductor circuit. Otherwise, the output voltage of the input buffer is proportional to the difference between the voltage received from the silicon semiconductor circuit and the switch-point of the silicon semiconductor circuit. The balanced input circuit minimizes variations in its output voltage due to variations in power supply voltage, circuit temperature and process parameters.

Abstract: An output buffer having a data input terminal, a data output terminal, a predriver stage, an output stage and a resistive device. The predriver stage includes a first pull-up transistor and a first pull-down transistor which have control terminals coupled to the data input terminal and have first and second outputs, respectively. The output stage includes a second pull-up transistor and a second pull-down transistor which have control terminals coupled to the first and second outputs, respectively, and have third and fourth output terminals coupled to the data output terminal. The resistive device is coupled between the control terminals of the second pull-up and pull-down transistors.

Abstract: According to the present invention, an integrated circuit device is capable of responding to more than one input threshold voltage level by making only minimal changes to the device. The input buffer of the integrated circuit device is modified to be a programmable buffer that is controlled by a control input signal which may be generated by several different control means. Such control means include a bond option, a mask option, a fuse option, a register option, and a voltage detector option.

Abstract: An output buffer circuit is provided, which enables to reduce the delay of a digital output signal with respect to an input digital signal. The output buffer circuit includes first and second FETs serially connected to each other. A gate of the first FET is applied with a first digital input signal. A gate of the second FET is applied with a second digital input signal. The first and second FETs operate to be opposite or complementary in logic state to each other. A digital output signal is taken out from a connection point of the first and second FETs. The circuit further includes a current source for causing a bias current having the same direction or polarity as that of a drain current of the first FET to flow through the first FET in the pseudo-OFF state. A turn-on speed of the first FET from the pseudo-OFF state to the ON state is enhanced by the bias current.

Abstract: The output impedance in a CMOS output driver stage is programmed and compensated by complementary current mirrors that are MOS devices in series with each of the conventional pull-up and pull-down devices. The conduction of these additional complementary devices is controlled according to complementary programming signals that are compensated for variations in manufacturing process parameters as well as for changes in temperature. A P-type programming signal may be referenced to +VDD and be produced from an N-type programming signal referenced to GND by the action of a gate voltage mirror that includes symmetrical N-type and P-type FET's in series. The N-type programming signal may be produced in the first instance from the gate voltage of an N-type FET used in a feedback loop that servos an external programming voltage to track an internally generated reference voltage. That gate voltage exhibits variations that reflect differences attributable to both process variations and to temperature.

Abstract: A transfer gate is provided between an input terminal, receiving voltage Vh of the super Vcc level when a special operating mode is set, and an inverter and an n channel MOS transistor included in a super Vcc detection circuit of a DRAM. The transfer gate is rendered conductive only during a potential detection period during which signal WCBR attain an "H" level. Therefore, a leakage current flowing from the input terminal through the n channel MOS transistor to a ground terminal can be minimized, thereby reducing a consumed current.

Abstract: A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points.

Abstract: The control voltage .phi.1 outputted by the control voltage generating circuit 1 is at a low level in a range where an external supply voltage Vcc is lower than the threshold value of the transistor P1, but increases continuously in analog manner when the external supply voltage Vcc rises. After having matched the external supply voltage Vcc, the control voltage .phi.1 increases in the same way as the external supply voltage Vcc. By use of the control voltage provided with the characteristics as described above for an output circuit, controlled is the gate of a transistor P4 of a low-voltage operating output section 6 operative only at a voltage lower than a predetermined value. The transistor P2 of a full-voltage operating output section 5 of the output circuit is always operative on the basis of the control signal .phi.H of the data output control circuit 3.

Abstract: A method and apparatus are disclosed for sending and receiving logic signals responsive to external digital data input and control signals. A reference circuit providing a first and second reference signal is common to the signal generating and receiving circuitry. The signal generating circuitry includes a signal source connected to the transmission line for generating a variable level digital signal, and a reference level adjusting and switching circuit ("RLA/S circuit") which is responsive to the digital data input and the first reference signal. The RLA/S circuit is connected to the signal source for selecting the level of the variable level digital signal and providing a switching signal. The signal source output is thus adjusted and switched so that the signal source generates a digital signal to the transmission line which follows the digital data input at the selected output signal level.

Abstract: A buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied.

Abstract: A potential supplied to a first node from an inverter having an NMOS and a PMOS both series-connected between a constant potential node (V.sub.DD or GND) and the first node is switched according to a signal input to the inverter. The NMOS can be prevented from being brought into conduction beyond need, thereby making it possible to reduce an on-quiescence current.

Abstract: A voltage supply isolation buffer which prevents a voltage applied to an input or output of an IC device from reaching the power supply plane of the device. An inverter circuit is modified such that Vdd is coupled to the source of the p-channel pull-up transistor through a pn diode with the p terminal coupled to Vdd and the n terminal coupled to the source of the p-channel transistor. Under normal operation, Vdd forward biases the diode allowing a high voltage to be applied to the output of the inverter circuit when the p-channel transistor turns on. If, however, a voltage is applied to the output of the inverter circuit by an external voltage supply which is higher than Vdd, the diode will be reverse biased, preventing the voltage at the output node from raising the Vdd level.

Abstract: A buffer circuit which exhibits increased speed in transitions between binary states. A control transistor is coupled between a pull-up transistor and an input terminal. During low-to-high input signal transitions, the control transistor limits the signal swing at the input terminal such that small variations in the input terminal voltage result in larger voltage variations at the output terminal. During such transitions, the control transistor simultaneously decouples the input terminal from the pull-up transistor, thereby decoupling the input capacitance from the pull-up transistor. As a result, the speed with which the pull-up transistor can pull the output high is increased. As the number of input signal desired to be processed increases, the reduction in logic transition time becomes more significant. Some versions further include a pull-down transistor having a control terminal coupled to the gate of the pull-up transistor and to a power-down terminal.

Abstract: A output buffer circuit incorporates an output controller and voltage controller between a first and a second voltage potential to buffer the output of data produced by a semiconductor device. The output controller provides switching control signals to transistors in the voltage controller in order to prevent the first potential from being effected by the potential at the output of the output buffer.

Abstract: A wave propagation circuit having one or more circuit stages. Each circuit stage preferably has the same number of evaluation devices as the number of logic inputs into that circuit stage. The circuit stages alternately precharge and evaluate in a serial, wavelike manner responsive to a clock signal. During the precharge cycle of the clock, a precharge pulse propagates from circuit stage to circuit stage to precharge the output nodes of the circuit stages in a distributed, serial manner. During the evaluation cycle of the clock, a pulsed data signal permits the first stage to evaluate its inputs. Responsive to the output of the first circuit stage, a second circuit stage evaluates its inputs. The circuit further includes forward conduction devices and feedback devices to improve the noise margin and to reduce output errors caused by charge sharing and charge redistribution.

Abstract: This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks.

Abstract: An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.

Abstract: An inverter circuit having a readily programmable and stable threshold voltage and low propagation delay. An input stage of the inverter includes a pair of transistors, a first one adapted to receive an input signal for inversion and being disposed in a first current path and a second one being disposed in a second current path. The input stage further comprises a third transistor connected in series with the first transistor and receiving a bias voltage. The first, second, and third transistors are all of the same type; i.e., all NMOS or all PMOS. An output stage of the inverter includes a PMOS transistor and an NMOS transistor having interconnected drain terminals at which an inverted output signal is provided. The threshold voltage about which the output signal transitions is a function of the bias voltage and characteristics of the first, second, and third transistors in the input stage.

Abstract: A timekeeping integrated circuit with devices partitioned into areas with different power supplies and level translators between the areas; the level translators use a memory cell for isolation and to shorten the signal active time for low power consumption. Also a one-wire communication port with low power input buffers may be used to detect very slowly varying voltages. The input buffers include staged decreasing resistors as a power dissipation limitation.

Abstract: A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, wherein a differential in voltage between the source node and the gate node is limited to a desired level.

Abstract: An I/O transceiver circuit for use on each integrated circuit of a multi-chip module that controls the threshold voltage of the receiver portion and also controls the output resistance of the transmitter portion. Control of the threshold voltage allows operation of the circuit at low voltage levels and with relative immunity from process and temperature variations. Control of the output resistance allows operation without characteristically terminated I/O lines between multi-chip modules, thereby saving power otherwise wasted in the terminating resistors. Control of the threshold voltage is achieved by means of a reference circuit. Control of the output resistance is achieved by a phase-locked-loop arrangement. Further, the I/O transceiver circuit may also have a state where it clamps noise pulses on its I/O line.

Abstract: A logic gate with highly matched output rise and fall times is provided which includes at least one stacked transistor pair (24) and at least one complementary stacked transistor pair (30) connected in parallel across at least one node (NODE 1 and NODE 2).

Abstract: An input buffer is described which is configurable depending on whether a 5.0 or 3.3 volt supply voltage is present, The input buffer includes two input buffer circuits. The output of a first input buffer circuit is output as valid data when the supply voltage VCC equals 5.0 volts. The output of the second input buffer circuit is output as valid data when the supply voltage VCC equals 3.3 volts.

Abstract: CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors before the gate terminals of each input switching transistor. Each shielding transistor has a gate terminal coupled to a shield voltage of a magnitude substantially midway between ground potential and the positive power supply voltage. The input signal is conveyed by the source-drain channel of the input shielding transistor to the gate of the switching transistor, while preventing the gate of the switching transistor from rising above the shield voltage, in the case of n-channel devices, or below the shield voltage, in the case of p-channel devices.

Abstract: Disclosed is a switch circuit which has a depletion mode n-channel MOSFET which can be used in a circuit allowing only a positive voltage to be supplied thereto, comprising a first D-FET having a gate for receiving an input signal, a drain for outputting an output signal and a source; a first resistor connected between the drain of the first D-FET and a positive voltage source to bias the drain of the first D-FET; a second D-FET having a gate connected to an intermittence controlling voltage source, a drain and a source connected to the positive voltage source and the source of the first D-FET 201, respectively; a second resistor connected between the gate of the second D-FET and a ground to bias the gate of the second D-FET; a constant-current source connected between each of the sources of the first and second D-FET and the ground; a bypass capacitor connected in parallel with the constant-current source and between the drain of the constant-current source and the ground to bypass an RF signal to the ground

Abstract: An integrated buffer circuit configuration has two inverters which are mutually connected in series. A circuit node lies between the two inverters. At least the first inverter is a CMOS inverter for an input signal IN. The CMOS inverter has an n-channel transistor which is connected to a first supply potential. The source of a p-channel transistor is connected with a constant current source. A first enable transistor is connected between the n-channel transistor of the first inverter and the circuit node. A second enable transistor is connected in parallel to the configuration formed by the constant current source and the p-channel transistor of the first inverter. The gates of the enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS-transistor may function as the constant current source.

Abstract: A level shift amplifier has first to n th inverters connected in series, with each positive voltage terminal of the first to n th inverter is connected to the first source line. Each negative voltage terminal of the first to (n-2)th inverter is connected to output of the second next inverter, respectively. The negative voltage terminal of the (n-1)th inverter is connected to a part of the output of the n th inverter, and the negative voltage terminal of the n th inverter is connected to the second source line. n pieces of feedback elements are connected between the input and output of each inverter. When a feedback element is established so that the gain of each inverter can be maximized, a self-bias amplifier circuit is composed. All inverters are driven by the self-bias voltage. The fine amplitude signals input to the first inverter become the output voltage of full amplitude between the first and second source lines in the n-th inverter.

Abstract: A CMOS driver circuit (20) has a high impedance driver (30) and a low impedance driver (36) connected to the near end of a transmission line (43). The output impedance of the high impedance driver (30) matches the characteristic impedance of the transmission line (43). As a digital signal from the CMOS driver circuit (20) transitions from one logic state to another, the low impedance driver (30) drives the transmission line (43) until a predetermined voltage before the signal reaches its steady state voltage. A sensing circuit (24) senses when the predetermined voltage is reached, and in response, provides a control signal to deactivate the low impedance driver (36). The high impedance driver (30) completes the signal transition. The high impedance driver (30) absorbs the reflected waves from the far end of the transmission line (43), reducing the effects of ringing, and increasing noise immunity.

Abstract: A statically operated dynamic CMOS logic gate that includes an FET logic network for performing a predefined logic function with respect to its logic inputs, an output node, a precharge transistor, and in some embodiments an evaluate transistor. During operation, the precharge transistor is first turned on by a clock signal during a precharge phase to precharge an output node of the dynamic logic gate to a first voltage state. During the precharge phase, the evaluate transistor is turned off by the clock signal. An evaluate phase typically follows the precharge phase, and during the evaluation phase, the evaluate transistor is turned on by the control signal to allow the logic network to perform the predefined logic function with respect to its inputs, and the logic network selectively charges or discharges the output node to a second voltage state via the evaluate transistor in accordance with the predefined logic function given to the logic inputs to the logic gate.

Abstract: A fast static logic gate contains a pullup logic network and a pulldown logic network configured to implement a logic function. The pullup logic network is coupled to receive gate inputs, and generates a first voltage level at a first node to represent a first state in accordance with the gate inputs and logic function. The first voltage level is less than the source voltage for the fast static logic gate circuit. A leaker circuit generates a second voltage level at the first node in response to a second state of the logic function. A driver circuit is coupled to a second node for generating an output. The pulldown logic network receives the gate inputs, and generates a second voltage level for the output to represent the second state in accordance to the gate inputs and logic function. The switch circuit couples the first node to the second node when the logic function generates the second state, and couples the source voltage to the second node when the logic function generates the first state.

Abstract: A high speed multiple input NOR gate. In an illustrative embodiment, the invention includes a plurality of pull-down transistors for providing an output signal. A pull-up transistor is coupled to the plurality of pull-down transistors for providing a drive current. A regulator is coupled to the pull-up transistor for regulating the drive current in response to temperature and power supply voltage variation so as to maintain the speed of the output signal during a low-to-high transition of the output signal. In specific implementations, the NOR gate is designed to regulate the output signal so that a high level or a low level thereof is maintained at a predetermined level.

Abstract: A structure for and method of operating a transition-controlled off-chip driver is disclosed. Turn-on of output pulling devices is controlled, while turn-off is uncontrolled. An AC voltage reference circuit dissipating essentially zero DC power provides a reference voltage for control during transition. Turn-on control dissipates during transition, and ends when transition is complete without the use of output feedback.

Abstract: A BiMIS circuit includes a load pull-up bipolar transistor, a load pull-down bipolar transistor, a first MISFET and first and second MISFETs for driving the load pull-up bipolar transistor, and a third MISFET and a second MISFET for driving the load pull-down bipolar transistor. The second MISFET has a turn-on voltage lower than the turn-on voltage of the load pull-up bipolar transistor, and the second MISFET has a turn-on voltage lower than the turn-on voltage of the load pull-down bipolar transistor.

Abstract: An input terminal is connected commonly with a first transistor gate and drain and a second transistor source having the same polarity with the first transistor. A first transistor source is connected to a voltage source. A second transistor gate is connected to the voltage source through a variable voltage source. A second transistor drain terminal is used as a current output terminal, and an input terminal is used as a voltage output terminal. The input circuit is capable of obtaining a current gain approximating "1" while input impedance variation due to input signal variation maintain suppressed smaller.

Abstract: An input buffer particularly suitable for a semiconductor device includes a CMOS inverter for buffering an input signal which varies between first and second logic levels and producing an output signal at an output node thereof which is the logical inverse of the input signal, and a compensation circuit for compensating the output signal for fluctuations thereof which are due to fluctuations of a supply voltage. The CMOS inverter preferably includes a pull-up MOS transistor having a gate, a first electrode coupled to a supply voltage, and a second electrode, and a pull-down MOS transistor having a gate, a first electrode coupled to a reference voltage, and a second electrode.

Abstract: A buffer utilizing the pseudo-ground hysteresis of the present invention contains first and second stage switching elements and a resistive element. The pseudo-ground hysteresis is implemented via a ground path from the switching elements. The first stage switching element is configured to have a first DC voltage trip point, and the second stage switching element is configured to have a second DC voltage trip point. As an input voltage, transitioning from a first state to a second state, is applied to the first stage switching element, a first current (I.sub.1), from the first stage switching element, and a second current (I.sub.2), from the second stage switching element, is generated. When the input voltage equals the first stage DC voltage trip point, the first and second stage switching elements transition. During the transition of the input voltage from the second state to the first state, the total current flowing through resistive element is reduced, and the voltage at the resistive element decreases.