Abstract: A controllable width OR gate employs a plurality of controllable OR gate cells. If the maximum width of the data to be ORed is N bits, then N-1 such controllable OR gate cells are needed. Each controllable OR gate cell 100 has four data inputs, OR0, ST0, OR1 and ST1, and a single control input CO. Each controllable OR gate cell has two outputs: ORout and STout. A first OR gate forms the OR of the OR0 and OR1 inputs unconditionally as the ORout output. A second OR gate forms the OR of the OR0 input and the ST1 input. Two pass gates are controlled in the opposite sense via the signal on control input C0 due to an invertor. If C0 is "1", then the output the second OR gate (OR0 OR ST1) is supplied to output STout. If C0 is "0", the ST0 input is supplied to output STout. Layers of the controllable OR gate cell can be used to from a wide controllable width OR gate. Each layer of cells is controlled by a corresponding bit of the control word.

Abstract: A null consumption CMOS switch which may be set by nonvolatile programming is formed by a pair of complementary transistors preferably having a common drain and a common gate. The common gate is coupled to the floating gate a programmable and erasable, nonvolatile memory cell. The common gate/floating gate coupling can be a unitary floating gate structure. The floating gate directly drives the ON or OFF states of the two complementary transistors. On an output node of the switch, represented by the common drain of the pair of transistors, a signal present on a source node of one or the other of the two complementary transistors is replicated. The state of charge of the floating gate, imposed by programming or erasing, may be such as to reach advantageously a potential higher than the supply voltage or lower than the ground potential of the circuit. Different embodiments, such as a polarity selection, a path selector, a TRISTATE selector, and a logic gate selector are described.

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources.

Abstract: A method and device for performing logic functions. A logic array (1) is controlled by a plurality of DRAM cells (101). The DRAM cells are, in preferred embodiments, loaded in a serial fashion with a shift register (1205). Refresh according to one aspect of the invention utilizes a shift register (1201) with a circulating "0." A charge pump circuit, voltage boost circuit, and a variety of memory cell/logic array configurations are also disclosed.