Abstract: Buffers for driving interconnection conductors on programmable logic devices are shared between two types of uses, i.e., to drive static programmable connections to interconnection conductors, and to drive dynamically controllable connections to other interconnection conductors. The dynamically controllable connections are preferably tri-statable. Signals for effectuating the dynamic control are preferably generated on the programmable logic device near the tri-state-type connections. For example, a nearby logic module ("subregion") may provide the dynamic control signal. This reduces the extent of routing for, and consequent delay of, the dynamic control signal.

Abstract: A CMOS buffer circuit having a trip point which is insensitive to variations in temperature, supply voltages and manufacturing processes. The circuit output stage has three series-connected MOS transistors including an N channel pull-down transistor connected between the buffer output and the circuit common, a first P channel pull-up transistor connected to a positive supply voltage and a second P channel pull-up transistor connected between the first P channel transistor and the buffer output. The gates of the first P channel transistor and the N channel transistor are connected together to form the buffer input. An N channel reference transistor is used to generate a reference current which is mirrored into the output stage by a third P channel transistor which is connected to the second P channel transistor of the output stage so as to form a current mirror.

Abstract: An input/output driver circuit which provides a buffer interface between a functional digital circuit and a common bus for other digital circuits achieves high levels of voltage tolerance and compliance, while requiring only two power supply pins, by using two PMOS switching transistors between the circuit's output line and an output power supply terminal, rather than only one. To turn the transistors OFF, the output power supply voltage is applied to the gate of one of them and the output line voltage to the gate of the other. This assures that at least one of the transistors is fully OFF when desired, whether or not the output line voltage exceeds the output power supply level.

Abstract: An integrated circuit device capable of effectively shutting off the power supply in a powerdown mode. The integrated circuit device is connected to a first (ground) power supply, a second power supply that continuously provides power, and a third power supply that halts power supply during the powerdown mode. It includes a controller and a CMOS tri-state driver consisting of a series connection of a P-channel MOS transistor and an N-channel MOS transistor. The P-channel MOS transistor has its source connected to the third power supply, its backgates connected to the second power supply and its gate connected to the controller. The N-channel MOS transistor has its source and backgate connected to the first power supply, its drain connected to the drain of the P-channel MOS transistor and its gate connected to the controller.

Abstract: An input/output circuit in which, one of the two output signals from a signal level converting circuit is inputted into one input terminal of a NAND gate and into one input terminal of a NOR gate, while the other signal is inputted into the other input terminal of the NOR gate and also to the other input terminal of the NAND gate through an inverter. An output signal from the NAND gate and NOR gate is inputted into the gate of a PMOS transistor and into a gate of a NMOS transistor, which makes it possible to prevent the PMOS transistor and NMOS transistor from concurrently being ON and also prevents a through current from flowing therethrough.

Abstract: In accordance with the present invention there is provided a tristatable digital MOS output buffer/driver having a significantly reduced subthreshold leakage current. The buffer of the present invention comprises three P-channel transistor devices and three N-channel transistor devices. A reduced subthreshold leakage current is achieved by having the source of the output N-channel transistor device and the output P-channel transistor device connected to nodes having a variable voltage. This adjusts the source-to-body voltages of the output N-channel and P-channel transistor devices to be equal in magnitude to the voltage of the positive supply, resulting in the reduction of subthreshold leakage currents.

Abstract: A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be "disabled" by an inactive enable signal so they output a constant "0" level for the differential output clock. This disabling feature of the differential clock receiver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

Abstract: An active termination circuit for terminating a transmission line in memory bus, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor.

Abstract: Switching circuit comprising a reference voltage, an input voltage, suitable to assume alternatively a negative value or a value equal to said reference voltage, an output node, suitable to assume selectively three possible voltage values equal to a supply voltage, to the reference voltage, to the input voltage or, alternatively, to be kept floating, in response to a first, a second, a third, a fourth, a fifth, a sixth control logic signal, switching between the supply voltage and the reference voltage.

Abstract: An output buffer circuit is provided which comprises a level conversion circuit having a first conversion circuit for converting a control signal and an output signal to "H" and "L" signals in a first source system and a second conversion circuit for converting these into "H" and "L" signals in a second source system, a tristate control type input/output control circuit for computing the "H" and "L" signals outputted from the second conversion circuit in the second source system, and a push-pull circuit having MOS transistors Q13a and Q14, which is activated in the second source system in response to the "H" and "L" signals so as to select a tristate and output it as an input/output signal.

Abstract: In a case where a plurality of outputs are connected and used, even when a voltage higher than the power-supply voltages inside the integrated circuit is applied to the signal output terminal, the reliability of the internal elements is prevented from deteriorating. The semiconductor integrated circuit includes a PMOS transistor that has its source potentially isolated from its back gate and has one end of the current path between its source and drain connected via a transistor switch to the signal output terminal.

Abstract: Data enabled complex logic gates provide improved speed/power performance over conventional topologies such as static logic or clocked domino logic. Within a data enabled complex logic gate, complementary parallel logic structures, such as NFET logic trees, are configured such that for any combination of input variables one logic structure will produce a logic low as an output and the other logic structure will produce a logic high as an output. The logic structures are cross-coupled to each other by way of internal precharge devices, and are further individually coupled to an output latch. In this way the logic structures can be precharged to prepare for evaluation of the next set of input signals while the output latch maintains the result of the previous evaluation. In a further aspect of the invention, data enabled complex logic gates are combined with pass gate latches and multiplexer based logic gates to produce a high-speed, low-power logic pipeline.

Abstract: An output circuit which suppresses the occurrence of leakage current from the power supply of an external element to the power supply of an internal device, even if the power supply voltage of the external element is higher than the power supply voltage of the internal device. Even if a voltage (5V) from an external circuit etc. which is higher than a power supply terminal 6 voltage (3V) is input to the output terminal 8, due to the fact that a floating state N-well B1 at the substrate of PMOS transistors P12, P13 and P14 rises to around 5V, PMOS transistor P12 and PMOS transistor P13 are put into an OFF state. If PMOS transistor P12 and PMOS transistor P13 are in the OFF state, the (5V) voltage is applied to PMOS transistor P1 and there is no flow of leakage current to the power supply terminal 6 through the substrate of PMOS transistor P1.

Abstract: The drains of P- and N-channel MOS transistors 1 and 2 are connected to each other. An output terminal is formed at the node of the drains. Each of first and second amplifier stages 4 and 5 is configured by cascading an n number of CMOS inverters. The amplifier stages drive first and second last-stage CMOS inverters 6 and 7 to drive the P- and N-channel MOS transistors 1 and 2, respectively. A dummy CMOS inverter 8 is disposed so that the input is connected to the node of the second amplifier stage 5 and the second last-stage CMOS inverter 7. The load of the second amplifier stage 5 is equal to that of the first amplifier stage 4. The drivabilities of the CMOS inverters of the same stage in the first and second amplifier stages 4 and 5 are made equal to each other. According to this configuration, the number of CMOS inverters which must be checked in a process of adjusting the duty can be reduced.

Abstract: A buffer for enabling a signal to be applied to a bus. The buffer includes a first transistor coupled to a bus and a voltage supply. The logic buffer includes a first logic circuit which has an input coupled to receive a data signal and adapted to charge a terminal of the transistor at a first rate in response to a transition in the data signal. A second logic circuit charges the terminal at a faster rate during an initial transition period, until a first preselected condition is met. The buffer also includes a third logic circuit to charge the terminal at a second faster rate during a final transition period, after a second preselected condition is met. A method for controlling a voltage level of a signal applied to a terminal of a transistor includes charging the terminal at a fast rate until a first preselected condition is met.

Abstract: An output pad circuit is provided that adjusts a driving output current size within the chip based on a control signal. Thus, the output pad circuit adjusts a driving output current size, without attaching an external buffer or exchanging the output pad circuit, when an external load size varies during a chip design. The output pad circuit includes a tri-state inverter having an output being a tri-state level when a control signal is low level, but operating as an inverter when the control signal is high level.

Abstract: The present invention provides an apparatus for providing two different modes of operation for an output driver on an integrated circuit. A first mode provides an open drain driver, such as an enhanced GTL+ driver, for high-speed data transmission. A second mode provides a totem pole output driver, such as a TTL or a LVTLL driver, which does not require additional circuitry for external terminations, as is required for open drain drivers. Thus, one embodiment of the present invention can be characterized as an integrated circuit with an output buffer having a first mode that provides a driver for an open drain bus, and a second mode that provides a totem pole output. This output buffer receives a signal to be outputted from the integrated circuit and a mode select signal that selects between the first mode and the second mode.

Abstract: A bus switch uses both n-channel and p-channel transistors in parallel to connect two busses. The bus switch can be used on a network card to be plugged into a running network. During hot or live insertion of the network card into a live or hot bus, the network card and a bus switch are in a powered down state. Although n-channel transistors are normally off when the power is off, p-channel transistors can conduct. The hot bus could be disturbed when the bus switch is first connected since the p-channel transistor conducts when its gate is powered down to zero volts. A p-n junction from the p-channel transistor's drain to its substrate can become forward biased, drawing current from the hot bus. These problems are avoided by an isolation circuit that operates without power from a power supply. Instead, a high voltage from the hot bus is routed to the gate of the p-channel transistor, keeping the p-channel transistor turned off during hot insertion.

Abstract: A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages between two power rails and voltage division techniques to limit the voltages to acceptable limits for drain-to-source, gate-to-drain, and gate-to-source of CMOS devices in any chosen technology. The circuit comprises first and second CMOS cascode chains connected between a high voltage power rail, e.g 5 volt and a reference potential power rail, e.g. ground. Each CMOS cascode chain comprises first and second p-type MOS devices in series with first and second n-type MOS devices. An input circuit is coupled to a node at the midpoint of the first CMOS cascode chain. A bias voltage, typically 3.3 volts is connected to the NMOS devices in the first and CMOS cascode chains.

Abstract: An integrated circuit having a DC current test function operates at a core supply voltage and interfaces at an input-output (I/O) supply voltage. The I/O supply voltage is greater than the core supply voltage. The integrated circuit includes a buffer, a voltage level shifting circuit and a pull-up circuit. The buffer is coupled between a core terminal and a pad terminal. The pad terminal has a voltage swing which is substantially equal to the I/O supply voltage. The voltage level shifting circuit has a test signal input with a voltage swing substantially equal to the core supply voltage and a test signal output with a voltage swing from the I/O supply voltage to a selected bias voltage. The pull-up circuit is coupled to the pad terminal and has a control terminal coupled to the test signal output.

Abstract: An output buffer includes a differential data circuit for generating a first and a second differential signal, a pulse circuit for generating a pulse signal, a first latch circuit set by the first differential signal and reset by either the pulse signal or the second differential signal and a second latch circuit set by the second differential signal and reset by either the pulse signal or the first differential signal. An output circuit generates an output signal, the output signal being tri-stated whenever the pulse signal resets the first and second latch circuits. A method for improving output tri-state time of an output buffer includes the steps of pre-charging first and the second differential data inputs; tri-stating the buffer output upon each assertion of a timing signal; switching the output out of tri-state and into either a first or a second logic state only when one of the first and second differential data inputs changes to an active state; and returning to the pre-charging step.

Abstract: A programmable input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal, the I/O circuit including a pull-up transistor, a gate bias control circuit and a well bias control circuit, all being connected between Vcc and the I/O terminal. The gate bias control circuit connects the gate of the pull-up transistor to the I/O terminal and the well bias control circuit connects the bulk terminal of the pull-up transistor to the I/O terminal when the I/O circuit is in a 5V tolerant input mode. The gate bias control circuit connects the gate of the pull-up transistor to the system voltage source and the well bias control circuit connects the bulk terminal of the pull-up transistor to Vcc when the I/O circuit is in a PCI compliant input mode. In an output mode, the gate bias control circuit and well bias control circuit allow the pull-up transistor to pull up the I/O terminal to Vcc in response to a pull-up data signal.

Abstract: An output drive circuit enables both 5V and 3V devices to be connected to the same bus, without exposing the 3V devices to damage from the 5V signals on the bus. The 3V devices utilize 3V output drives that are tolerant of the 5V signals on the bus. The tolerance is achieved by a circuit design which adjusts internal voltages depending upon the external voltage on the bus. The internal voltage adjustments prevent transistor voltage limits from being exceeded and hence prevent damage from occurring.

Abstract: A monolithic integrated multiple mode circuit having an output stage, a transfer gate, a control circuit arrangement, and a well contacting region where a well potential may be applied, the multiple mode circuit adapted to be controlled into an output stage mode or an input stage mode by means of control data.

Abstract: A tri-state input-output (I/O) buffer which includes a core terminal, a pad terminal and an enable terminal. A pad pull-down transistor and pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. A pull-down control circuit is coupled between the core terminal and the pull-down control terminal. A pull-up control circuit is coupled between the core terminal and the pull-up control terminal. A feedback circuit is coupled between the pad terminal and the pull-up control terminal for sensing a first voltage on the pad terminal and adjusting a second voltage on the pull-up control terminal based on the sensed first voltage to reduce leakage current through the pull-up transistor when an enable signal received on the enable terminal is an inactive state.

Abstract: A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors that are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.

Abstract: The invention provides for an input/output circuit in a CMOS integrated circuit which can withstand pad voltages which are higher than the supply voltages for the integrated circuit. The input/output circuit has a pair of first polarity-type transistors which is connected in series between a first supply voltage terminal and the input/output pad, and a pair of second polarity-type transistors which is connected in series between a second supply voltage terminal and the pad. Responsive to a disable control signal, one of the first polarity-type and one of the second polarity-type transistors are turned off. Switch circuitry is connected between the pad and a gate of a second transistor of the second polarity-type transistor pair.

Abstract: A tri-state I/O buffer and a method of inhibiting current to an I/O buffer arranged to be powered by a supply voltage and to drive an output terminal are provided. The I/O buffer preferably has an output driving circuit connected to the supply voltage for driving the output terminal and includes a first plurality of transistors defining an isolated floating well circuit for operatively connecting the output terminal to the supply voltage and a second plurality of transistors defining a pull-down circuit for operatively connecting the output terminal to ground. An input control circuit is connected to the output driving circuit and the supply voltage, and is arranged to receive a buffer input signal for controlling the buffer input signal to the output driving circuit.

Abstract: A pre-driver circuit in an I/O circuit for an integrated circuit performs the combined functions of voltage level shifting, slew rate control, and tri-state capability, in a single circuit to avoid additional delay caused by implementing any combination of these functions in two or more circuits.

Abstract: An output circuit for an integrated circuit device in which first and second power wirings are connected to a high-potential power terminal, third and fourth power wirings are connected to a low-potential power terminal, and a plurality of inverters are responsive, respectively, to a plurality of bit data signals, each being formed of P-channel and N-channel MOS transistors having drains thereof connected together, a junction of which forms an output terminal. First to fourth auxiliary transistors are provided for each of the inverters, which are connected, respectively, between the first power wiring and the source of the P-channel MOS transistor, between the second power wiring and the source of the P-channel MOS transistor, between the third power wiring and the source of the N-channel MOS transistor, and between the fourth power wiring and the source of the N-channel MOS transistor.

Abstract: An output buffer with improved tolerance to overvoltage conditions. Among other features, especially when in a high-impedance state, the output buffer prevents a leakage path from a pad (108) through a pull-up driver (101) to supply voltage VDD when any voltage above VDD is placed on the pad (108). Further, the output buffer provides improved transient response characteristics. In one embodiment, the output buffer includes a pull-up driver (101), a first tracking transistor (120), a second tracking transistor (122), a voltage bias generator (112), and a coupling capacitor (124).

Abstract: The output buffer circuit according to the present invention is connected to an I/O pad of the integrated circuit. The output buffer circuit includes an output totem pole, a level shifter and enable logic. The output totem pole has a first input connected to the level shifter and a second input connected to the enable logic. The output of the totem pole is connected to an I/O pad. The totem pole includes a pullup transistor connected to 3.3 volt Vcc and a pulldown transistor connected to ground. In a first embodiment of the invention, the pullup transistor in the totem pole is an N-channel MOS transistor, and in a second embodiment of the invention, the pullup transistor in the totem pole is a P-channel MOS transistor formed in an N-well tied to the 5 volt Vcc. In the first embodiment of the present invention, the N-Channel MOS pullup transistor is turned on by a 5 volt signal from the level shifter.

Abstract: A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.

Abstract: An integrated circuit is implemented in a low-voltage technology and has an output driver. The output driver has circuitry adapted to generate an output voltage at an output node (e.g., PAD in FIG. 1) based on an input voltage (e.g., A). Within the output driver, a transistor is configured to limit the drain-to-source voltage drop across another transistor to enable the integrated circuit to tolerate, at its output node, voltages of magnitude up to two times the operating voltage of the integrated circuit. The invention enables low-voltage integrated circuits to be interfaced with other circuitry implemented in a relatively high-voltage technology, without suffering the adverse effects that can otherwise result in the low-voltage circuitry from such interfacing.

Abstract: A circuit for selectively generating one of three voltage level as an output has a pull-up transistor and a pull-down transistor. The circuit includes a bias voltage source for generating a constant voltage signal; a temperature compensating constant-current source for outputting variable voltage signal corresponding to a temperature change; a tri-state control circuit for receiving a data signal to generate a control signal based on the data signal; and a switching circuit, in response to the control signal, for selectively the bias voltage source and the temperature compensating constant current source to the pull-up and pull-down transistors.

Abstract: Ferroelectric transistors are combined with MOSFETs to perform logic functions. The logic functions include a non-volatile ferroelectric latch (30), a clocked non-volatile ferroelectric latch (50), a programmable switch (60), an edge-triggered complementary flip-flop (78), a tri-state logic circuit (80), a ferroelectric logic NAND-gate (100), a clocked ferroelectric logic NAND-gate (140), and a programmable logic function (150). The programmable logic function (150) includes a programming terminal (156) to select between a NOR-gate function and a NAND-gate function.

Abstract: A CMOS output buffer circuit includes a predriving circuit which generates two predriving signals, a main driving circuit which has a plurality of parallel connected pull-up transistors and a plurality of parallel connected pull-down transistors, and a sequential driving circuit which provides sequential pull-up and pull-down driving signals to the pull-up and pull-down transistors, respectively. The main driving circuit generates the output signal according to the sequential pull-up or pull-down driving signals, whereby the output signal is developed step by step into either the power supply potential or the ground potential. In the manner, any spike in the switching current is considerably mitigated, thereby reducing switching noise.

Abstract: In a mixed voltage input buffer for managing mixed voltages in a semiconductor device which uses various voltages, includes a transmission unit for inputting a given signal and transmitting the input signal according to an enable signal, and a voltage level conversion unit for inputting an output signal of the transmission unit and converting its voltage level into a voltage level of an inner core power and then outputting it.

Abstract: An I/O buffer with minimized footprint; which is less susceptible to voltage spikes caused by switching noise, and which is adapted for used in a separate power bus arrangement. The buffer minimizes voltage spikes caused by switching noise by replacing the single large current surge that occurs during switching with smaller current surges at different times. This is accomplish by having two different drivers for the transitional and holding phases: a Transient Switching Circuit (TSC) and a Logic Holding Circuit (LHC). Generally, the TSC is operational to cause a change in the output signal when there is a change in the input signal. Conversely, the LHC is operational subsequent to the logic transition occurrence at the input signal to bring the output signal to the rail voltage.

Abstract: A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

Abstract: A method and apparatus for providing a high speed tristate buffer. The buffer includes a p-channel pull-up transistor and a transfer gate. The source of the transistor is coupled to a voltage supply. The drain of the transistor is coupled to the buffer output. The gate of the transfer gate is coupled to a first clock source. The input to the transfer gate is a second clock source, and the output of the transfer gate is coupled to the gate of the p-channel transistor.

Abstract: A CMOS buffer circuit having a trip point which is insensitive to variations in temperature, supply voltages and manufacturing processes. The circuit output stage has three series-connected MOS transistors including an N channel pull-down transistor connected between the buffer output and the circuit common, a first P channel pull-up transistor connected to a positive supply voltage and a second P channel pull-up transistor connected between the first P channel transistor and the buffer output. The gates of the first P channel transistor and the N channel transistor are connected together to form the buffer input. An N channel reference transistor is used to generate a reference current which is mirrored into the output stage by a third P channel transistor which is connected to the second P channel transistor of the output stage so as to form a current mirror.

Abstract: Problems associated with excessive crowbar current due to input signal transitions at a buffered programmable interconnect point are solved by inserting a transistor switch between power and ground. The inserted switch is in series with the input buffer and is controlled by a memory cell which also controls the pass/no-pass state of the interconnect. An OFF inserted switch blocks current that flows during switching when the memory cell output causes a no-pass state of the interconnect.

Abstract: An output circuit for a semiconductor device that offers improved reliability of data transfer over long distance as well as low consumption. In one embodiment, an output circuit according to the invention includes: an output circuit section having a pair of output terminals for outputting complementary output signals in response to an input signal received by the output circuit section, and a switch circuit connected between the pair of output terminals of the output circuit section. The output circuit section sets the pair of output terminals in a high-impedance state in response to a high-impedance setting signal received by the output circuit section. The switch circuit causes electric coupling between the pair of output terminals in response to the high-impedance setting signal.

Abstract: There is disclosed an integrated circuit including a programmable driver circuit having first and second transistors. Each of the first and second transistors has first, second and third terminals. The first terminal of each of the first and second transistors are coupled together to form an input node. The second terminal of the first transistor is coupled to a power node. A third terminal of the first transistor is coupled to a first intermediate node. The second terminal of the second transistor is coupled to a second intermediate node. The third terminal of the second transistor is coupled to a reference potential. A first switch having at least one input is coupled between the first and second intermediate nodes. Third and fourth transistors each having first, second and third terminals. The first terminal of the third transistor is coupled to a third intermediate node. The first terminal of the fourth transistor is coupled to the second intermediate node.

Abstract: An input and output buffer circuit which is contained in a first circuit operated on a first power source of a first voltage level Vcc1 and is permitted to connect to a second circuit operated on a second power source of a second voltage level Vcc2 higher than the first voltage level Vcc1 including: a driver PMOS transistor with a CMOS gate; a PAD terminal serving as an input and output terminal; and means for controlling the potential of the N well of the driver PMOS transistor in such a manner that when the potential at the PAD terminal is less than Vcc1-Vth, wherein Vth is a threshold voltage of a MOS transistor contained between the driver PMOS transistor and the PAD terminal, the potential of the N well is set at the first voltage level Vcc1; when the potential at the PAD terminal is more than Vcc1+Vth, the potential of the N well is equated with the potential at the PAD terminal; and when the input and output buffer circuit is in the output mode the potential of the N well is switched to the first volta

Abstract: Either a power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.

Abstract: An output buffer 10 of an integrated circuit controls the slew rate of an output signal in order to minimize electro-magnetic interference. Transient current delay circuits 132 and 134 provide a delay between turning off pull down circuit 122 and turning on pull up circuit 124, and vice versa, in order to assure that driver overlap does not occur. Pull up circuit 124 selectively switches a plurality of output transistors P(n) in order to control the rise time of an output signal. Likewise, pull down circuit 122 selectively switches a plurality of output transistors N(n) in order to control the fall time of an output signal so that current spikes on supply lines to output buffer 10 are reduced or eliminated.

Abstract: A mixed voltage compatible buffer having reduced power consumption is provided. One embodiment of the buffer according to the present invention comprises: a data input configured to receive an output data signal; a data interface configured to couple with a pad interconnect; an output driver coupled with said data interface and being configured to apply the output data signal thereto; and a data controller intermediate said data input and said output driver, said data controller being configured to apply a plurality of control signals of substantially equal voltage to said output driver to control the operation thereof responsive to the output data signal received via said data input. The present invention also provides for a method of transferring data within the buffer.

Abstract: A first output buffer circuit with independent transparent latch and tristate output capabilities includes input translators that directly drive a pair of main pull-up and pull-down output transistors. The input translators are tristatable in response to latch control signals and latching elements on side branches of the signal paths leading from the translator outputs to the output transistor gates hold the last voltage value on those signal paths at the time the translators are disabled. The main current paths through the output transistors include isolation transistors in series with the output transistors and responsive to feedback control from the buffer output. These feedback paths include logic gates responsive to output enable control signals that can shut off isolation transistors and hence put the buffer output in a high impedance state.