Abstract: A tri-state output driver comprised of a pair of complementary field effect transistors (CMOS FETs) having sources and drains connected in a series circuit between a voltage rail and ground, apparatus for applying similar logic high and low input signals to respective gates of the FETs whereby an output terminal connected in a circuit between the sources and drains of the FETs is driven toward ground or the voltage rail respectively, or opposite polarity input signals to the gates for causing the FETs to assume a high impedance, and apparatus for maintaining a voltage across the source and drain of the FET which is connected in a circuit between the voltage rail and the output terminal, at less than a lower of an FET threshold of conduction voltage or diode turn-on voltage greater than the voltage of the voltage rail, during the high impedance state, so as to maintain the latter FET in a high impedance state even when a voltage at the output terminal is equal to a voltage which is higher than an FET threshold

Abstract: A data transmission method exchanges data between at least first and second electronic devices which are coupled via a plurality of bus lines, where each of the bus lines is terminated via a terminating resistor having one end coupled to a bus line and another end applied with a terminating voltage. The data transmission method includes the steps of (a) setting a high logic level of data to a voltage higher than the terminating voltage and setting a low logic level of the data to a voltage lower than the terminating voltage, and (b) continuously outputting the data from the first electronic device to at least one bus line at a timing determined by a first clock signal by alternately repeating a state where the data is output to the one bus line and a state where an impedance between the first electronic device and the one bus line is set to a high impedance.

Abstract: An overvoltage tolerant CMOS tristate output buffer capable of withstanding tristate overvoltages without reverse currents or latch-up, the output buffer having a stabilized protection circuit for driving the N-well and gate of the P-channel driver transistor to the output pad voltage when the output pad voltage becomes excessive. The stabilized protection circuit includes a hysteresis circuit for controlling switch transistors which bias the N-well. The presence of the hysteresis circuit causes the protection circuit to have an input hysteresis characteristic, thus preventing excessive switching of the N-well biasing transistors when the output pad voltage varies near the output buffer power supply voltage during tristate.

Abstract: An output circuit serving as an interface between an LSI and an external LSI, even though the power voltage of the external LSI is not less than the withstand voltage of the gate oxide layer of each of the MOS transistors forming the output circuit, can supply, from the output unit thereof, a signal of which amplitude is equal to the power voltage of the external LSI without a voltage not less than the withstand voltage above-mentioned applied to the gate oxide layer of each of the MOS transistors. A pull-up circuit for pulling up the potential of the output unit comprises first and second PMOSs being connected in series between the power of the external LSI and the output unit, the first PMOS receiving a pull-up control signal at the gate thereof. A pull-down circuit for pulling down the potential of the output unit comprises first and second NMOSs being connected in series between the output unit and the ground, the first NMOS receiving a pull-down control signal S.sub.d at the gate thereof.

Abstract: The present invention is a battery backed output buffer which provides a well-defined signal, even during battery power. The buffer includes a regular output buffer for providing output data during operation with a main power supply and for switching to a tri-state during battery power. The buffer also includes a configurable battery backed output buffer which provides a predetermined output signal during battery operation and produces a signal in the tri-stated during main power operation.

Abstract: An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.

Abstract: A low voltage driver circuit capable of interfacing with a high voltage node. The high voltage tolerant input/output circuit of the present invention has a first stage operating at a low voltage integrated circuit standard and a second stage capable of operating at both the low voltage and a high voltage integrated circuit standard. The second stage operates at high voltage during the tristate mode and at low voltage during an active mode. The second stage uses an output driver having a p-type pull-up transistor coupled to an input/output pad. The input/output pad interfaces with a high voltage or mixed voltage network. An isolator circuit is coupled between the first stage and the second stage for voltage isolation when the second stage is operating at high voltage. A charger circuit maintains the high voltage on a gate of the p-type pull-up transistor during the tristate mode and the low voltage during the active mode.

Abstract: A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the source of the second field effect transistor is coupled to the second input node and the gate thereof is coupled to the first input node. The diode is coupled between the common drain of the first and second field effect transistors and an output node, so as to increase the speed of the operation in the application circuit utilizing the above rectifying transfer gate circuit.

Abstract: A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith.

Abstract: The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase. Next, during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage.

Abstract: There is disclosed an integrated circuit includes an output driver circuit providing control of transition time from one state to another. The output driver includes first and second input transistors coupled to an input node at which data is received. First and second output transistors are coupled to an output node at which the data is presented when the output driver is enabled. The first input transistor is coupled to the first output transistor defining a first node. The second input transistor is coupled to the second output transistor defining a second node. First and second switching circuits are coupled between the first node and the second node. The first switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node.

Abstract: A driver circuit provides for selectively changing the state of an output signal, such as a pre-charged dynamic bus signal. The circuit detects whether or not the data is the opposite state as the pre-charged bus signal, and if so, it drives the bus to the appropriate state. The output from the circuit is self-timed when data can be driven onto the bus as soon as data is valid, i.e., data propagates from the input of the circuit to the bus without depending on a clock or other timing edge.

Abstract: A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors which are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.

Abstract: Tri-state devices having exclusive gate output control include a tri-state device having first and second inputs and a tri-state output, a normally-off transistor connected in series between the tri-state output and a first reference potential (e.g., VCC or VSS) and an exclusive gate (e.g., NOR, OR) having first and second inputs coupled to the first and second inputs of said tri-state device, respectively, and an output electrically coupled to a control electrode of said normally-off transistor so that the tri-state output becomes electrically connected through the normally-off transistor to the first reference potential whenever the first and second inputs of said tri-state device are at different logic potentials. However, the normally-off transistor is maintained in a nonconductive state to reduce power consumption whenever the output of the tri-state device is switched to VCC or VSS.

Abstract: An output buffer includes a pair of P-channel transistors and two cascode pull-down N-channel transistors to drive an output node. The output pull-up transistor has the gate thereof connected through a P-channel control transistor to an input driving signal. The control signal is isolated from the output node by a P-channel transistor which only conducts during overvoltage conditions. During normal operation, the control transistor is maintained in a conductive state to allow the gate of the output pull-up transistor to be pulled high and low. During an overvoltage condition, the P-channel transistor connected between the output node and the control transistor is turned on in order to effectively turn off the control transistor. The P-channel transistors in the output buffer are floating well-type transistors with the wells thereof tied to a switched voltage that is either the supply voltage during the normal operating mode or the output node during overvoltage conditions.

Abstract: A level convertor is provided between circuits, which act with different power supply voltages, respectively, and converts a first voltage level of an output of a circuit to a second voltage level, which corresponds to an operational voltage level of another circuit. The level convertor comprises a level shift circuit, which receives the first voltage level and outputs an output of the second voltage level, and a buffer circuit, which receives the output of the second level and a control signal, and fixes the output of the second voltage level to a low logic level, when the control signal is a low logic level. The control signal may be used to set a timing for registering the data to a register, avoiding data in an instable state when power is supplied, from being registered to the register.

Abstract: An output buffer is disclosed for an integrated circuit having a varying number of simultaneously switching outputs. As fewer outputs on the integrated circuit are simultaneously switching, the output conductance of certain logic gates within each of the output buffers on the integrated circuit is increased by sharing intermediate nodes between each of the output buffers. Consequently, the speed of the output buffer increases as fewer of the outputs simultaneously switch and internally generated noise is small. Conversely, as additional outputs simultaneously switch, the output conductance of certain logic gates within the output buffer is decreased, resulting in reduced speed of the output buffers and a corresponding reduction in internally generated noise.

Abstract: A CMOS differential twisted-pair driver which utilizes CMOS switches and current sources advantageously. No alternative power supply is required, the switches do not have to be low impedance and the device is low power. The preferred embodiment driver further limits signal overshoot and common mode energy. The signal transmission facility is bi-directional so an off state is provided. It is doubly terminated to provide for symmetry, improved bandwidth and reduces reflective signal noise. The double termination also provides for faster rise and fall times which reduces the systems sensitivity to receiver offset.

Abstract: A driver circuit is provided which unconditionally discharges a bus conductor during clock cycles in which the driver circuit is transmitting a value. The unconditional discharge occurs during a first drive phase of the logic drive state. During a second drive phase, the driver circuit either charges or continues to discharge the conductor based on the data value being transmitted. Since the conductors are transitioning in the same direction at approximately the same rate, line to line coupling is virtually non-existent during the first drive phase. By partially discharging bus conductors during the first drive phase, transition speed is increased to the point at which a receiving circuit senses the transmitted value. Effectively, the line-to-line coupling which would have occurred during the first drive phase is endured during the second drive phase, when certain conductors may be recharged.

Abstract: A low capacitance bus driver circuit includes, in this example, P-channel and N-channel output transistors with input gates connected by means of CMOS pass gates to a common input terminal and having respective P-channel and N-channel transistors connected to the input gates of the output transistors so as to place them in a high impedance state when the CMOS pass gates are disabled. Input capacitance of the bus driver circuit is greatly reduced by elimination of CMOS gate capacitance when the bus driver is enabled. When the bus driver is not enabled, it provides optimal performance of a single gate delay from input to output without the need for series connected output devices or correspondingly higher input capacitance.

Abstract: A CMOS buffer circuit having a trip point which is insensitive to variations in temperature, supply voltages and manufacturing processes. The circuit output stage has three series-connected MOS transistors including an N channel pull-down transistor connected between the buffer output and the circuit common, a first P channel pull-up transistor connected to a positive supply voltage and a second P channel pull-up transistor connected between the first P channel transistor and the buffer output. The gates of the first P channel transistor and the N channel transistor are connected together to form the buffer input. An N channel reference transistor is used to generate a reference current which is mirrored into the output stage by a third P channel transistor which is connected to the second P channel transistor of the output stage so as to form a current mirror.

Abstract: A voltage output clamp circuit includes a reference voltage generator, a switched differential operational amplifier, and an output driver circuit. The reference voltage generator has a first input coupled to a first reference voltage and a second input coupled to a second reference voltage. An output of the reference voltage generator is coupled to a first input of the switched differential operational amplifier. The output of the operational amplifier is coupled to an input of the output driver circuit and an output of the output driver circuit is coupled to a second input of the operational amplifier, providing a feedback path. The voltage output clamp circuit may further include a first NAND gate receiving a first logical signal and an output enable signal and providing an output. The output of the first NAND gate may be coupled to an input of a first transistor which is arranged to provide an electrical path between the first reference voltage and the operational amplifier.

Abstract: An interface circuit includes at least one signal processing circuit connected to a transmission line which is equipped with a terminal circuit having a resistor with a terminal voltage applied to at least one terminal, and includes an input circuit for inputting from the transmission line a signal to be processed in the signal processing circuit, or an output circuit for outputting a processed signal to the transmission line or an input and output circuit for inputting and outputting a signal. The input circuit or the output circuit or the input and output circuit are incorporated in the signal processing circuit. The input circuit or the output circuit or the input and output circuit are directly connected to the transmission line, wherein the output circuit has a push-pull circuit which is directly connected to the transmission line to receive an output signal from the signal processing circuit and to have a constant output impedance which is independent of an output from the output signal.

Abstract: An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the Gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.

Abstract: An output buffer circuit with low power pre-output driving capability uses existing output drivers and includes input inverters with three-state outputs interposed between the input and output stages and a feedback circuit with three-state outputs connected to the output stage. During normal data transmission, the input inverters buffer the incoming complementary data signals driving the pull-up and pull-down transistors in the output stage while the three-state outputs of the feedback circuit are turned off. Upon receiving an active pre-output control signal, the input inverters are disabled, thereby isolating the pull-up and pull-down transistors from the incoming complementary data signals, and the feedback circuit is enabled. The enabled feedback circuit monitors the signal level of the output signal from the output stage.

Abstract: A tri-state synchronous bus driver avoids contention between succeeding cycles by shutting off each device's output enable early, so that it is guaranteed to no longer drive the line by the time any other device begins to drive. Enable activation occurs on a leading edge of the bus clock, and deactivation occurs at a delayed half phase clock edge. A low current bus holding cell is coupled to each bi-directional line to maintain the driven signal value until it can be sampled by a receiving device. This has the advantages that set up time is not eroded by the technique, and that the disable timing is relatively non-critical. The technique is particularly useful in gate array technology as process, temperature, and voltage variation can cause considerable fluctuation in the actual timing of circuits.

Abstract: This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

Abstract: An output buffer (30) is connected to an output signal line and receives an internal power supply voltage, for example 3.3 volts, which is lower than a voltage, for example 5 volts, that other devices which may be connected to the output signal line are able to drive. To protect an output transistor (71) from the harmful effects of the higher voltages on the output signal line, the output buffer (30) includes a special bulk biasing circuit (80). The bulk biasing circuit (80) biases the bulk of the output transistor (71) at an internal power supply voltage when the output buffer is driving and when not driving to a voltage determined by the output signal. To prevent overlap currents, the output buffer (30) includes a special gate biasing circuit (100), which momentarily drives the gate of the output transistor (71) to a voltage equal to the internal power supply voltage when the output buffer (30) stops driving.

Abstract: A data output buffer circuit for a semiconductor device for transferring read cell data to the peripheral circuits, comprising an input terminal for inputting the read cell data, a first NMOS transistor for transferring the data from the input terminal when it has a first logic level, a first PMOS transistor for transferring the data from the input terminal when it has a second logic level, a second PMOS transistor for transferring a high logic signal in response to an output signal from the first NMOS transistor, a second NMOS transistor for transferring a low logic signal in response to an output signal from the first PMOS transistor, and an output terminal for outputting the high logic signal from the second PMOS transistor or the low logic signal from the second NMOS transistor to the peripheral circuits.

Abstract: An output buffer circuit operating normally when its supply potential is exceeded by the potential of the bus to which the buffer circuit output is connected. The circuit comprises a p-channel MOS transistor and a first and a second n-channel MOS transistor. The output node of the output buffer circuit is connected not to the p-channel MOS transistor but to the connection point between the source of the first n-channel MOS transistor and the drain of the second n-channel MOS transistor. The threshold potential of the first n-channel MOS transistor is set so that, with the output node in the high-impedance state, the first n-channel MOS transistor is turned off when the output node potential exceeds the supply potential of the output buffer circuit. This prevents the p-channel MOS transistor from getting activated or from being forward-biased between the back gate and the drain or source. Thus no leak current flows when the bus potential becomes higher than the supply potential of the output buffer circuit.

Abstract: A built-in intermediate voltage sensor for CMOS circuits comprises a linear inverter, a first voltage control switch, a second voltage control switch, and a buffer. The linear inverter has an input end connected with an input signal under test. The first voltage control switch has a control end and an input end which are connected respectively with the input end and an output end of the linear inverter. The second voltage control switch has a control end and an input end which are connected respectively with the output end and the input end of the linear inverter. The buffer has an input end connected with the output end of the first voltage control switch and the output end of the second voltage control switch. The buffer gives forth an output voltage having a first logic value when the input signal has a voltage value of logic "0" or logic "1".

Abstract: An output driver circuit for a semiconductor chip has a push-pull output with a P-channel pull-up and an N-channel pull-down. Predrivers produce push-pull outputs for driving the gates of the output driver. Compensator circuits, one for the N-channel pull-down, and one for the P-channel pull-up, are used to prevent the transition from high-to-low or low-to-high from being too rapid, which could cause noise due to inductance of the package leads. A feedback circuit halts the operation of the compensator circuits after a short interval. An overvoltage circuit formed in a well of the semiconductor chip holding the driver circuit, having an input coupled to receive the data output of the predriver circuit going to the P-channel pull-up, also functions to prevent damage to the output driver circuit due to overvoltage on the output node.

Abstract: In a driving circuit for generating driving signals for controlling and switching on and off a first output element employed in an output circuit for generating a high-level output signal and a second output element employed in the output circuit for generating a low-level output signal in a mutually complementary manner, the conductance of the driving circuit is controlled so that it increases gradually with the lapse of time. By sequentially controlling the conductance of the driving circuit for generating the driving signals, the rates of change of the driving signals can be controlled in a smooth and stable manner and output currents can thus be changed smoothly to result in high-speed operation of an output signal with a reduced amount of noise.

Abstract: A data output buffer rapidly transits an output data signal to improve the data reading speed of a semiconductor memory device. To do this, the data output buffer comprises a first input terminal for receiving true data, a second input terminal for receiving complementary data, a pull-up MOS transistor connected between a first power supply and an output line and being driven by the true data from the first input terminal, a pull-down MOS transistor connected between a second power supply and the output line and being driven by the complementary data from the second input terminal, a reference logic voltage generator for supplying a reference logic voltage to the output line, and a controller for driving the reference logic voltage generator, by the true data from the first input terminal and the complementary data from the second input terminal to be complementary to the pull-up MOS transistor and the pull-down MOS transistor.

Abstract: A DRAM includes an output terminal, a memory cell array having a plurality of memory cells, a row decoder, a column decoder, an input/output circuit, a data extending circuit, an output buffer circuit, and a control circuit. The data extending circuit extends each data read out from the input/output circuit until a subsequent data is read out. The output buffer circuit responds to the extended data from the data extending circuit for providing output data sequentially to the output terminal. In response to an output control signal provided from the control circuit, the output terminal is set to a high impedance state before each output data is provided from the output buffer circuit.

Abstract: A semiconductor integrated circuit with a buffer circuit is disclosed. The source of the first P(N)MOS transistor is connected to a voltage supply (ground), its drain being connected to an output terminal. The source of the first N(P)MOS transistor is connected to the ground (voltage supply), its drain being connected to the output terminal. The gate of the second P(N)MOS transistor is connected to the gate of the first NMOS transistor, its source being connected to the voltage supply (ground) and its drain being connected to the output terminal. The gate of the second N(P)MOS transistor is connected to the gate of the first PMOS transistor, at least one of its source and drain being floated. A controller responses to an enable signal and an input signal to apply control signals to the gates of the first PMOS and NMOS transistors. By these control signals, any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is on.

Abstract: An input/output buffer including a bidirectional node, an output stage, an input stage, and a control circuit. The output stage has a first n-channel transistor coupled between the bidirectional node and a voltage supply node for pulling-up the bidirectional node, and first and second p-channel transistors coupled between the bidirectional node and the voltage supply node for pulling-up the bidirectional node. The input stage has a first inverter stage coupled between the bidirectional node and a first intermediate node and a second inverter stage coupled between the bidirectional node and a second intermediate node. The input stage also has a second n-channel transistor coupled between the first intermediate node and a ground node and a third n-channel transistor coupled between the second intermediate node and the ground node. The control circuit is coupled to the output stage and to the input stage and enables the output stage when in an output mode and disables the output stage when in an input mode.

Abstract: The generation of a controlled voltage signal as a buffer control signal for an output driver provides for relatively less delay for a high output enable access for an output buffer. As the output buffer undergoes the transition from a deselected state to a selected state to generate an output signal corresponding to a high input signal, a first voltage level is generated at a node and output as the control signal for the output driver, providing for an initial pull-up transition for the output signal. A second voltage level is subsequently generated at the node and output as the control signal for the output driver, providing for a steady-state voltage level for the high output signal.

Abstract: An output buffer with improved tolerance to overvoltage conditions. Among other features, especially when in a high-impedance state, the output buffer prevents a leakage path from a pad (108) through a pull-up driver (101) to supply voltage VDD when any voltage above VDD is placed on the pad (108). Further, the output buffer provides improved transient response characteristics. In one embodiment, the output buffer includes a pull-up driver (101), a first tracking transistor (120), a second tracking transistor (122), a voltage bias generator (112), and a coupling capacitor (124).

Abstract: A buffer circuit includes a pair of pull-up output transistors and a pair of pull-down output transistors driving an output line. Each output transistor is driven by its own tristate input translator, all connected to an input terminal of the circuit. Two of the translators are tristated by control signals received as feedback from the output line to turn off one of the pull-up transistors when the output exceeds the high logic level transition voltage (2.2 V) and to turn off one of the pull-down transistors when the output drops below the low logic level transition voltage (0.8 V). This not only prevents ground bounce or overshoot of the output, but also avoids larger current flow or power dissipation from pull-up and pull-down transistors being simultaneously partially on during a transition.

Abstract: A tri-state CMOS output buffer is provided which exhibits a relatively low input capacitance and tolerance to a range of operating voltages. The output buffer includes a PUP input, a PD input and an output. The output buffer includes a source follower circuit coupled to the PUP input such that the output of the source follower generally follows transitions in the PUP input signal. The source follower output is the buffer output. A pull-down transistor is coupled between the buffer output and ground to pull-down the output voltage when the PD signal goes high. A pull-up transistor and an isolation transistor are coupled in series to form a series coupled circuit. This series-coupled circuit is coupled in parallel with the source follower. The pull-up transistor pulls up the voltage on the buffer output when the PUP input signal goes high. The isolation transistor is switchable to an off state to isolate a parasitic diode associated with the pull-up transistor.

Abstract: A driver circuit provides for selectively changing the state of an output signal, such as a pre-charged dynamic bus signal. The circuit detects whether or not the data is the opposite state as the pre-charged bus signal, and if so, it drives the bus to the appropriate state. The output from the circuit is self-timed when data can be driven onto the bus as soon as data is valid, i.e., data propagates from the input of the circuit to the bus without depending on a clock or other timing edge.

Abstract: A system of interface circuits (15, 20-1 through 20-N) includes a mode sensing circuit (15) and one or more output circuits (20-1 through 20-N). The mode sensing circuit is arranged for producing control signals (on leads 22, 24) in response to an input signal (on lead 21). The output circuit (34-1) is arranged for producing an output data signal (DQ-1) dependent upon an input data signal (DATA) when the input signal (on lead 21) is in a first state and dependent upon the input data signal and the configuration of the connected output circuit (34-1) when the input signal is in a second state.

Abstract: A self-timed tri-state driver circuit for a dual-rail differential input and single-ended output is disclosed. The circuit generates a tri-state mode in response to an Output Enable (OE) input pulsing low. The OE signal input is driven high to place the driver circuit into a ready state. The circuit is maintained in a tri-state mode until data appears at the inputs. Once a data signal is received after the tri-state circuit is in the ready state, the output immediately outputs this signal. Therefore, the output of the driver is self-timed from the arrival of the data.

Abstract: A single data output terminal and an output portion having a pair of output control terminals for generating a ternary output, are disposed for a plurality of data input terminals and a plurality of control input terminals in the same number as that of the data input terminals. Input changeover portions have (i) a state where data signals can be entered into the output control terminals and (ii) a state where the data signals cannot be entered into the output control terminals. An input control portion supplies, according to the states of control signals entered therein, a changeover signal for switching the input changeover portions to (i) a mode in which one of the input changeover portions is set to the conductive state, or (ii) a mode in which all of the input changeover portions are set to the non-conductive state.

Abstract: A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.

Abstract: An output circuit for a TTL-CMOS integrated circuit that comprises an output stage with two P MOS and N MOS transistors in parallel, which are connected in cascade with an N MOS enabling transistor between the power supply and the reference voltages. The output stage connected by means of a validation signal TRISB and of P and N MOS transistors delivers an output signal representing the input logic variable to the common point between the P MOS transistor and enabling transistor. A first circuit allows switching of the P MOS transistor by an intermediate switching control signal TRISP and a third circuit allows switching of the N MOS transistor, the circuit operating in mode of feedback of the switching control of the P MOS transistor, the controls being applied successively in order to generate an intermediate switching level belonging to the high logic level.

Abstract: An output buffer circuit for a memory device comprising a pull-up path including first and second PMOS transistors for forming two parallel charging paths, and a pull-down path including first and second NMOS transistors for forming two parallel discharging paths. The first and second PMOS transistors are selectively operated according to a level of an output voltage at an output terminal to perform a charging operation for a load capacitance connected to the output terminal. The first and second NMOS transistors are selectively operated according to the level of the output voltage at the output terminal to perform a discharging operation for the load capacitance through a lead inductance.

Abstract: A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3 V voltage to a 5.0 V voltage. The 3.3 V voltage is received on source/drain terminal N1 of an NMOS transistor. The transistor gate is at 3.3 V. The other source/drain terminal N2 of the transistor is connected to an input of a CMOS inverter powered by 5.0 V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0 V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0 V when terminal N1 is at 3.3 V. The same translator is suitable for translating a 5.0 V voltage on terminal N1 to 3.3 V on terminal N2 if the inverter is powered by 3.3 V and the PMOS transistor is connected between 3.3 V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.

Abstract: A current transition rate control circuit is provided, comprising first and second data inputs; first and second charge/discharge circuits for receiving the first and second data inputs; a first reference voltage circuit for sending a first control signal and a second reference voltage circuit for sending a second control signal to, respectively, the first and second charge/discharge circuits; and first and second output transistors coupled, respectively, to the outputs of the first and second charge/discharge circuits. The circuit controls the switching speed of the output transistors to minimize current spikes on the output. The circuit may include a pre-driver circuit for (i) receiving a single data input and outputting the first and second data inputs, and (ii) receiving a circuit disabling signal and placing the circuit in a high impedance state which turns off both of the output transistors.