Abstract: A digital bit-level repeater for joining two wired-AND buses such as the I2C bus is described. A protocol detector is used for tracking clock and data signals to determine the direction of the transfer. A state machine reads and regenerates the clock lines of both buses and provides the clock-stretching protocol feature on both buses. The repeater is designed to pass data bits from one bus to the other transparently when possible, and to latch and hold each data bit until the receiving bus can be clocked when clock-stretching occurs or when the bus is turned around.

Abstract: When a fan drive current has become excessive, a fan drive device intercepts that current, waits for just a fixed time period T1, and thereafter flows that current for a second time. The fan power supply current flowed to the fan drive device is detected by a shunt resistor R. The value of the fan power supply current detected by the shunt resistor R is inputted to a controller, and the cause of any abnormality of the fan is decided upon by this controller, based upon the magnitude of the above described fan power supply current and the time period over which it has continued.

Abstract: A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the nodes, carrying in-phase signals, are tapped to generate a first signal, which is used to generate a second signal driving the NMOS transistor. The other two nodes, carrying in-phase signals, are tapped to generate a third signal, which is used to generate a fourth signal driving the PMOS transistor. The first signal is 180° out-of-phase with respect to the third signal.

Abstract: The invention relates to a circuit of which the operating rate varies according to temperature, supply voltage and intrinsic quality of the transistors of the circuit, associated to a compensating circuit which comprises a constant current source (26) that produces a substantially constant current which is independent of temperature, supply voltage and intrinsic quality of the transistors of the circuit, a variable current source (28) producing a current that increases in an inverse proportion to temperature, supply voltage and intrinsic quality of the transistors of the circuit, and means for decreasing the operating rate of the circuit when the difference of the currents produced by the first and second sources increases.

Abstract: A semiconductor interface circuit connected between a first semiconductor device driven by a first level power voltage and a second semiconductor device driven by a second level power voltage which is higher than the first level power voltage. The semiconductor interface circuit includes an output buffer circuit being connected to the first semiconductor device; and at least a depletion type field effect transistor connected between the output buffer circuit and the second semiconductor device, wherein the at least depletion type field effect transistor has a driving capability substantially equal to or near a driving capability of the output buffer circuit.

Abstract: A semiconductor integrated circuit device comprises a semiconductor substrate; an input and output terminal (1) formed on the semiconductor substrate; an input and output circuit (2, 3) formed on the semiconductor substrate, connected to the input and output terminal (1), and having an output buffer (2) of CMOS FETs, supply voltages Vcc1 and Vcc2 being applied to the output buffer; a semiconductor integrated circuit formed on the semiconductor substrate and connected to the input and output circuit; and a circuit for preventing forward junction current from flowing from the input and output terminal (1) to the output buffer (2) when an input voltage exceeding the supply voltages is applied to the output buffer. In an integrated circuit device using a plurality of different supply voltages, it is possible to prevent an input voltage beyond the supply voltages from being applied to the input and output circuit.