Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.

Abstract: A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.

Abstract: A semiconductor integrated circuit of embodiments includes a first MOS transistor configured to control conduction and non-conduction between a reference voltage point and a node, a second MOS transistor connected to the first MOS transistor via the node and configured to apply a voltage equal to or lower than a withstand voltage of the first MOS transistor to the node, a third MOS transistor configured to receive supply of a second voltage higher than the first voltage, and output an output signal of a signal level corresponding to a voltage range of the second voltage, and a switch circuit configured to make a voltage of the node a fixed voltage when the first MOS transistor is in an OFF state.

Abstract: A level shift circuit includes: a first transistor connected to ground and having a control terminal; a second transistor connected to the ground and having a control terminal connected to the a terminal of the first transistor; a pull-up circuit connected to a power source and also connected to the first terminal of the first transistor, and having a current mirror circuit constituted by two transistors; a third transistor having a first terminal connected to the first terminal of the first transistor, a second terminal connected to the power source, and a control terminal connected to a first terminal of the second transistor; and a fourth transistor having a first terminal connected to the first terminal of the second transistor, a second terminal connected to the power source, and a control terminal connected to the first terminal of the first transistor.

Abstract: A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.

Abstract: A circuit for implementing an input/output connection in an integrated circuit device is described. The circuit comprises a pull-up circuit comprising a first plurality of transistors coupled in series, wherein a gate of a first transistor of the first plurality of transistors is configured to receive a first dynamic bias signal; a pull-down circuit comprising a second plurality of transistors coupled in series, the pull-down circuit being coupled to the pull-up circuit at an output node, wherein a gate of a first transistor of the second plurality of transistors is configured to receive a second dynamic bias signal; and an input/output contact coupled to the output node. A circuit for implementing an input/output connection in an integrated circuit device including a splitter circuit for receiving an input signal on an input pad is also described. A method of implementing an input/output connection in an integrated circuit device is also described.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Abstract: Some embodiments provide a voltage-level shifter circuit comprising a cross-coupled transistor pull-up network that includes a plurality of diode-connected transistors configured to cause the state of the cross-coupled transistor network to switch at a low current through a pull-down network coupled thereto, such as a current corresponding to near-threshold voltage or sub-threshold voltage operation of the pull-down network.

Abstract: Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

Abstract: A control circuit and a delay circuit are provided. The control circuit includes a control unit and a feedback unit. The feedback unit is configured to output a feedback signal according to a voltage of the control unit and a reference voltage; a first terminal of the feedback unit is connected to a first terminal of the control unit, a second terminal of the feedback unit serves as an input terminal of the reference voltage, and an output terminal of the feedback unit is connected to a second terminal of the control unit. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the feedback signal, so as to allow a current variation of the control unit with a first parameter to be within a first range.

Abstract: A control circuit and a delay circuit are provided. The control circuit includes a control unit and a feedback unit. The feedback unit is configured to output a feedback signal according to a voltage of the control unit and a reference voltage; a first terminal of the feedback unit is connected to a first terminal of the control unit, a second terminal of the feedback unit serves as an input terminal of the reference voltage, and an output terminal of the feedback unit is connected to a second terminal of the control unit. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the feedback signal, so as to allow a current variation of the control unit with a first parameter to be within a first range.

Abstract: An all-MOSFET voltage reference circuit includes a first cascaded branch configured to generate a bias current and composed of a first current source and a diode-connected first N-type transistor connected at a first interconnected node; a second cascaded branch composed of a second current source, a diode-connected second N-type transistor and a third N-type transistor connected with the second N-type transistor disposed in between, wherein the second N-type transistor and the third N-type transistor are connected at a second interconnected node; a third cascaded branch composed of a third current source and a diode-connected fourth N-type transistor connected at an output node that provides a reference voltage; and an amplifier with a non-inverting node coupled to the first interconnected node and an inverting node coupled to the second interconnected node. A threshold voltage of the third N-type transistor is larger than a threshold voltage of the second N-type transistor.

Abstract: The present invention discloses a voltage level conversion circuit. A first and a second N-type driving transistors turn on when a first power voltage source supplies a high state voltage. A voltage transmission circuit transmits a first and a second input voltages having opposite levels to sources of the first and the second N-type driving transistors. A current source operates according to a second supply voltage source and has a first and a second output terminals. A first and a second connection transistors respectively couple between the drain of the first N-type driving transistor and the second output terminal and between the drain of the second N-type driving transistor and the first output terminal. The first and the second connection transistors turn on and off when the first voltage supply source supplies the high state voltage and a low state voltage.

Abstract: A level shifter includes a pull-down circuit, a pull-up circuit, a protection circuit, and an output generator. The pull-down circuit is configured to receive input voltages, and generate bias voltages. The input voltages are associated with a voltage domain. The pull-up circuit is configured to receive a supply voltage and generate control voltages. The protection circuit is configured to receive reference voltages, and control the generation of the bias voltages and the control voltages. The output generator is configured to receive at least one of the reference voltages, and at least one of the bias voltages and the control voltages, and generate output voltages that are able to reach minimum and maximum voltage levels of another voltage domain. Further, the output voltages remain unaffected by variations in process, voltage, and temperature.

Abstract: A level shifter includes a self-initialization circuit. The self-initialization circuit judges whether the input signal and the inverted input signal received by the level shifter are invalid while a power supply voltage is powered up. If the self-initialization circuit confirms that the input signal and the inverted input signal received by the level shifter are invalid, the self-initialization circuit controls the level shifter to be maintained in a self-initializing power up state. Consequently, the output signal from the level shifter has the specified voltage level.

Abstract: As disclosed herein, a level shift circuit includes devices that are responsive to an ESD signal for placing those devices in a specific condition in response to the ESD signal indicating an ESD event. In some embodiments, the devices are transistors in current paths that are placed in a condition such that during an ESD event, voltage differentials in the current paths across voltage domain boundaries do not damage the circuitry of the level shift circuit. In some embodiments, some of the same devices that are responsive to the ESD event are also responsive to a signal to that detects the absence of a power supply voltage of one of the domains and places those devices in a condition to disable the level shift circuit if the power supply voltage is not present.

Abstract: A wireless headphone system, a wireless headphone, and a base. The wireless headphone system includes the wireless headphone and the base. The base includes a base RXD wire, a base TXD wire, a base connection wire, and a base triode; and the wireless headphone includes a wireless headphone RXD wire, a wireless headphone TXD wire, a wireless headphone connection wire, and a wireless headphone transistor. The base RXD wire and the base TXD wire are connected together through the base transistor and led out through the base connection wire. The wireless headphone RXD wire and the wireless headphone TXD wire are connected together through the wireless headphone transistor and led out through the wireless headphone connection wire. When the headphone is charged on the base, two-way communication between the headphone and the base can still be implemented while maintaining the existing three-wire design.

Abstract: The invention relates to a high-voltage voltage level converter for matching of the components of electronic systems containing multiple power sources. In particular, the high-voltage voltage level converter includes seven P-type field-effect transistors and seven N-type field-effect transistors, the signal input terminal (IN), the inputs of reference source voltages ?VDD) and (?VDD), inverted output, high-level source voltage terminals (VCC) and (VDD), and low-level source voltage terminal (VSS).

Abstract: Systems, methods, and devices for generation of narrow pulses in a flying high-voltage domain that are used as a timing control signal are presented. A main signal processing path that generates the timing control signal is replicated and used to detect time and duration of perturbations due to flying events in the main signal processing path based on a fixed input level to the replicated path. Detected time and duration of the perturbations are used to generate a blanking control signal to the main signal processing path. According to one aspect, the main signal processing path may be part of a high side level shifter that operates in a flying high-voltage domain and used to control a high-voltage switching device.

Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

Abstract: Described is a high speed, low power level shifter circuit which includes a cross-coupled level shifter coupled to a sensing circuit. The sensing circuit turns off a cross-coupled node of a pair of cross-coupled nodes based on detecting that an input voltage has crossed a threshold voltage for a cross-coupled input transistor of a pair of cross-coupled input transistors, i.e. due to switching from a current logic level to an incoming logic level. Once the sensing circuit detects a threshold voltage crossing, a pull-up circuit pulls high a cross-coupled node and cross-coupled source transistor tied to the cross-coupled node. This turns off the cross-coupled source transistor and turns on another cross-coupled source transistor. Two parallel paths are now established to pull the cross-coupled node high, enabling a high-speed transition. The turning off of the cross-coupled source transistor also pulls the output to the incoming logic level.

Abstract: An embodiment of the invention provides a multi-bit flip-flop. The multi-bit flip-flop includes a clock input pin, a clock buffer circuit, and a plurality of flip-flops. The clock buffer circuit is used to receive a first clock signal received from the clock input pin and provide a second clock signal and a third clock signal according to the first clock signal. Each of the plurality of flip-flops is used to receive the second clock signal and the third clock signal and store data according to the second clock signal and the third clock signal. Therefore, the multi-bit flip-flop is designed such that makes each of the plurality of flip-flops to share the same clock.

Abstract: Fuse latch circuits and related systems, methods, and apparatuses are disclosed. An apparatus includes a half interlock latch circuit including a first half and a second half. The first half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the second half of the half interlock latch circuit in a driven state. The second half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the first half of the half interlock latch circuit in a driven state.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

Abstract: In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.

Abstract: A battery controller includes a first driving pin, a second driving pin and a third driving pin. The first driving pin is coupled to a charge switch and is operable for turning on the charge switch to enable a battery pack to be charged by a power source. The second driving pin is coupled to a first discharge switch and is operable for turning on the first discharge switch to enable the battery pack to power a first load. The third driving pin is coupled to a second discharge switch and is operable for turning on the second discharge switch to enable the battery pack to power a second load.

Abstract: A protection device includes a dynamic gate bias circuit and an input pass switch. The dynamic gate bias circuit comprises an input pass switch configured to receive a first input and a first control signal; a voltage level shifter coupled to the input pass switch; a current mirror coupled to the voltage level shifter at a first node; a regulator coupled to the current mirror at a second node; and a transistor coupled to the first node, wherein the transistor is configured to receive a second control signal from the first node and to receive the first input.

Abstract: A level shifter circuit included in a computer system may include bootstrap and feedback nodes. The level shifter circuit may discharge the feedback node in response to high-going transition on a received input signal generated using a first power supply signal. The level shifter circuit may also increase a voltage level of the bootstrap node in response to the high-going transition and charge the bootstrap node, in response to the discharge of the feedback node, to a voltage level of a second power supply signal that is different than a voltage level of the first power supply signal. The level shifter circuit may generate an output signal using the voltage levels of the feedback node and the second power supply signal.

Abstract: A first circuit and a second circuit, which have different operating voltages, are connected through a level shifter, and a combination circuit below is provided in the level shifter. An enable signal, which is switched between active and inactive states according to whether or not a potential is supplied to a second high potential power line, is applied to the combination circuit. The combination circuit outputs a first signal and a second signal, which is acquired by logically inverting the first signal, to a level shift circuit according to an output signal of the first circuit, in a case where the enable signal is active, and causes both the first signal and the second signal to be at a low level in a case where the enable signal is inactive.

Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

Abstract: In an embodiment, an apparatus includes: a repeater to receive an input signal at an input node and output an output signal at an output node; a dynamic header device coupled between the repeater and a supply voltage node; and a feedback device coupled between the output node and the dynamic header device to dynamically control the dynamic header device based at least in part on the output signal. Other embodiments are described and claimed.

Abstract: A circuit for driving a switched transistor comprises: a level shifter comprising at least one transistor, the level shifter configured to convert an input pulse to a pulse having a greater voltage swing than the input pulse and shift a voltage level of the converted pulse; and a pulse shaping filter coupled between the level shifter and the gate of the switched transistor, the pulse shaping filter tuned to cancel or reduce an impedance of the gate of the switched transistor. The switched transistor and/or the at least one transistor are a GaN High Electron Mobility Transistor (HEMT).

Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: A level shifter circuit is provided.

Abstract: There are provided a level shifter and a memory system including the same. The level shifter includes: a pull-up unit for supplying an internal power supply voltage to a first output node or a second output node in response to an input signal and an inverted input signal; a pull-down unit for applying a ground voltage to the first output node or the second output node in response to potential levels of the first output node and the second output node; and a discharge unit for discharging the potential level of the first output node or the second output node in response to the input signal and the inverted input signal.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Abstract: A level shifter includes a pair of cross-coupled PMOS transistors, intrinsic-type NMOS transistors, an input node, a control circuit and an output node. A high voltage is supplied to the PMOS transistors. The intrinsic-type NMOS transistors and the PMOS transistors are respectively coupled in serial. The input node is configured to receive input signals. The control circuit is triggered by the voltage Vdd and is configured to generate enable signals and control signals according to the input signal. The output node is configured to output the high Voltage HV or the GND voltage as the output signal. After the node aa is charged, the transistor HVNI_1 is turned off according to the control signal SW to avoid leakage current being generated. After the node MOUT is charged, the transistor HVNI_2 is turned off according to the control signal SWb to avoid leakage current being generated.

Abstract: A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.

Abstract: In order to provide a power supply switch circuit using only low-breakdown voltage transistors and eliminate the need for a special through-current preventing circuit, the switch control circuits output a signal ranging from a ground voltage level to a second power supply voltage level when a first power supply voltage (0 V/3.3 V) is in off-state and a second power supply voltage (0 V/1.8 V) is in on-state, and a signal ranging from the second power supply voltage level to a first power supply voltage level when the first and second power supply voltages are in on-state, thereby allowing a PMOS transistor and an NMOS transistor to turn on or off.

Abstract: A driving module for a display device includes a first transistor, comprising a gate coupled to a first node, a drain coupled to an output end, and a source coupled to a first positive voltage source; a second transistor, comprising a gate coupled to a second node, a drain coupled to output end, and a source coupled to a first negative voltage source; and a voltage generating unit, coupled to an input end, a second positive voltage source and a second negative voltage source for generating a first voltage at first node and a second voltage at second node according to a control signal from input end; wherein voltage difference between a first positive voltage of first positive voltage source and first voltage is smaller than first threshold and voltage difference between a first negative voltage of first negative voltage source and second voltage is smaller than second threshold.

Abstract: The present invention discloses a buffer circuit including: a pre-driver providing a first, a second, a third and a fourth driving signals according to the voltages of voltage nodes and control signals; a voltage-detection and bias circuit providing bias voltages for an output buffer and an input buffer according to the voltages of the voltage nodes and the third driving signal; the output buffer determining conduction states of the transistors of the output buffer according to the voltages of the voltage nodes, the first and the second driving signals, and the bias voltages, and thereby outputting an output signal to a signal pad; and the input buffer determining the conduction states of the transistors of the input buffer according to the voltage of the signal pad, the voltages of the voltage nodes, the fourth driving signals, and the several bias voltages, and thereby generating an input signal.

Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.

Abstract: An object is to provide a level shift circuit that operates stably. A semiconductor device includes a level shift circuit including first to fourth transistors and a buffer circuit. One of a source and a drain (S/D) of the first transistor is connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is connected to one of a source and a drain of the third transistor. A gate of the first transistor and a gate of the fourth transistor are connected to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor. A gate of the third transistor is connected to a wiring to which an input signal is input. An input terminal of the buffer circuit is connected to one of a source and a drain of the fourth transistor. An output terminal of the buffer circuit is connected to a gate of the second transistor and a wiring to which an output signal is output.

Abstract: A signal level converter includes a bias generating circuit that generates a bias voltage, and a level shifter circuit that converts a lower voltage signal into a higher voltage signal in response to the bias voltage. The bias generating circuit includes a replica circuit that controls an on-current of the level shifter circuit in response to the bias voltage output from an operational amplifier.

Abstract: A level shift circuit includes two resistors by which logic is fixed when two input terminals become low level, and a logic circuit and transistors which set the logic of an output terminal to a desired value according to the fixation of the logic.

Abstract: The present disclosure provides a voltage circuit. The voltage circuit includes a first input signal-inverting circuit, a second input signal-inverting circuit, a first level-shifting circuit, a second level-shifting circuit, a first diode circuit and a second diode circuit. The first input signal-inverting circuit receives an input signal and outputs a first inverted signal. The second input signal-inverting circuit receives the first inverted signal and outputs a second inverted signal. The first level-shifting circuit determines a voltage level of a first output node in response to the first and second inverted signals. The second level-shifting circuit determines a voltage level of a second output node in response to the first and second inverted signals. The first diode circuit is connected between a first voltage-supplying node and the first output node. The second diode circuit is connected between a second voltage-supplying node and the second output node.

Abstract: A level shifter includes a driving circuit, which receives an input signal and outputs a driving signal in response to a first voltage level of the input signal; a level shifting circuit, which outputs an output signal of a second voltage level in response to the driving signal; and a leakage prevention circuit, which prevents a leakage current of the driving circuit, wherein the driving circuit may include at least one native transistor.

Abstract: A level shifter circuit includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, and a low state pulse generator. The high voltage latch circuit includes a non-inverting output terminal, an inverting output terminal, a high state trigger input terminal, and a low state trigger input terminal. The low voltage latch circuit includes a high state trigger input terminal and a low state trigger input terminal. The high state trigger input terminal is coupled to the inverting output terminal of the high voltage latch circuit. The low state trigger input terminal is coupled to the non-inverting output terminal of the high voltage latch circuit. The high state pulse generator is coupled to the high state trigger input terminal of the high voltage latch circuit. The low state pulse generator is coupled to the low state trigger input terminal of the high voltage latch circuit.

Abstract: A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.