Abstract: In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.

Abstract: A packaged integrated circuit device includes a first driver, which has a first pair of differential output terminals and a first common-mode sensing terminal, and a second driver, which has a second pair of differential output terminals and a second common-mode sensing terminal. The second driver can be a smaller scaled replica of the first driver. A comparator and a reference signal generator are provided. The comparator is configured to compare first and second common-mode voltage signals developed at the first and second common-mode sensing terminals, respectively, and the reference signal generator is configured to provide the first and second drivers with a reference voltage having a magnitude that varies in response to changes in a signal generated at an output terminal of the comparator. This variation in the magnitude of the reference voltage supports a built-in adaptive response to changes in source-side termination in HCSL driver/receiver circuits.

Abstract: A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch.

Abstract: A control circuit includes a platform controller hub (PCH), a basic input/output system (BIOS), an electronic switch, and first and second resistors. A management engine interface is loaded in the PCH. The BIOS is connected to the PCH to control the signals output from a general input/output (GPIO) pin of the PCH. A power supply is connected to a serial pin of the PCH through the electronic switch. The GPIO pin of the PCH controls on or off of the electronic switch.

Abstract: Apparatus and methods are provided for generating output signals representative of bits of serial data. A transmitter includes driver circuitry configured to generate an output signal at an output node and an allocation control module coupled to the driver circuitry. The driver circuitry includes a plurality of driver legs configured to generate the output signal based on a plurality of data bits. The allocation control module is configured to allocate a respective subset of the plurality of driver legs to a respective data bit of a plurality of data bits, wherein the each subset generates a component of the output signal that is influenced by its respective data bit.

Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.

Abstract: An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad.

Abstract: A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process.

Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.

Abstract: A solid-state switch according to the invention is designed to be connected in series with a load. The switch comprises at least two electric switching means connected in parallel, measuring means designed to measure an electric voltage at the terminals of the electric switching means and a main current flowing in the load, and control means delivering a control signal to act on opening and closing according to the value of the main current. The state of conduction of the first electric switching means depends at the same time on the main current flowing in the load, on a control current, on a control voltage delivered by the control means, and on the gain of the first electric switching means.

Abstract: An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.

Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.

Abstract: According to various embodiments, a differential transmitter includes a driver and a predriver. In various embodiments, the predriver may include pull-up transistors and pull-down transistors configured in various ways to produce a staged output signal during a pull-up transition, wherein the higher bits of the input signal are switched slower in comparison with the lower bits of the input signal, while at the same time maintaining the simultaneous pull-down transition among all the bits. In various embodiments, the staged output of a predriver may further be dynamically disabled during a deemphasis exit transition. Other embodiments may be described and claimed.

Abstract: A driving auxiliary circuit receiving an input voltage to control an output voltage of an operational amplifier via a first switch and a second switch is provided. A pull-low circuit turns on the first switch, including a first input terminal coupled to a high voltage source providing a high voltage and a first output terminal for controlling the voltage level of the output voltage. The output voltage is charged to be equal to the input voltage when the input voltage exceeds the output voltage. A pull-high circuit turns on the second switch, including a second input terminal coupled to the high voltage source providing the high voltage and a second output terminal for controlling the voltage level of the output voltage. The output voltage is discharged to be equal to the input voltage when the output voltage exceeds the input voltage.

Abstract: A drive circuit for a power switch component.

Abstract: Embodiments of the invention include a common mode cancellation circuit and method for correcting signal skew in a differential circuit. According to one embodiment, an op amp circuit is used to correct the mismatch between transmission line lengths in the differential circuit. The CMCC can be embodied as an ASIC and added on to an existing differential signaling systems to correct and compensate for board wiring skew or other causes of phase misalignment. The result is restoration of the cross-over intersection of the plus and minus signals of the differential pair closer to the common voltage level point, as if the signals had been in phase.

Abstract: A high voltage driver circuit for devices such as non-volatile memories, in which a low voltage driver is combined in two different ways with a high voltage driver In one, input-independent embodiment, a low voltage driver (Q7, Q8) is connected directly in parallel with a high voltage driver, thereby providing a high voltage signal path for high voltage operations and a low voltage signal path for low voltage operations. In an alternative, partially input-dependent embodiment, a low voltage driver is connected to the output of a high voltage driver (Q9, Q10), which may comprise a partial level shifter (Q1 B Q6). The output of this low voltage driver (Q9, Q10), which forms the output terminal of the entire stage, has a pull up/pull down transistor (Q11), depending on whether the partial level shifter (Q1 B Q6) is a positive or negative level shifting high voltage driver.

Abstract: A semiconductor integrated circuit according to the invention has a plurality of output transistors connected to an output terminal through which output data is outputted, and an impedance control circuit and a slew rate control circuit. The impedance control circuit generates control signals specifying output transistors to be turned on when the output data is output, from among the plurality of output transistors. The slew rate control circuit generates, according to the control signals, drive signals driving the output transistors to be turned on, and variably sets respective delay times of the drive signals according to the control signals.

Abstract: A bi-directional buffer is connected between a first node and a second node, wherein the first node is connected by a first pull-up resistor to a first voltage supply rail, and the second node is connected by a second pull-up resistor to a second voltage supply rail. In an embodiment, the bi-directional buffer is enabled when a voltage of the first node does not exceed a first threshold voltage, and/or a voltage of the second node does not exceed a second threshold voltage. However, when the voltage of the first node exceeds the first threshold voltage, and the voltage of the second node exceeds the second threshold voltage, the bi-directional buffer is disabled, which disconnects the first and second nodes. This allows the first node to be pulled up to the first voltage supply rail, and the second node to be pulled up to the second voltage supply rail.

Abstract: A CMOS output driver is provided for driving a capacitive load over a circuit trace in high speed applications. The CMOS output driver comprises a signal input and a signal output. The output driver has a first buffer amplifier with an input connected to the signal input and an output connected to the signal output through a resistor. A second buffer amplifier is also provided, which has an input connected to the signal input and an output connected to the signal output through a capacitor.

Abstract: Embodiments that decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one or more elements to conserve power after an input signal remains unchanged for a period of time. Another embodiment reduces power consumption in a circuit, the embodiment comprising a swing module coupled with a swing selector and an output controller. The swing module may generate full or low swing signals depending on the state of the swing selector. The output controller may increase the output impedance of the swing module after an input signal to the swing module remains unchanged for a quantity of time. Various apparatus embodiments include portable computing devices and cellular telephones.

Abstract: There is provided a switching circuit including, a semiconductor switching circuit comprising, a transistor, a first electrode of the transistor being connected to an electrical source via a load, a second electrode of the transistor being connected to a standard potential, a driving circuit outputting a signal to a control electrode of the transistor on a basis of a potential in the first electrode of the transistor so as to turn on and off the transistor, the driving circuit turning on when an input voltage applied from an input terminal being a first voltage higher than a threshold voltage of the transistor, the driving circuit turning off when the input voltage being a second voltage lower than the threshold voltage of the transistor.

Abstract: An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.

Abstract: A plurality of transistors are connected between an I2C bus operating at a first voltage level and an I2C bus operating at a second voltage level and a main control electrode of at least one transistor is connected to a first power supply terminal and a main control electrode of the other at least one transistor is connected to an intermediate level between the first voltage level and the second voltage level, whereby a withstand voltage required to a transistor of the bidirectional level shift circuit of the I2C bus can be lowered.

Abstract: A rail-to-rail high speed subLVDS receiver demonstrates good jitter and duty cycle performance for high-speed signals at low power supply levels. A sample receiver includes a voltage shifter for shifting the voltage levels of a differential input signal so that a shifted differential input signal is produced. The shifted differential input signal can be applied to a first differential pair, and the differential input signal can be applied to a second differential pair. The outputs of the first and second differential pairs can be summed together to produce a differential output signal. The differential output signal can be output using an output block. A clamp circuit can be used to adjust the gain of the first differential pair responsive to a common mode voltage of the first and second differential input signals.

Abstract: An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132).

Abstract: A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The first PFET is configured to convert a low level signal at the input terminal to a high level signal at the output terminal, and the BJT is configured to convert a high level signal at the input terminal to a low level signal at the output terminal. The radiation hardened inverter includes a second PFET disposed in the second electrical path. The second PFET is configured to provide a path for bleeding excess current away from the BJT. The radiation hardened inverter also includes a current limiting PFET disposed in the second electrical path. The current limiting PFET is configured to limit current flowing into a base of the BJT. The radiation hardened inverter is free-of any NFETs.

Abstract: A pull-up circuit comprises an operational amplifier which forms part of a feedback circuit, acting to bring a pull-up circuit output equal to a reference voltage input. The pull-up circuit may form part of a USB transceiver for incorporation in a USB Device. When the supply voltage of the USB Device is sufficiently high, it is used to provide the required pull-up voltage, with the feedback circuit including the operational amplifier the USB Device is not high enough to provide the required pull-up voltage. In that case, the USB bus voltage is used to generate the reference voltage which is used as an input to the feedback circuit.

Abstract: A differential input driver circuit (10, 50) includes first and second transistors (Q0, Q3) as input transistors and third and fourth transistors (Q1, Q2) as diode-connected, cross-coupled transistors. In one embodiment, first, second, third and fourth transistors are NPN bipolar transistors. The base terminals of the first and third transistors are connected while the base terminals of the second and fourth transistors are connected. The input transistors receive a pair of differential input signals (In+/?) at the emitter terminals (24, 26) and provides a pair of differential output signals (Vo+/?) at the collector terminals (16, 18). The emitter terminals of the diode-connected transistors (Q1, Q2) couple the input signal at the emitter terminal of the first transistor to the collector terminal of the second transistor and vice versa. The cross-coupling of the third and fourth transistors enables the input driver to operate effectively in single-ended to differential conversion mode.

Abstract: A flat display device may include a plurality of electrodes arranged in one direction, a first transistor coupled between the plurality of electrodes and a first power source for supplying a first voltage, and a gate driving circuit for supplying a driving voltage to a gate of the first transistor through a push-pull circuit including second and third transistors coupled between second and third power sources for respectively supplying second and third power sources, wherein a resistance formed between the second transistor and the second power source is greater than that formed between the third transistor and the third power source.

Abstract: A drive circuit of a computer system is for driving a mode indicator. The computer system includes a first port and a second port. The mode indicator includes a first receiving end and a second receiving end. The drive circuit includes a first input end connected to the first port, a second input end connected to the second port, a first output end connected to the first receiving end, a second output end connected to the second receiving end. A power supply is connected to the first input end and the second input end via a first resistor and a second resistor respectively. The mode indicator is dichromatic and has two LEDs emitting non-matching colored light.

Abstract: A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may be prevented from delivering its current. The present invention provides a supplemental current that is active during this transition period to supply the missing current. The present disclosure also details a common mode circuit that maintains a stable common mode output level to help control EMI issues when the power supply for the driver changes.

Abstract: Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.

Abstract: A reference voltage circuit having an open-loop buffer driven by a matching buffer included within a closed-loop, generates a stable differential or single-ended voltage while minimizing signal-dependent short-term and long-term drift. The open-loop buffer may be a replica of the closed-loop buffer, reducing the effect of a signal coupled on the voltage reference lines. The reference voltage circuit may be adapted for a switched capacitor ADC.

Abstract: An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data signals, respectively. The circuit also includes a plurality of off-chip drivers for respectively receiving the delayed data signals from the respective delay circuits and generating respective output signals in response to respective control signals, wherein the total number of the off-chip drivers to be activated at the same time is changed by the respective control signals which are generated in response to a desired drivability, and the activated off-chip drivers sequentially generate the output signals in response to the delay times, thereby increasing a total drivability of the off-chip driver circuit.

Abstract: A buffer circuit includes an input terminal operable to receive an input signal and an output terminal at which an output signal for the buffer circuit is provided. In the buffer circuit, three transistors at most provide signal currents. Two of the three transistors can be matched. Means are provided for feeding back the output signal so that the two matched transistors are balanced in response to a change in the input signal appearing at the input terminal.

Abstract: As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for generating from input signals (A) and (B) drive signals (a) and (b) to control the action of the semiconductor switching element is provided comprising a characteristic compensating means (2) for generating from a characteristic compensation input signal a compensation signal to eliminate variations in the transmission delay time of the drive controlling means (1).

Abstract: A CMOS driver with minimum shoot-through current is disclosed. The potential for shoot-through current may be eliminated or reduced with a break-before-make circuit driving an output stage. The break-before-make circuit may include a first logic element followed by a first inverter and a second logic element followed by a second inverter. The inverters may be cross-coupled to one another and/or the internal transistors may be configured with different strengths. The logic elements may be configured to eliminate or reduce potential shoot-through current paths, and the signal inputs may be controlled within a certain voltage range.

Abstract: A high-side driver circuit for driving a load, including a low-side driver IC having a drive output and a feedback input, a first transistor coupled to the drive output, and a second transistor coupled between a power source and the load. The second transistor is configured to enter an “OFF” state when the first transistor is driven into an “OFF” state by the drive output, and to enter an “ON” state when the first transistor is driven into an “ON” state by the drive output.

Abstract: The invention provides a semiconductor device which performs a write operation of a signal current rapidly to a current input type pixel. Before inputting a signal current, a precharge operation is performed by flowing a large current. After that, a signal current is inputted to perform the set operation. A predetermined potential can be obtained rapidly as the precharge operation is performed before the set operation. The predetermined potential is approximately equal to a potential after completing the set operation. Therefore, the set operation can be rapidly performed and a write operation of a signal current can be rapidly performed. By using two transistors, a gate width W can be long or a gate length L can be short in the precharge operation or the gate width W can be short and the gate length L can be long in the set operation.

Abstract: A method and an apparatus are described for a voltage tolerant input buffer. An embodiment of an input buffer includes a differential circuit and a plurality of switches coupled with the differential circuit. The plurality of switches applies a voltage to the differential circuit in a first state and isolate the differential circuit from the voltage in a second state.

Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: An output circuit includes a source follower constituted by a n-channel MOS transistor, having a drain connected to a power source and a source connected to an output terminal, and applying an output voltage to a load through the output terminal when a gate is charged, a voltage detector determining if the output voltage is at a first voltage or at a second voltage level, a first discharge circuit discharging the gate of the source follower according to an inputted turn-off signal when the output voltage is at the first voltage level, and stopping discharging the gate of the source follower when the output voltage decreases to the second voltage level and a second discharge circuit discharging the gate of the source follower more gradually than the first discharge circuit does according to the turn-off signal when the output voltage decreases from the first voltage to the second voltage level.

Abstract: A basic switching circuit combines CMOS and bipolar technique on SiGe basis and operates at a low operating voltage of only slightly more than 2V. To achieve this low operating voltage, switching operation of the circuit is effected by switching a constant current source of the switching circuit on or off using MOS transistors. In addition, the constant current source is implemented using a MOS transistor rather than a bipolar transistor, which basically acts as a controllable resistor. Moreover, the logic levels in the output signal are accurately controlled using a constant current source that is controlled by an operational amplifier and a resistor voltage divider at the output to pull the voltage level down by an amount that corresponds to the logical levels.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto.

Abstract: An input circuit comprises an input terminal for receiving an input signal, an output terminal for outputting an output signal, a node connected to the input terminal, a terminating resistor connected between the node and a ground, a potential shift element connected between the node and the output terminal, a potential source for supplying a predetermined potential, and a current source connected between the potential source and the output terminal.

Abstract: The invention concerns a switching circuit (20) adapted to generate a pulse when there occurs a rising edge of a signal applied on an input terminal (CTRL), comprising: a first NPN type bipolar transistor (TN2) whereof the transmitter is connected to the input terminal; a second transistor (TP2) whereof a control electrode is connected, through a first resistor (Re2), to the input terminal, the base of the first transistor being connected to a supply potential (VDD) by the second transistor in series with a second resistor (Rp2); and a third transistor (TN3) connecting an output terminal (22) of the switching circuit to a reference potential (GND) and whereof a control electrode is connected to the collector of the first transistor (TN2).

Abstract: A system and method is described for a driver circuit used for high speed data transmission in LVDS and CML transceiver device applications. The transceivers are intended to receive a low voltage differential input signal and interchangeably drive a standard LVDS load with a TIA/EIA-644 compliant LVDS signal, and a standard CML load with a standard CML compatible signal. The driver circuit operates at speeds up to 1.36 Gbps, making it compatible with the OC-24 signaling rate for optical transmission. To accomplish this, the driver uses a mixed combination of voltage and current mode drive sections in the output circuit when coupled to LVDS loads, and when the driver is coupled to CML loads, operates purely in a current mode using only the current mode drive section.

Abstract: A main driver, in which NPN and PNP bipolar transistors are connected in series, is driven by an output of a pre-driver having a first CMOS circuit driven by an input signal. An assist circuit having a second CMOS circuit driven by the input signal and also having a current limit resistor is provided, and an output of the main driver is assisted by an output of the assist circuit. Therefore, it is possible to reduce a short circuit current in a transistor output circuit, to increase and decrease an output signal to an power-supply potential (upper limit) and a ground potential (lower limit), and to smoothly change the output signal near the power-supply potential and the ground potential. Further, an intensity of electromagnetic noise is reduced and a switching output having a sufficiently large amplitude is supplied.

Abstract: A circuit arrangement for an LVDS driver, which uses combined bipolar and MOSFET technology with at least two MOSFETs, is shown, wherein a multiplier circuit is connected to an output stage of the LVDS driver and the multiplier circuit is controlled by means of an automatic control circuit, which generates control signals for controlling a current source of the multiplier circuit and for controlling the amplification factor of differential input signals of the multiplier circuit. Advantages of the invention are that it enables said technology, in which semi-conductor components are used in bipolar techniques (e.g. NPN and/or PNP transistors) (as well as MOS technology), to take advantage of the high speed of the bipolar elements compared with MOS elements.