Abstract: The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a delayed reset signal and a second flip-flop configured to generate a second signal, the second signal transitioning to the first logic level in response to a second edge of a second input signal and transitioning to the second logic level in response to the delayed reset signal. The phase-frequency detector may further include a first delay unit configured to delay a reset signal to generate the delayed reset signal and a second delay unit configured to delay the reset signal to generate an output control signal for adjusting at least one of the first and second signals.

Abstract: A method and radiation hardened phase frequency detector (PFD) for implementing enhanced radiation immunity performance, and a design structure on which the subject PFD circuit resides are provided. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract: A semiconductor memory apparatus includes a phase comparator configured to compare phases of rising and falling feedback clocks with that of a reference clock, a delay circuit configured to delay the reference clock by a predetermined time based on a comparison result of the phase comparator to thereby generate rising and falling delayed clocks, a clock transmission block configured to invert the rising delayed clock outputted from the delay circuit when the rising and falling feedback clocks have substantially different phases, a duty compensator configured to compensate a duty ratio from outputs of the clock transmitting block to generate a delay locked clock having a compensated duty ratio, and a delay model configured to delay an output and an inverse output of the duty compensator by a modeled delay time respectively to generate the rising and falling feedback clocks.

Abstract: A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.

Abstract: A time-to-digital converter comprises a ring oscillator, a counter, an encoder, and a multi-bit latch. The ring oscillator comprises a first input and a clock input, as well as, a first output responsive to a single cycle of the ring oscillator and a second output responsive to a signal applied at the first input. A counter coupled to the first output generates a first binary word. An encoder coupled to the second output generates a second binary word. The multi-bit latch receives the first and second binary words and generates a composite representation of a phase-frequency error signal. The time-to-digital converter is well suited for digital phase-locked loops used in communications applications and digital phase-locked loops in electromechanical control systems that require high-precision phase-frequency error detection.

Abstract: A rotational frequency detector system including a rotational frequency detector responsive to a data signal and a clock signal. The rotational frequency detector is configured to compare the frequency of the clock signal to the frequency of the data signal to define frequency up and frequency down signals that adjust the frequency of the clock signal to be equal to the frequency of the data signal. A step control system is responsive to the rotational frequency detector and a step clock signal and is configured to define predetermined pulse widths for the frequency up and frequency down signals.

Abstract: An inverted-phase detector is implemented in a system including a first clock circuit that provides a first clock signal and a delayed clock circuit that outputs an delayed clock signal. A reference circuit outputs a reference signal. A feedback circuit generates a feedback signal that is one of greater than and less than the reference signal when the first clock signal changes state before the second clock signal, and that is the other of greater than and less than the reference signal when the first clock signal changes state after the second clock signal.

Abstract: Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e.g., x1, x2, x4, x8, . . . ) according to delay. Each of the plurality of delay chain units may include a respective phase comparator. Each phase comparator is configured to identify whether a delay provided by the corresponding delay chain unit exceeds a fraction of a period of a reference clock signal applied to an input of the delay chain. This fraction of a period may be equivalent to one-half or other percentage of a period of the reference clock signal. The phase comparators with the delay chain units operate to generate a multi-bit delay value signal, which is provided to a delay chain control circuit.

Abstract: In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated ‘I’ and ‘Q’ channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.

Abstract: Methods and apparatus are provided for trimming a phase detector in a delay-locked-loop. A latch that evaluates a phase offset between two signals is trimmed by applying two signals to the latch that are substantially phase aligned; obtaining a phase offset between the two signals measured by the latch; and adjusting a trim setting of one or more buffers associated with the two signals until the phase offset satisfies one or more predefined criteria. The two signals can be a clock signal and an inverted version of the clock signal. The two signals can be a source of phase aligned data generated from a single clock source.

Abstract: An improved clock lock detection circuit is disclosed. The circuit has a first input indicating an edge of a first clock and a second input indicating a corresponding edge of a second clock wherein the second clock is expected to be synchronized with the first clock with an allowable time difference. Further, it has a difference generation module for generating a difference signal based on the time difference between the first and second inputs, and a voltage divider module for receiving the difference signal and generating an indication voltage which varies based on a change of the time difference between the first and second inputs.

Abstract: A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: A phase detector includes a first flip flop having a data input coupled to a first clock signal at a first frequency and a clock input coupled to a second clock signal at a second frequency. The frequency of the first clock signal is a multiple of the frequency of the second clock signal. The phase detector also includes a second flip flop having a data input coupled to an output of the first flip flop and a clock input coupled to the second clock signal.

Abstract: A system and method of reducing the pulse width differential in a phase frequency detector (PFD) is provided. In a first embodiment, a PFD is construed using a plurality of flip-flops (or clocking devices) and a plurality of logic gates. A first set of flip-flops are adapted to receive a plurality of inputs and a plurality of clocks and to latch the inputs at transitions in the clocks. A first logic gate is then used to reset the first set of flip-flops and a second set of flip-flops if the inputs are latched (i.e., the clocks are active). If an input is not latched (i.e., a clock is inactive), then the first and second set of flip-flops are not reset, and the outputs of the PFD are forced to zero. Once the inactive clock is reactivated, a third set of flip-flops is used to hold the first set of flip-flops in a reset state for a period of time (e.g., half a clock cycle). Once the period of time elapses, the first set of flip-flops is released from its reset state, and normal operation is resumed.

Abstract: A phase difference detector adapted to generating a signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first signal and having a first output signal, and a second bistable element clocked by the second signal and having a second output signal; means for determining the variation of the signal indicative of the phase difference, responsive to the first and second output signals, and a reset circuit having a first and a second inputs respectively connected to the first and second output signals and adapted to determine the resetting of the first and second bistable elements in response to the attainment of a respective prescribed state by the first and the second output signals. The first and second inputs of the reset circuit are substantially symmetrical to each other from the point of view of an input impedance associated to each of them.

Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

Abstract: An apparatus and method is disclosed for programmable determination of frequency, phase, and jitter relationship of a first clock and a second clock in an electronic system. In a first, initialization, mode, a first register and a second register are initialized with a first bit pattern and a second bit pattern, respectively. In a second, normal, mode, the first clock is coupled to the first register and the second clock is coupled to the second register. A compare unit observes the bit patterns of the first and second registers and reports when one or more predetermined relationships between the first clock and the second clock occur.

Abstract: Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages.

Abstract: A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.

Abstract: Delay-locked loop (DLL) integrated circuits include digital phase comparators that are unaffected by variable duty cycle ratios. These phase comparators determine a shortest direction to phase lock before establishing a value of a compare signal (COMP) that specifies the shortest direction. The phase comparator is responsive to a reference clock signal REF and a feedback clock signal FB. These clock signals have equivalent periods and may have equivalent non-unity duty cycle ratios. The phase comparator is configured to determine whether a first degree to which the reference clock signal REF leads the feedback clock signal FB is smaller or larger than a second degree to which the reference clock signal REF lags the feedback clock signal FB. Based on this determination, the phase comparator generates a compare signal COMP that identifies a direction in time the feedback clock signal FB should be shifted to bring it into alignment with the reference clock signal REF.

Abstract: A phase detector includes a first selection circuit configured to select a first clock from a first group of clocks supplied to the first selection circuit and to transmit the first clock, and at least one phase comparator configured to detect a difference in phases between the first clock and a second clock supplied to the phase comparator and to transmit the difference as a scan signal.

Abstract: A phase frequency detector used in a phase locked loop includes a phase error detecting unit for outputting phase error signals according to a phase error between a first input signal and a second input signal, and a reset unit coupled to the phase error detecting unit. The reset unit outputs reset signals according to the first and second input signals so as to reset the phase error detecting unit without delay time. Thus, it is possible to make the output timing of the phase error signal in a more precisely linear proportion to the phase error value and to enhance the sensitivity of the phase locked loop.

Abstract: A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic. Moreover, it provides a frequency-scalable circuit that unlike a conventional phase-and-frequency detector (PFD), does not rely on asynchronous elements.

Abstract: First and fourth phase difference signals, and first and second phase difference information signals respectively having first, fourth, second and third phase differences may be generated using an input signal and a plurality of clock signals each of which has different phase with each other. A level of the first phase difference information signal may be lowered, and a second phase difference signal having a first level less than levels of the first and fourth phase difference signals may be generated. A level of the second phase difference information signal may be lowered, and a third phase difference signal having a second level less than the levels of the first and fourth phase difference signals may be generated. The level of the phase difference signals having a phase difference lower than 45° may be lowered, and thus the operational speed of a CDR device may be maintained and/or the jitter characteristics may be enhanced.

Abstract: A phase detector employs a modified logic gate in conjunction with a set/reset latch to make a phase detector that generates control outputs for use in increasing and decreasing the delay in a delay circuit in the path of a feedback clock generated by delaying a reference clock. The delay circuit provides a controllable delay from less than to greater than one clock cycle of the reference clock. The phase detector generates an up control (UP) signal for increasing delay when the feedback clock leads the reference clock and a down control (DN) signal for decreasing delay when the feedback clock lags the reference clock. The UP signal and DN signal are updated each clock cycle when the leading clock edge makes a transition.

Abstract: Provided is a phase frequency detector for use in a phase locked loop (PLL) or a delay locked loop (DLL), the phase frequency detector including: an UP signal output unit having a first stage operated according to a reference clock delayed by a predetermined time and a reset signal, a second stage operated according to the reference clock and an output of the first stage, and an inverter for inverting an output of the second stage; a DOWN signal output unit having: a first stage operated according to an outer clock delayed by a predetermined time and the reset signal, a second stage operated according to the outer clock and an output of the first stage, and an inverter for inverting an output of the second stage; and a logic gate logically combining the output of the second stage of the UP signal output unit and the output of the second stage of the DOWN signal output unit to generate the reset signal, thereby a phase range of the input signal with which an effective control signal can be obtained is wide so

Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

Abstract: A phase detector includes a first flip-flop responsive to a reference clock signal, a first inverter responsive to an output of the first flip-flop, a second flip-flop responsive to a feedback clock signal, a second inverter responsive to an output of the second flip-flop, a third inverter responsive to an output of the first inverter, a fourth inverter responsive to an output of the second inverter, a first conjunction circuit responsive to the output of the first inverter and to an output of the fourth inverter, and a second conjunction circuit responsive to the output of the second inverter and to an output of the third inverter. The first conjunction circuit outputs a first alignment signal when the feedback clock signal is earlier than the reference clock signal, and the second conjunction circuit outputs a second alignment signal when the feedback clock signal is later than the reference clock signal.

Abstract: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

Abstract: The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a phase/frequency comparator PD, which supplies a regulation signal Tun, which is subjected to pulse width modulation according to the difference observed. The device also includes a current source, which is designed to emit a charge current Ics, with a value which is controlled by the regulation signal Tun. The device further includes a capacitive element Cs, which is designed to generate the control signal Vcnt, under the effect of the charge current Ics. By means of a regulation signal Tun, which has a frequency which is virtually constant, the invention makes it possible to impose high-frequency variations on the control signal Vcnt.

Abstract: A data sampling apparatus includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for sequentially delaying a strobe signal by a second delay amount which is larger than the first delay amount, and a plurality of timing comparators for sampling a plurality of data signals delayed by the plural stages of first variable delay elements by the strobe signal delayed by the second variable delay element of the same stage, wherein the timing comparator includes a dynamic D-FF circuit for latching and outputting the data signal by its parasitic capacitance based on the strobe signal, a buffer for delaying the strobe signal, and a positive feed-back D-FF circuit for latching and outputting the output signal outputted by the dynamic D-FF circuit by its positive feed-back circuit based on the strobe signal delayed.

Abstract: Embodiments of an edge detector and related methods are disclosed. One method embodiment for detecting the rising and/or falling edge of an input clock signal of unknown phase and frequency includes providing a reference clock signal of a known phase and frequency to an edge detection circuit; dividing and phase shifting the reference clock signal to provide a plurality of meta flip-flop clock signals; providing the plurality of meta flip-flop clock signals and an input clock signal to a plurality of flip-flop pairs that provide meta-stability resolution; selecting the earliest output signal of the plurality of flip-flop pairs to register a transition on the input clock signal; providing a signal corresponding to the transition to an edge detection circuit; and providing an edge detect indication at the edge detection circuit during one of the corresponding high and low phase of the input clock signal.

Abstract: A delay-locked loop device capable of anti-false-locking includes a voltage control delay circuit including a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupling to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupling to the phase detector for generating the control voltage to the voltage control delay circuit according to the control signal; and a lock detector coupling to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of each delay unit of the voltage control delay circuit.

Abstract: An apparatus comprising a first circuit configured to generate (i) a pump up signal in response to a reference signal and a reset signal and (ii) a pump down signal in response to an input signal and said reset signal and a second circuit configured to (i) generate said reset signal in response to said pump up signal and said pump down signal.

Abstract: A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.

Abstract: A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain that is clocked with a first clock signal and second circuitry disposed in a second clock domain that is clocked with a second clock signal. The phase detector includes means for sampling the second clock signal with the first clock signal to generate a sampled clock signal. By tracking movement in a predetermined transition in the sampled clock signal, the phase detector is operable to determine the phase difference between the first and second clock signals.

Abstract: A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for high speed frequency discrimination (or frequency comparison) in applications such as frequency acquisition in frequency synthesizers. The complex SSB down-converter consists of a quad of mixers and quadrature splitters in both the signal path and local oscillator (LO) path. Each mixer receives both the signal and the LO, each either in-phase or quadrature. The outputs of mixers are combined in pairs, to produce the SSB in-phase (I) baseband signal and the SSB quadrature (Q) baseband signal. Both I and Q signals are then delayed, each multiplied by un-delayed version of the other one. The multiplication products are summed together, to produce an FD error signal, or an FM demodulated signal at the output.

Abstract: A semiconductor integrated circuit includes a first clock input and a second clock input to receive elements of a differential clock signal. Each clock signal element has a logic state. The circuit generates an output activation signal that depends on the states of the differential clock input signals. Operation of the circuit does not require detection of a frequency of the differential clock signal.

Abstract: A reference clock signal or a clock signal delayed in phase from the clock signal by ?/2 is input to D input terminal of a flip-flop circuit. An FSM receives signals input to the flip-flop circuits and signals which have been held by the flip-flop circuits, and outputs an up signal and a down signal. The flip-flop circuits and the FSM operate in synchronization only with a rising edge of a data signal.

Abstract: A phase comparison circuit has (1) a data discriminator to which a data signal is input for discriminating the data signal using a clock signal, (2) a logic circuit for outputting the exclusive-OR data of the data signal and a data discrimination signal output by the data discriminator and inputting the result of the exclusive-OR as a phase-difference signal to a clock generator which generates the clock signal, (3) an erroneous-synchronization phase detector for detecting whether the phase difference between the data signal and the clock signal resides within a range of phases for which there is a possibility of erroneous synchronization, and (4) an output fixing unit which holds the phase-difference signal at a fixed value if the phase difference resides within the above-mentioned range of phases, thereby it is possible to eliminate erroneous synchronization in which the clock generator is locked to a phase other than a target phase.

Abstract: The present invention helps to mitigate and reduce the amount of interfering signals (e.g. RF leakage) that enter the phase detector of a phase locked loop by acting as a less than perfect sampler. This is accomplished by introducing a time jitter to the signal edges that enter the phase detector input. A phase detector can also be made to act as a less than perfect sampler by intentionally introducing an interfering signal. For example, a small interfering analog signal can be introduced with a different frequency from the reference frequency already present in the PLL. The interfering signal will cause the stable internal signal to vary slightly in time at the rate of the interfering signal frequency. It is this signal variation and jitter introduced on the signal edges entering the phase detector input that induces the phase detector to act as a less than perfect sampler.

Abstract: When both the sourcing command and the sinking command to the phase comparator are high, the charge pump phase detector creates a high impedance output dead period, which is undesirable. The dead zone can be minimized by resetting the phase comparator when both sourcing command and sinking command are high. Accurate timing of the reset signal is crucial to good PLL phase noise performance and also to the elimination of the dead zone problem. In our invention, accurate reset timing is achieved by including the charge pump delay time caused by the input gate capacitance of the output complementary MOSFETs in the reset signal path.

Abstract: A phase-locked loop (PLL) employs a phase detector (PD) generating an up/down signal based on the phase error between a data signal and a clock signal input to the phase detector. The PD senses excess jitter and extends the loop bandwidth to accommodate such excess jitter. Phase error is derived by sampling of the clock signal and at least one phase-shifted version of the clock signal by the data signal, and a retimed data is generated by the PD by sampling of the data signal by the clock signal. The sampled clocks are employed to generate a modified control signal with greater resolution in detecting the phase error, which, in turn, increases the loop bandwidth.

Abstract: A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The phase detector includes a series of flip flops disposed in parallel that sample the second clock signal with both a rising edge of the first clock signal and a falling edge of the first clock signal. By tracking movement in one-to-zero or zero-to-one transitions in the sampled clock signals, the phase detector is operable to determine the phase difference between the first and second clock signals.

Abstract: A jitter-less phase detector in a clock recovery circuit is disclosed. A first control signal generating circuit generates a first control signal by inverting and delaying input data signals through half clock. A second control signal generating circuit generates a high level second control signal when the data signal changes. A phase comparator generates an up signal having a high-level from the falling edge of the first control signal to the falling edge of the second control signal, and generates a down signal having a high-level from the falling edge of the second control signal to the falling edge of the first control signal, so as to control a pair of current sources to selectively discharge and charge a capacitor.

Abstract: The present invention relates to cycle slip detectors for phase and frequency detectors (PFD) and to lock detectors for phase lock loop (PLL) circuits. The present invention provides a cycle slip detector circuit for use with a phase and frequency detector circuit having first and second signal inputs, and arranged to provide first and second PLL control signal outputs responsive to clock edges in the first and second input signals respectively; the cycle slip detector circuit comprising: means for determining a cycle slip between said input signals by determining when a delayed output signal coincides with a respective input signal.

Abstract: A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for high speed frequency discrimination (or frequency comparison) in applications such as frequency acquisition in frequency synthesizers. The complex SSB down-converter consists of a quad of mixers and quadrature splitters in both the signal path and local oscillator (LO) path. Each mixer receives both the signal and the LO, each either in-phase or quadrature. The outputs of mixers are combined in pairs, to produce the SSB in-phase (I) baseband signal and the SSB quadrature (Q) baseband signal. Both I and Q signals are then delayed, each multiplied by un-delayed version of the other one. The multiplication products are summed together, to produce an FD error signal, or an FM demodulated signal at the output.

Abstract: The invention relates to a new phase detector state machine having a reset state that is released only when both phase detector input signals (R, V) have a common predetermined signal state. In this way, phase inversion is effectively prevented. The complementary phase error is properly masked and the phase detector range is reduced to the interval—180°<&thgr;e<180°, while still maintaining the direction sensitivity. Phase errors &thgr;e larger than half a period are automatically discarded. Consequently, if the phase detector ends up in a state, for example due to reference clock loss, in which the phase error is larger than half a period, the phase detector will be shifted back to normal operation with a phase error less than half a period during the next consecutive phase comparison period. Naturally, this saves valuable time in the lock-acquisition procedure.