Abstract: A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

Abstract: A circuit is described for detecting a difference in phase and frequency between two incoming signals. Digital output signals are produced whose widths vary according to a degree of phase lead or phase lag of one signal with respect to the other. First sub-circuits are connected, one to each of the input signals to produce an output pulse of short duration, compared with a period of the incoming signal, at rising transitions of the associated input signal. Two resettable pulse detection circuits each have an output set to a first stable state when an active signal is received on a reset input and which change to a second stable state when a short duration pulse is received from one of the subcircuits on a pulse input. Further circuitry is connected such that when both outputs of the resettable pulse detection circuits are in the second stable state, an active reset signal is supplied to both resettable pulse detection circuits, to return both of their outputs to the first stable state.

Abstract: A high speed bit synchronizer is provided with a digital phase detector and a digital offset eliminating circuit. The output of the digital offset eliminating circuit is summed together with the output of the digital phase detector to compensate for the DC offset voltage generated by unsymmetrical digital data received at the input of the phase detector. Further, the phase error offset voltage produced at the output of the digital phase detector is linearized so that the lock point of the phase S-curve located on a linearized portion of a phase offset S-curve, thus, substantially eliminating all seeking and jitter that normally occurs at the lock point.

Abstract: A digital loss of lock detection (LLD) device for a phase looked loop (PLL) generates a locked frequency signal synchronized with a reference frequency signal. The LLD comprises first to fifth latching means for detecting when the reference clock failed high/low, when the locked clock failed high/low and when the reference clock is outside the tracking range of the PLL. The first to fifth latching means provide respectively a first to fifth error signals for each type of the above faults.

Abstract: A linear phase detector used with half-speed quadrature clock architecture is provided. The linear phase detector includes a first circuit receiving a data signal, a first half-speed quadrature clock signal and a second half-speed quadrature clock signal. The first circuit generates an adjusted data signal and a polarity representing signal of the first half-speed quadrature clock signal. A high speed phase detector is coupled to the first circuit for generating a linear phase correction signal.

Abstract: The present invention discloses a novel latching phase detector which eliminates prior art errors in phase detection due to DC and low frequency offsets present in reference and input signals. The invention also eliminates prior art errors in phase detection due to timing skews caused by unequal reference and input signal delay paths. The invention further eliminates the effects of logic element metastability. The invention comprises a reference signal differentiator and an input signal differentiator. Each differentiator has a corner frequency that is easily adjusted to block DC and low frequency offsets. The corner frequency can be adjusted to result in an n.pi./2 phase detector where 1.ltoreq.n.ltoreq.4. The invention also comprises an output latch that presents a delay path to the reference signal that is equal to the delay path presented to the input signal.

Abstract: In the present embodiment, digital phase detection of digital telecommunications signals is based on heterodyning. The frequency of two signals are scaled to different nominal values that are separated by a typically small but finite difference. The two frequencies are then mixed to generate a finite beat frequency. In mixing, phase is preserved and the finite beat frequency phase is in one-to-one correspondence with the signal phase. Phase detection is performed indirectly at the lower finite beat frequency with high resolution and greater ease than direct phase detection.

Abstract: A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: A method and system are provided for detecting and measuring a phase difference, linearly over a range of 360.degree., between the output signals from a primary stratum clock module (100) and a standby stratum clock module (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (.o slashed.2) enough to cancel the phase difference, and controlling a digital delay line (132) to shift the phase of the standby clock signal (.o slashed.2) accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module (100) to the standby stratum clock module (120), phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system.

Abstract: A phase synchronization circuit uses a phase comparator and adjustable delay lines that selectively delay a system clock timing signal applied to two integrated circuit chips. The phase comparator and delay lines compensate for propagation delays in each of the integrated circuit chip. The phase comparator receives bus clock signals of the two chips and generates two trigger signals for application to two counters. The counters count signals are applied to corresponding delay lines, which are clocked by a system clock. The delayed timing signals from the delay lines furnish timing signals to the corresponding integrated circuit chips. The count of the counter which corresponds to the integrated circuit chip having the smaller propagation delay is increased until the bus clock signals for the two integrated circuit chips are phase synchronized.

Abstract: A frequency and phase comparator has a first flip-flop and a second flip-flop. Logical calculation between the outputs of these flip-flops is performed by an AND circuit, and the first and second flip-flops are reset by the output of the logical calculation. The first and second flip-flops receive periodic signals at their clock terminals. When the periods of the output pulses of the first and second flip-flops are short, a circuit driven by the pulses sometimes cannot operate correctly. To prevent this, a pulse generating circuit is provided which receives a first periodic signal and a second periodic signal to generate a pulse signal of a predetermined width, and the pulse signal is added to the outputs of the first and second flip-flops.

Abstract: There is disclosed an integrated circuit including a phase detection circuit having an exclusive gate having first and second gate inputs for receiving first and second gate input signals. The exclusive gate provides at an output, a gate output signal that is the exclusive combination of the first and second gate input signals. A first switched resistance is coupled between a first voltage source and a common node. A second switched resistance, coupled between a second voltage source and the common node, receives the gate output signal of the exclusive gate to control the effective resistance thereof. The first and second resistances develop a signal at the common node. A comparator has a first input coupled to the common node and a second input coupled to a threshold value.

Abstract: A novel method and apparatus providing an all digital phase comparator of two binary signals which employs a type of cross correlation of two binary signals and provides a 2bit binary word uniquely representative of phase alignment. The method can be carried out using a pair of flip-flop (FF) circuits, each FF having a docking input and a data input, and where each FF has a delay in series with its data input.

Abstract: A phase-locked loop includes an input terminal (1) for receiving a binary signal, a phase comparator (3) having a first input (2) coupled to the input terminal (1), having a second input (4), and having an output (5) coupled to an input (9) of a control-signal-controlled oscillator (10) via a control-signal generator unit (7). An output (11) of the oscillator is coupled to the second input of the phase comparator. The phase comparator derives a first pulse (P.sub.1) and a second pulse (P.sub.2) in response to a signal transition from a first value to a second value in the binary signal applied to the first input and an oscillation signal applied to the second input, the first pulse having a pulse width which is a measure of the phase difference between the binary signal and the oscillation signal, and the second pulse having a pulse width proportional to 1/2.f.sub.o, where f.sub.o is the frequency of the oscillation signal.

Abstract: A phase-locked loop circuit includes a voltage-controlled oscillator, a pre-scaler, a main counter, a shift register, and a phase comparison section. The oscillation frequency of the voltage-controlled oscillator is controlled on the basis of phase different information. The pre-scaler frequency-divides an oscillation frequency output from the voltage-controlled oscillator by one of frequency division ratios of 1/j (j is a positive integer) and 1/(j+1) which is selected in accordance with an external control signal. The main counter frequency-divides a frequency division output from the pre-scaler by a frequency division ratio of n (n is a positive integer). The shift register generates .alpha. (.alpha. is an integer equal to or larger than two) time series pulse strings which are synchronized with the output from the pre-scaler and have phases sequentially delayed by one period on the basis of a frequency division output from the main counter.

Abstract: A comparator of phase between a digital signal and a clock signal adapted for the construction of a phase locked loop in integrated circuit form, that includes a first channel formed by a flip-flop and an exclusive OR gate, and a second channel formed by a second exclusive OR gate and a delay circuit whose delay is set to half the period of the clock signal. The first channel receives the digital signal and the clock signal and delivers a first detection signal of transition of the digital signal. The second channel receives only the digital signal and delivers a second detection signal of transition of the digital signal.

Abstract: A reset circuit for a phase detector in a phase-locked loop is described. A first set of input lines receives a first set of latched signals corresponding to a cycle of a reference signal applied to the phase detector of the phase-locked loop. Reset assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to generate a reset signal that is applied to an output node. The generated reset signal has a cycle duration corresponding to the reference signal cycle duration. Reset de-assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to de-assert the generated reset signal after a period of time corresponding to the reference signal cycle duration. Similar processing may be performed in relation to a second set of latched signals corresponding to a cycle of a feedback signal applied to the phase detector of the phase-locked loop.

Abstract: A single bit status register includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, a comparator for comparing the outputs of the flip-flop and the latch, and an output stage which provides an error output when the comparator determines that the outputs of the flip-flop and the latch are not the same. In this fashion, it is known when a "read" of the status register is invalid due to the presence of the error output. Preferably, the register also includes a reset disabling mechanism which prevents the input flip-flop from being reset until a valid read has occurred. A n-bit status register includes n register sections, where each register section includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, and a register section comparison mechanism for comparing the outputs of the flip-flop and the latch in that register section.

Abstract: A phase detector is described. The phase detector receives a data signal from an external circuit. The phase detector generates a first signal when a transition edge of the clock signal occurs after a transition edge of the data signal. The phase detector generates a second signal when the transition edge of the clock signal occurs before the transition edge of the data signal and generates a third signal when the data signal remains in a same signal state for at least two transition edges of a same type of the clock signal.

Abstract: A phase comparison circuit used in a phase locked loop circuit which realizes a stable phase locked loop circuit without changing the output frequency of a voltage-controlled oscillator, even if an input pulse is missing. The phase comparison circuit includes a circuit for generating a first pulse at each rising edge of an input signal, a circuit for generating a second pulse at each falling edge of the input signal, a circuit for generating a third pulse at each falling edge of a reference signal, a circuit for generating a first output signal from the first pulse and the second pulse, and a circuit for generating a second output signal from the first pulse and the third pulse. The output signals are not increased even if an input pulse is missing so that the operation of the phase locked loop circuit remains stable.

Abstract: An integrated circuit utilizing a symmetric phase detection circuit for detecting a phase relationship between a reference clock signal and a delayed clock signal. The integrated circuit described herein features a control block circuit coupled to receive the reference clock signal and an enable check signal. The control block circuit generates an enable signal which provides the present invention with the ability to detect the phase difference between signals having the same frequency or signals that differ in frequency by a rational factor. The control block circuit generates the enable signal in response to the enable check signal and the reference clock signal. The enable signal, the reference clock signal, and the delayed clock signal are coupled to the phase detection circuit. In response to the enable signal, the phase detection circuit then determines the phase relationship between the reference clock signal and delayed clock signal.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A phase comparing circuit includes a first device for generating a detection signal in response to a multi-level signal. The detection signal represents whether or not the multi-level signal is in a given level. A second device connected to the first device is operative for generating a first control signal in response to the detection signal generated by the first device and a clock signal. The first control signal represents a time interval between a leading edge of a pulse in the detection signal and a strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal. A third device connected to the first device is operative for generating a second control signal in response to the detection signal generated by the first device and the clock signal. The second control signal represents a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the detection signal.

Abstract: A circuit, indicating the first or last signal activated among n signals, includes flip-flops respectively associated with pairs of signals, a first signal of each pair being applied to a reset input of a flip-flop and a second signal of each pair being applied to a set input. Logic gates are respectively associated with each considered signal and are connected to indicate whether the considered signal is the first or the last activated signal when the flip-flops associated with all the pairs of signals including the considered signal are at respective suitable states once the first or last signal is activated.

Abstract: A fault tolerant computer according to the invention includes a processing unit including a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second, abbreviated system bus to receive read data from said first system bus. Coupled to said processing unit is an Input/Output device for interfacing to external devices. The processing unit includes a phase detector apparatus for aligning a clock of the processor unit to that of the Input/Output unit to facilitate data transfer. The phase detector apparatus includes a first means for providing a first clocking signal related to the clocking signal of the Input/Output unit, and a second means for providing a second clocking signal related to the clocking signal of the processor unit. The phase detector apparatus further includes means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

Abstract: A small and efficient control circuit for a compensated CMOS off-chip driver and a driver circuit incorporating the control circuit. The control circuit uses an exclusive OR gate as a phase detector to determine the phase difference between a system clock and a delayed version of the system clock. An RC filter smooths the output of the exclusive OR gate to produce a voltage proportional to the delay introduced in the CMOS circuitry by environmental and process variables. The voltage from the RC filter is used as a control voltage to control the effective channel width of the effective pull-down device of the off-chip driver circuit. An off-chip driver using the control circuit is used in the I/O unit of a CMOS integrated circuit chip.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: Any one of several improved devices capable of implementing microwave phase logic (MPL) operating at gigabits per second rates comprises either at least one of means performing the function of a multigate microwave-monolithic-integrated-circuit (MMIC) field-effect transistor (FET), or a pair of doubly-balanced mixers, in which each of the mixers includes an RF port, a local-oscillator (LO) port and an IF port, and the IF port of a first of the doubly-balanced mixers is directly connected to the IF port of a second of the doubly-balanced mixers.

Abstract: An object of the present invention is to provide an A/D conversion device capable of compensating for quantizing errors occurring as a result of variations in operating conditions and a physical quantity detection device using this A/D conversion device.

Abstract: A digital phase detector that stores four sequential digital samples in a shift register. The contents of the shift register is evaluated at one half the clock frequency which generated the digital samples. The digital phase detectors predicts what the value should be for each of the two middle samples in the shift register. The predicted value and the actual value of each middle are used to generated a correction signal. The correction signals for the two middle samples are then added to produce a total correction signal which is to be used in controlling the phase and frequency of the voltage controlled oscillator in the phase locked loop generating the clock that controls the generation of the digital samples.

Abstract: A phase angle difference between two alternating electrical signals is determined as a function of a ratio of a differential combination of two different numbers of pulse counts to an additive combination of the two different numbers of pulse counts, wherein the first of the two different numbers of pulse counts is obtained by counting a series of electric pulses generated by an electrical pulse generator in a time interval between an occurrence of zero value of the leading signal of the two alternating electrical signal and (i-1)th occurrence of zero value of the trailing signal of the two alternating electrical signals occurring after the occurrence of zero value of the leading signal, and the second of the two different numbers of pulse counts is obtained by counting the pulses in an time interval between an occurrence of zero value of the trailing signal and the (j)th occurrence of zero value of the leading signal occurring after the occurrence of zero value of the trailing signal, wherein (i) and (j) are

Abstract: A single bit status register includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, a comparator for comparing the outputs of the flip-flop and the latch, and an output stage which provides an error output when the comparator determines that the outputs of the flip-flop and the latch are not the same. In this fashion, it is known when a "read" of the status register is invalid due to the presence of the error output. Preferably, the register also includes a reset disabling mechanism which prevents the input flip-flop from being reset until a valid read has occurred. A n-bit status register includes n register sections, where each register section includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, and a register section comparison mechanism for comparing the outputs of the flip-flop and the latch in that register section.

Abstract: A method and apparatus for timing acquisition of partial response class IV Signaling is described. The invention uses an acquisition logic block to determine an output sequence that best matches a preamble pattern. The logic block analyzes current quantizer output X and the two previous decisions X.sub.n and X.sub.n-1. The logic uses these values to determine the next value X.sub.n+1 so that the best match occurs. The invention is implemented with OR gates, AND gates, and D flip-flops and can operate in acquiring mode or tracking mode.

Abstract: Phase of first and second signals is compared by producing an output signal in the event of a predetermined phase relationship between the first and second signals and clearing the output signal at a predetermined phase during the cycle of the second signal regardless of the state of the first signal.

Abstract: A phase detector is described. The phase detector receives a data signal from an external circuit. The phase detector generates a first signal when a transition edge of the dock signal occurs after a transition edge of the data signal. The phase detector generates a second signal when the transition edge of the dock signal occurs before the transition edge of the data signal and generates a third signal when the data signal remains in a same signal state for at least two transition edges of a same type of the dock signal.

Abstract: A semiconductor integrated circuit having a plurality of power source voltages in one chip and which comprises delaying means which accurately implements a predetermined delay time into a signal. An inverter circuit block receives at its input part an output from a NAND gate. An output from the inverter circuit block is coupled to a node of a phase comparing part through a switch. The output from the inverter circuit block is also coupled through another switch to an input part of another inverter circuit block whose output is coupled to the node of the phase comparing part through still another switch. A control signal is set at a L level if the phase comparing part is to operate at a first power source voltage and set at a H level if the phase comparing part is to operate at a second power source voltage which is larger than the first power source voltage.

Abstract: A system and method for estimating input phase for bit cells recovered from run length limited code where the bits cells have a nominal duration allows use of sampling rate as low as the nominal data rate in an all digital phase-locked loop. For the all digital phase-locked loop, a clock generates sample cells of a fixed duration. The sample cell phase contribution corresponding to a proportion of the fixed duration to the nominal duration is calculated and added to an accumulated phase value with each successive sample cell. For each sample cell, an input phase estimate is made from the accumulated phase value and timing information for any bit cell event occurring within the sample cell. Finally the input phase estimate information is used to adjust an accumulated phase value for the next sample cell.

Abstract: A signal processing circuit measures the phase difference between digitally formated reference tone and telephone line signals over a prescribed number of signal periods so as to provide to an attendant processor an average value of phase differential. The reference tone and line signals are conditioned as square wave signals, and applied to a first exclusive-OR circuit and to respective divide-by-two flip-flop circuits, which produce square wave signals having a frequency which is half the frequency of the conditioned square wave signals. The output of the first exclusive-OR circuit represents the half-cycle phase difference between the two sine waves. The full-cycle square wave signals are applied to a second exclusive-OR circuit, which produces a series of pulses, each representing a respective full-cycle phase difference between the reference and line sine waves.

Abstract: A phase difference measuring device includes a phase detector, a low-pass filter/voltage controlled oscillator, a reference signal selector for selecting either an internal reference signal or an external reference signal as a reference signal, a phase comparator for comparing an undertest signal with the selected reference signal and obtaining a phase difference between the two compared signal. The internal reference signal is selected when the undertest signal is a jittering signal, and the external reference signal is selected when the undertest signal is a wandering signal. The undertest signal, the selected reference signal, and a relatively high frequency clock signal from external are sent to the phase comparator and a phase difference between the undertest signal and the selected reference signal is counted by the relatively high frequency clock signal.

Abstract: A phase/frequency comparator includes: two inputs which respectively receive first and second logic signals; a first logic gate which is at an active state during a duration equal to the phase advance of the first signal with respect to the second signal; and a second logic gate which is at an active state during a duration equal to the phase advance of said second signal with respect to the first signal. The phase/frequency comparator also includes: a first switching element operated by the active state of the second gate to prevent transmission to the first gate a state liable to switch the first gate to its active state; and a second switching element operated by the active state of the first gate to prevent transmission to the second gate a state liable to switch the second gate to its active state.

Abstract: A phase-locked-loop (PLL) with stable phase discrimination includes a charge pump with a current source and current sink to control a VCO, and a phase discriminator to compare the VCO's signal to a stable reference signal for controlling the charge pump. The phase discriminator includes a resettable D-flipflop to provide the current source control signal and a resettable D-flipflop to provide the current sink control signal. The reset signal keeps both sink and source temporarily alive to avoid a dead zone region. The reset signal is produced under the combined control of the sink and source control signals and, in addition, of the reference signal to enhance stability.

Abstract: A digital phase comparator measures the phase difference of two signals (S1, S3) from a third signal (S2), and calculates the difference. The zero crossing of the two signals respectively sets two flip-flops (11, 12). If both flip-flops are set, they are simultaneously reset with a delay. Each set flip-flop enables a corresponding counter (13, 14). An evaluation unit averages the counter outputs at major intervals. The phase comparator can be incorporated into a phase-locked loop.

Abstract: A phase detecting system is provided for detecting when phase differences which occur between first and second clock pulses from a clock generator exceed acceptable tolerances, regardless of whether the first clock pulse leads the second clock pulse or the second clock pulse leads the first clock pulse. Two identical phase detectors are utilized each of which includes a phase detecting circuit, one group of signal delay elements that allow flip-flops in the phase detecting circuits time to set in order to detect the phase changes, and another group of signal delay elements coupled to the flip-flops which are set so the phase detecting circuit is capable of detecting the nominal phase delay times between the first and second clock pulses.

Abstract: A skew due to distribution of a clock inside a gate array is reduced. Phase comparators (14A), (14B) and (14C) are prepared in the peripheral portion of an internal circuit 71. The phase comparator (14C) is selected which is located nearest an element (77C) which receives an internal clock signal (65C) which is to be synchronized in terms of phase with an external clock signal (73). The selected phase comparator (14C) is connected to a charge pump circuit (16). Without forming a plurality of PLL circuits except for the phase comparators, the phase of any desired internal clock signal is synchronized with the phase of the external clock signal.

Abstract: A clocked digital signal processing system includes apparatus for unambiguously indicating the phase of an input signal relative to a reference clock signal. In particular, the disclosed apparatus reduces timing uncertainty between the reference clock, and the output signal of a phase detector representing the phase relationship between the input signal and the reference clock. A phase detector including a logic network provides plural comparison signals representing a phase relationship between the input and reference signals. The comparison signals are conveyed via first and second latch circuits, in respective groups, to a clocked downstream stage. The first and second latch circuits are clocked by different phases of the reference clock and provide outputs synchronous with the reference clock. The downstream stage responds to the reference clock for conveying output signals front the first and second latch circuits to an output at which the unambiguous indication appears.

Abstract: In one embodiment, a method of providing phase detection from a circuit having first and second inputs and at least one output is disclosed. The method includes a cyclical operation of four steps. The first step awaits the receipt at the first input of an input signal which at least meets the requirements of one of two given binary values. The second step awaits the receipt at the first input of an input signal which at least meets the requirements of the other of the two given binary values before providing an output signal of a first value at the output. The third step awaits the receipt at the second input of an input signal which at least meets the requirements of one of two given binary values. The fourth step awaits the receipt at the second input of an input signal which at least meets the requirements of the other of the two given binary values before changing the output signal at the output to a second value. The process then returns to the first step.