Abstract: Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.

Abstract: This document discusses, among other things, apparatus and methods for controlling a hysteresis range of a voltage comparator. In an example, an apparatus can include an amplifier having a temperature dependency, a comparator configured to receive first and second currents and to provide an output voltage indicative of a hysteretic comparison of the first and second input voltages, wherein a range of hysteresis of the apparatus is controlled over a range of temperatures. In an example, the amplifier can be configured to receive first and second input voltages and to provide the first and second currents.

Abstract: A temperature stable comparator circuit, comprised of: a branch C having a first end, a second end, a first type-1 device and first type-2 device, wherein the first type-1 device and the first type-2 device are connected to a node O; a branch B having a first end, a second end, a second type-1 device, a second type-2 device, and a resistor; and a branch A having a first end, a second end, a third type-2 device and a current-control device; wherein the first ends of the branch A, branch B, and branch C are commonly connected, and the second ends of the branch B and branch C are commonly connected.

Abstract: A temperature compensation circuit for generating a temperature compensating reference voltage (VREF) may include a Bandgap reference circuit configured to generate a Bandgap reference voltage (VBGR) that is substantially temperature independent and a proportional-to-absolute-temperature reference voltage (VPTAT) that varies substantially in proportion to absolute temperature. The circuit may also include an operational amplifier that is connected to the Bandgap reference circuit and that has an output on which VREF is based. The circuit may also include a feedback circuit that is connected to the operational amplifier and to the Bandgap reference circuit and that is configured so as to cause VREF to be substantially equal to VPTAT times a constant k1, minus VBGR times a constant k2.

Abstract: A low power servo-controlled single clock ramp generator (100) includes a fast switched comparator (102), charge pump (110) and voltage-to-current converter (120) connected to provide a feedback control mechanism under control of a pulse comparison clock signal (pulse_comp) and a reset pulse clock signal (rst_pulse) that are generated from a single input clock signal (clkin) so that there are well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal, thereby providing a ramp signal (Vramp_out) having a stable, frequency-independent amplitude that is not limited by the reference voltage.

Abstract: An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

Abstract: A temperature compensation circuit having satisfactory linearity, a trimming circuit including a plurality of temperature gradients, and an acceleration detector having a wide applicable temperature range. A plurality of resistor elements R1 to R4, R5 to R8, R21 to R24, R25 to R28 are connected in series between a power supply voltage line and a ground voltage line. Resistor elements R9 to R14 are connected in series between connection nodes N1 and N3. Resistor elements R29 to R34 are connected in series between connection nodes N2 and N4. The resistor elements R1, R2, R4, R5, R7 to R14, R24, R25 have negative temperature coefficients. The resistor elements R3, R6, R21 to R23, R26 to R34 have positive temperature coefficients. An output terminal NT5 connects a connection node of the resistor elements R13 and R14 and a connection node of the resistor elements R30 and R29.

Abstract: A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The driver includes plural partial drivers configured to output signals based on time constants established by corresponding plural time-delay networks associated therewith. The signal driver further includes a slew rate selector coupled to the plural time-delay networks and configured to provide a common signal thereto to cause the plural time-delay networks to achieve target time constants, the target time constants causing the output signals to be generated such that the signal driver achieves the selectable aggregate slew rate.

Abstract: Zero crossings for a non-symmetrical VIN may be determined by first amplifying and clipping VIN to create a non-symmetrical square wave whose zero crossings are those of VIN. A selected polarity edge of the non-symmetrical square wave may be taken as a 0° indicator and is used to create a fundamental sawtooth ramp of the same frequency and in phase with VIN. The fundamental sawtooth ramp starts at zero volts, linearly ramps to some peak and is AC coupled to a comparator whose other input is zero volts. That creates a square wave that is symmetrical as to its half-cycles, and whose every other edge is synchronous with the start of the fundamental sawtooth ramp, and whose intervening edges occur in the middle of the ramp. The intervening edge is detected and taken as a 180° indicator.

Abstract: A load control device includes a triangular wave generation portion which generates a triangular wave signal by charging/discharging a capacitor based on a constant current supplied from a constant current source, a load control portion which controls a load based on the triangular wave signal, and a temperature compensation element whose characteristic changes with a rise in temperature, which is provided to the constant current source.

Abstract: An on-chip temperature detection device includes: a bipolar type power transistor; a mirror transistor in which a collector current, which is proportional to a collector current of the power transistor, flows; a current detection section that detects the collector current of the mirror transistor; a voltage detection section that detects a voltage between a base and an emitter of the power transistor; and a calculation section that calculates a chip temperature of the power transistor, based upon the collector current of the mirror transistor detected by the current detection section, and upon the voltage between the base and the emitter of the power transistor detected by the voltage detection section.

Abstract: A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage. The forward junction voltage and the thermal voltages have respective thermal sensitivities that act oppositely to each other so that, when the forward junction voltage is combined with the thermal voltage to produce a reference voltage, the reference voltage is substantially insensitive to temperature. The forward junction voltage and the thermal voltage are combined to produce the reference voltage in a manner that avoids generating any voltage having a magnitude that is greater than the magnitude of the sum of the forward voltage and the thermal voltage.

Abstract: A temperature sensor apparatus comprises a pair of parallel circuit branches each including a pn semiconductor junction coupled in series to an impedance. The pn semiconductor junctions have different cross-sectional areas. An amplification stage comprises a CMOS input stage coupled respectively across each pn semiconductor junction and a FET transistor output stage (coupled to a load impedance) that generates an amplified output signal corresponding to the pn semiconductor junction temperature.

Abstract: A temperature detection circuit comprises an OP amp, a reference current generator, a temperature detection voltage generator, a comparator, and a band gap reference voltage generator. The OP amp receives a band gap reference voltage and a first voltage. The reference current generator generates the first voltage and a reference voltage in response to an output signal of the OP amp. The temperature detection voltage generator generates a temperature detection voltage in response to an ambient temperature and the output signal of the OP amp. The comparator compares the reference voltage with the temperature detection voltage to generate a temperature control signal. The band gap reference voltage generator generates the band gap reference voltage. Accordingly, the temperature detection circuit of the present invention can perform high or low temperature detection stably in supply voltage and temperature variations and thus protect the operation of the integrated circuit.

Abstract: An integrated circuit including an on-board system clock, the integrated circuit including a clock filter configured to determine a temperature of the integrated circuit and to alter an output of the system clock based on the temperature.

Abstract: A scannable asynchronous preset and/or clear flip-flop having latch circuits 27 and 30. Latch circuit 27 comprises an inverter 28 and a tristate NAND gate 29. Latch circuit 30 comprises an inverter 31 and a tristate NOR gate 32. When the CLK (clock input signal) and CLRZ (the inverse of the clear input signal) are both low, the output of the tristate NOR gate 32 is forced low. Thus the input of inverter 31 is low so that the output signal, Q, is forced low and the inverse output signal, QZ, is forced high. When CLK is high and CLRZ is low the output of tristate NAND gate 29 is forced high so that the input to inverter 28 is high and the input to inverter 31 is low, thereby forcing Q low and QZ high. Thus the outputs Q and QZ are forced low and high respectively when CLRZ is low, regardless of the state of the CLK input.

Abstract: A circuit for generating a ramped voltage having controlled maximum amplitude (e.g., for use in a switching controller), and a method for generating such a ramped voltage without use of a comparator. The ramped voltage is a voltage developed across a periodically charged and discharged capacitor, or optionally a level-shifted version of such voltage. Preferably, a ring oscillator generates a clock signal (without use of a comparator) for use in controlling the periodic charging and discharging of the capacitor, and a feedback loop generates a supplemental charging current for the capacitor in response to feedback indicative of the ramped output voltage.

Abstract: A compensation circuit adapted to receive an input signal for a circuit element to be compensated. The input signal is used as an address to a memory at which a compensated signal is stored. The stored compensated signal is output to the circuit element as the compensated signal therefor. In a specific implementation, the command input is received by a shift register. The shift register converts a serial input to a parallel output. The parallel output of the shift register is combined with the output of a temperature sensor to provide an address for the memory. The command input data includes an address to the particular circuit element to be compensated. The temperature data is used to select a particular page of memory and the remainder of the command input data is used to select data from that page for output as the compensated signal for the selected element. In the illustrative embodiment, the components compensated are automatic gain control amplifiers.

Abstract: A clock control circuit is provided to control the frequency of a microprocessor clock signal and includes a clock management unit which controls the frequency of a timing signal applied to a clock generator and distribution unit, which correspondingly supplies an internal clock signal to a CPU core of the microprocessor. A thermal sensor is integrated with the semiconductor die which forms the microprocessor circuit. An output signal from the thermal sensor is provided to a primary temperature indicator unit and to an auxiliary temperature indicator unit. The primary temperature indicator unit is configured to assert a primary indicator signal when the temperature of the semiconductor die has increased above a first threshold level referred to as the primary threshold level, and the auxiliary temperature indicator unit is configured to assert an auxiliary indicator signal when the temperature of the semiconductor die exceeds yet a second threshold level referred to as the auxiliary threshold level.

Abstract: A pneumatic stapler includes a housing having an elongated guiding passage for guiding a staple to be struck, a pneumatically operated stapling hammer for striking the staple located in the guiding passage and an elongated hollow staple magazine for connected separate staples. The magazine has a first end open into the guiding passage and a second end spaced from the first end along the elongation of the magazine. The staples are displaced along the magazine towards the first end thereof by air pressure supplied through a pneumatic nozzle connection located in the magazine between the first and second ends thereof. A spring pawl prevents movement of the staples located upstream of the nozzle connection towards the second end of the magazine.