Abstract: To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch.

Abstract: The present invention enables an apparatus or the like, which does not respond to a communication using a superposed signal, to be used in a system using the superposed signal.

Abstract: A system includes a switching power converter, including a first transistor having a first gate, a first drain, and a first source, the first drain adapted to be coupled to a power supply. The switching power converter also includes a second transistor having a second gate, a second drain, and a second source, the second gate coupled to a second gate driver, the second source adapted to be coupled to ground, and the second drain coupled to the first source. The switching power converter also includes a third transistor having a third gate, a third drain, and a third source, the third gate adapted to be coupled to a current source, the third source coupled to a resistor, and the third drain coupled to the first gate. The switching power converter includes a capacitor coupled to the first drain and adapted to be coupled to the current source.

Abstract: In various aspects, a method for operating a memory cell arrangement is provided, including: providing a set of supply voltages to one or more sets of memory cell drivers to write one or more memory cells of the memory cell arrangement; wherein providing the set of supply voltages includes: ramping a first supply voltage of the set of supply voltages to a first predefined output voltage level, and ramping a second supply voltage of the set of supply voltages to a second predefined output voltage level dependent upon the first supply voltage, the first predefined output voltage level and the second predefined output voltage level defining a first predefined ratio, wherein, during the ramping of the first supply voltage and of the second supply voltage, a first ratio of the first supply voltage to the second supply voltage is substantially equal to or less than the first predefined ratio.

Abstract: An embodiment of the present disclosure relates to a circuit of cyclic activation of an electronic function comprising a hysteresis comparator controlling the charge of a capacitive element powering the function.

Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

Abstract: A protection circuit is adapted to a switching-capacitor regulation circuit having a capacitor. The protection circuit comprises a current source, first and second switch circuits, and a control unit. First, the control unit turns on the second switch circuit to make a top end and a bottom end of the capacitor, and control the first switch circuit to make the current source no connect the capacitor, and then set a voltage of the top and the bottom to be a first preset voltage. Next, the control unit turns off the second switch circuit to disconnect the top end and the bottom end, and turn on the first switch circuit to flow current from the bottom end of the capacitor. When a voltage difference between the top end and the bottom end is equal to a preset initial voltage, the control unit control the first switch circuit to disconnect the current source and the capacitor; next, the control unit controls current flow in or out from the top of the capacitor based on the voltage on the top of the capacitor.

Abstract: The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents, and when the oscillating circuit is used to provide clock signals for the sensor, it can be integrated with a sensor signal processing circuit to realize the miniaturization and integration of the sen

Abstract: To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch.

Abstract: A circuit is disclosed that includes a capacitive element, a control circuit, and a first switch and a second switch. The capacitive element is configured to generate an output voltage at a terminal thereof. The control circuit is configured to generate a first control signal and a second control signal in response to a first temperature-dependent voltage, a second temperature-dependent voltage, and the output voltage. The first switch and the second switch are coupled to the capacitive element, and configured to be turned on or off in response to the first control signal and the second control signal respectively. The first switch and the second switch have different switching status from each other in a charge mode.

Abstract: The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal.

Abstract: Provided are devices having a ramp signal generator for adjusting a slope of a ramp signal by adjusting a current of a unit current circuit to adjust a step size. The ramp signal generator may include a unit current circuit including one or more current paths that allow a flow of an electrical current generated based on a ramp supply voltage, and a slope adjustment circuit configured to adjust a slope of a ramp signal by changing a current path of the electrical current flowing through the one or more current paths of the unit current circuit.

Abstract: A pulse simulation device comprises a controller for generating at least one signal simulating a pulse, at least one tactile feedback unit wherein the tactile feedback unit is driven by the controller to generate tactile response simulating a pulse, and a wearable attachment for holding the tactile feedback on an actor.

Abstract: A solid-state imaging device and a camera system are provided. The solid-state imaging device capable of performing an intermittent operation includes a pixel unit and a pixel signal readout unit for reading out a pixel signal from the pixel unit in units of a plurality of pixels for each column. The pixel signal readout circuit includes a plurality of comparators and a plurality of counters whose operations are controlled by outputs of the comparators. Each of the comparators includes an initializing switch for determining an operating point for each column at a start of row operation, and is configured so that an initialization signal to be applied to the initializing switch is controlled independently in parallel only a basic unit of the initialization signal used for a horizontal intermittent operation, and the initializing switch is held in an off-state at a start of non-operating row.

Abstract: An oscillator circuit includes a voltage controlled oscillator (VCO) configured to generate a clock signal having a clock period that is adjustable based on a control signal. The oscillator circuit includes a time to voltage converter configured to receive the clock signal and generate a compensation voltage potential that is proportional to the clock period and a zero temperature coefficient (ZTC) current. The oscillator circuit includes an amplifier configured to generate the control signal responsive to the compensation voltage potential and a temperature independent reference voltage potential. A method includes applying a control signal to a VCO, generating a clock signal having a clock period responsive to the control signal, generating a compensation voltage potential, and adjusting the clock period using the compensation voltage potential. A memory device includes the oscillator circuit.

Abstract: Relaxation oscillator and method for providing an output frequency. For example, the relaxation oscillator includes a reference generator, a capacitor, a first comparator, a second comparator, a latch, and a temperature compensation circuit. The reference generator is configured to generate a first bias current, a first bias voltage and a second bias voltage. The capacitor is configured to be charged by a charging current to generate a charged voltage, and the charging current is generated based on at least the first bias current. The first comparator is configured to compare the charged voltage and the first bias voltage to generate a first comparison result, and the second comparator is configured to compare the charged voltage and the second bias voltage to generate a second comparison result. The latch is configured to generate a clock signal based on at least the first comparison result and the second comparison result.

Abstract: Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

Abstract: Various techniques are provided to implement hysteresis control for programmable logic devices (PLDs). In one example, a PLD includes a hysteresis control circuit configured to generate a hysteresis control signal based on a core voltage and an input/output (I/O) voltage. The PLD further includes an I/O cell associated with an I/O fabric of the PLD and powered by the I/O voltage. The I/O cell includes a first buffer circuit configured to receive an input voltage and generate a first buffer voltage based on the input voltage. The I/O cell further includes a hysteresis generator configured to generate a hysteresis voltage based on the hysteresis control signal and the I/O voltage. The I/O cell further includes a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the hysteresis voltage. Related methods and systems are provided.

Abstract: Methods of operating a display driver integrated circuit (IC) are provided. A method of operating a display driver IC may include generating a first clock signal, and calculating a frequency of the first clock signal using a second clock signal. Moreover, the method may include generating an adjustment signal using the frequency of the first clock signal and a target frequency, and adjusting the frequency of the first clock signal using the adjustment signal. Related display driver ICs and portable electronic devices are also provided.

Abstract: A power system includes a first unit block having first resonant circuitry that receives power from a DC bus, a first controlled rectifier that provides a first portion of power to one or more loads at a first voltage level, and a first transformer coupled between the first resonant circuitry and the first controlled rectifier. A second unit block includes second resonant circuitry that receives power from the DC bus, a second controlled rectifier configured to provide a second portion of power to the one or more loads at a second voltage level, and a second transformer coupled between the resonant circuitry and the controlled rectifier. The first and second unit blocks are coupled in series to output a summation waveform.

Abstract: An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.

Abstract: A switching power converter is provided with a power-on-reset (POR) circuit that discharges essentially no current until a power supply voltage exceeds a POR threshold voltage.

Abstract: A digitally controlled ramp generator has a constant current source, a first controllable switch coupled between the constant current source and an output node, a capacitor coupled with the output node, a second controllable switch coupled with the output node, a constant current sink coupled with the second controllable switch, and a control unit. The control unit is configured in a first operating mode to select control signals for the first and second controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the second controllable switch wherein the control signals can be selected from the group of a time based control signal and a voltage based control signal. A variety of other control modes may be provided.

Abstract: An analog-to-digital converter includes a ramp signal generation unit suitable for decreasing a voltage range of a ramp signal in reverse proportion to a multiple of a gain and repeatedly generating the ramp signal by the multiple of the gain; a comparator suitable for repeatedly outputting a comparison signal by the multiple of the gain in response to the ramp signal; and a counter suitable for performing a counting operation in response to the comparison signal.

Abstract: A circuit includes a comparator unit and a switching network. The comparator unit is configured to receive a first voltage value, a second voltage value and a third voltage value of a voltage node, and to provide a control signal. The switching network includes the voltage node and is configured to operate in a first condition or in a second condition based on the control signal. Based on the first condition, the voltage node is configured to have a voltage value increase to the first voltage value. Based on a second condition, the voltage node is configured to have a voltage decrease to the second voltage.

Abstract: A multi-channel Class D audio amplifier is provided to substantially reduce channel-to-channel crosstalk by employing in each channel a local triangle ramp generator controlled by a single global digital timing signal. The noise critical timing/integrating capacitor for the triangle ramp generator resides locally in each channel and adjacent to the PWM comparator of that channel and referenced to the local ground of that channel. The amplifier can also include a duty cycle limitation circuit to limit output power availability depending on the impedance of any attached loads (speakers).

Abstract: A CMOS image sensor used as a solid-state image sensing device includes a pixel circuit for outputting a voltage of a level corresponding to the illuminance, and an A/D converter for converting an output voltage of the pixel circuit into a digital signal. The resolution on the low illuminance side is higher than the resolution on the high illuminance side in the A/D converter. Thus, the dynamic range can be increased and the operation speed can be increased, compared to the case in which the resolution is constant independent of the illuminance.

Abstract: A control module of constant on-time mode for a voltage converting device, includes a comparing unit, for generating a comparing signal according to an enhanced feedback voltage and a comparing voltage; a feedback voltage generating unit, for generating the enhanced feedback voltage according to a voltage difference between a first reference voltage and a feedback voltage corresponding to an output voltage of the voltage converting device; a comparing voltage generating unit, for generating the comparing voltage according to a second reference voltage and a control signal; and a adjusting unit, for acquiring an average voltage of the enhanced feedback voltage and adjusting the first reference voltage according to a voltage difference between the average voltage and the second reference voltage.

Abstract: According to one embodiment, in an AD conversion circuit of a single slope type, a counter is configured to count number of clocks, in a state where a potential level of a first slope voltage and a potential level of a second slope voltage concurrently change, until an output signal of either one of a first comparator and a second comparator is inverted. A reference counter is configured to constantly output a full count value. A generation circuit is configured to generate and output a digital value corresponding to a count value of the counter when an output signal of the first comparator is inverted, and to generate and output a digital value corresponding to a value obtained by subtracting a count value of the counter from the full count value of the reference counter when an output signal of the second comparator is inverted.

Abstract: A triangular wave generating circuit incorporates a capacitor, first, second, third, and fourth constant current sources, first and second switching units, a high/low level limiter, a clock generator, and a phase detecting unit. The first and second constant current sources charge the capacitor and the third and fourth constant current sources discharge the capacitor. The phase detecting unit compares an externally supplied clock signal with an internal clock signal and generates first and second phase signals base on a phase difference between the externally supplied clock signal and the internal clock signal. The second switching unit comprises a third switch and a fourth switch. The third switch couples the second constant current source to the capacitor in response to the first phase signal. The fourth switch couples the fourth constant current source to the capacitor in response to the second phase signal.

Abstract: Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit.

Abstract: System and method for generating one or more ramp signals. The method includes an oscillator configured to generate at least a clock signal, and a ramp signal generator configured to receive at least the clock signal and generate a first ramp signal. Additionally, the ramp signal generator is coupled to a first resistor including a first terminal and a second terminal. The first resistor is configured to receive an input voltage at the first terminal and is coupled to the ramp signal generator at the second terminal. Moreover, the first resistor is associated with a first resistance value. Also, the clock signal is associated with at least a predetermined frequency. The predetermined frequency does not change if the input voltage changes from a first magnitude to a second magnitude. The first magnitude is different from the second magnitude.

Abstract: A potentiostat includes a voltage regulator, a current mirror, a capacitor, a comparator, a current source, and a counter. The voltage regulator maintains a voltage on a working electrode of an electrochemical sensor. The current mirror develops a mirror current that mirrors an input current from the working electrode. The capacitor is alternately charged by the mirror current, causing the capacitor voltage to increase at a rate related to the current's magnitude, and discharged by a control current, causing the capacitor voltage to decrease. The comparator outputs a waveform that includes upward and downward transitions based on the variations of the capacitor voltage. The current source produces the control current based on the waveform. The counter counts the number of upward or downward transitions in the waveform during a predetermined sampling period to produce a digital output. The digital output is representative of the magnitude of the input current.

Abstract: Waveform generation circuits are provided. A waveform generation circuit includes a waveform generation block configured to generate a waveform signal corresponding to a driving control signal, and a control signal generation block configured to generate the driving control signal to compensate the waveform signal for an environmental factor affecting the waveform generation circuit.

Abstract: An oscillator circuit selectively charges and discharges a capacitor with currents having variable magnitudes. A trimming circuit functions to measure a half period of the oscillator signal. The measured half period is compared to a reference period to generate an error signal. The variable magnitudes of one or the other or both of the current for sourcing or sinking at the capacitor are adjusted in response to the error signal.

Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

Abstract: A ramp output control device includes a driver configured to receive at least two inputs from a microcontroller. The driver includes a time duration register configured to store a current clock count until a preset time duration is reached. The driver also includes a ramp output register configured to store a current output value at an output of the device. The driver also includes a calculation block configured to determine whether to increase the current output value at the output based on the at least two inputs.

Abstract: A sawtooth wave generating circuit that outputs a sawtooth wave signal after calibration and a switch mode power supply device including the sawtooth wave generating circuit is disclosed. The sawtooth wave generating circuit includes a capacitor, a calibration circuit, a charging circuit, discharging circuit and a control unit. The calibration circuit feedbacks a sawtooth wave signal, generates a plurality of voltage signals based on the sawtooth wave signal, and selects one of the voltage signals to generate a calibration output signal. Therefore, the sawtooth wave generating circuit generates a stable sawtooth wave signal regardless of operating conditions.

Abstract: A PWM duty cycle converter includes a PWM signal generator, a timing signal generator, a limit signal generator, and a duty cycle limiter. The PWM signal generator generates a first PWM signal by comparing a triangular carrier wave with a duty command from a signal source. The timing signal generator generates a timing signal synchronously with at least one of a maximum value and a minimum value of the amplitude of the carrier wave. The limit signal generator generates a limit signal in response to the timing signal. The limit signal sets at least one of an upper limit and a lower limit on a duty cycle of the first PWM signal. The duty cycle limiter combines the first PWM signal and the limit signal to output a second PWM signal having a limited duty cycle.

Abstract: The present invention relates to a circuit and method of generating a ramp compensation voltage as might be used in a switching regulator. The ramp compensation voltage comprises: a charging current generating circuit configured to receive a switching signal having a frequency of fs, a duty cycle of D and a period of Ts, the charging current generating circuit generating a charging current in direct proportion to f s ( 1 - D ) ? DTs ; and a voltage generating circuit for generating a quadratic ramp compensation voltage by means of the charging current. The resulting ramp compensation voltage enables the switching regulator to operate over a broad range of duty cycles. The generated ramp compensation voltage has an amplitude as low as possible, the generated compensation slope approximates to the target compensation slope as close as possible, and over compensation at low duty cycles is reduced as far as possible.

Abstract: A circuit includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined voltage level. A first stage set of capacitors is operatively coupled to the level-crossing detector. A ramp circuit is operatively coupled to the set of series-connected capacitors. A second stage set of capacitors is operatively coupled to the first stage set of capacitors and the ramp circuit. The ramp circuit includes a feedback capacitor and a preset switch to provide a linear ramp output.

Abstract: A method for generating a ramp comprises providing a voltage reference source, providing a summing amplifier, providing n switched capacitor elements coupled in parallel between the voltage reference source and the summing amplifier, and selectively activating a predetermined number of the switched capacitor elements to first store charge on each activated switched capacitor element and then to measure the sum of the charges on the activated capacitor switch elements in each of a fixed-integer number of time slots in a cyclical manner, the predetermined number being between 0 and n.

Abstract: A ramp generator circuit for generating sawtooth waveforms based on a clock signal may include an operational amplifier, a first switched capacitor device within a first feedback path of the operational amplifier, and a first plurality of switch devices within the first feedback path, whereby upon actuation of the first plurality of switches, the first switched capacitor generates first ramp waveforms during first alternate clock periods of the clock signal. The circuit may also include a second switched capacitor device within a second feedback path of the operational amplifier, and a second plurality of switch devices within the second feedback path, whereby upon actuation of the second plurality of switches, the second switched capacitor generates second ramp waveforms during second alternate clock periods of the clock signal. The first alternate clock periods of the clock are followed by an adjacent one of the second alternate clock periods of the clock.

Abstract: An image sensor includes a band gap reference unit configured to provide a reference voltage having a predetermined voltage level, a storage unit configured to store the reference voltage, a switch configured to selectively connect the storage unit to the band gap reference unit, and a ramp signal generation unit configured to receive an input voltage corresponding to the reference voltage stored in the storage unit and generate a ramp signal.

Abstract: A stair-step voltage ramp module includes a stair-step voltage ramp generator circuit including at least one clocked first digital to analog converter (DAC) configured to receive digital data signals (codes) and a first clock signal and provide a first stair-step voltage ramp waveform. A programmable gain operational amplifier (op amp) has an input coupled to receive the first stair-step voltage ramp waveform. A second DAC being a current output, multiplying DAC is positioned to provide a gain setting resistance for the op amp. The second DAC and op amp configuration can be changed to provide gain or attenuation, or both. The output of the op amp provides a stair-step voltage ramp output suitable for applications including testing analog to digital converters (ADCs) having 10 or more bits.

Abstract: Provided are a method and apparatus (receiver) of receiving and processing a radio signal in a transmitter-receiver environment. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.

Abstract: A triangular waveform generator includes a square waveform clock circuit and an integrating circuit. The integration circuit receives input from the square waveform clock circuit and generates a triangular waveform output. A feedback circuit is operatively connected to the integrating circuit to reduce the audio band noise content in the triangular waveform output. The feedback circuit acts as a DC balance without significant sacrifice in the linearity of the triangular waveform output.

Abstract: A buck-boost power converter includes a power stage to convert an input voltage to an output voltage, an error amplifier to generate an error signal according to a reference voltage and a feedback signal proportional to the output voltage, a ramp generator to provide two ramp signals, and two comparators to generate two control signals according to the error signal and the two ramp signals to drive the power stage. By using feed-forward technique, one of the two ramp signals has a peak varying with the input voltage and the other ramp signal has a valley varying with the input voltage, so that the power converter has fast line response.

Abstract: A ramp generator circuit, e.g. foreign analog-to-digital converter. The ramp generator circuit has first and second current sources that are maintained in the on condition whether they are being used or not. A switched capacitor connects to the current source in order to create a multi-slope ramp.

Abstract: The sawtooth wave generation circuit includes: a switch circuit configured to switch a connection state thereof between a first connection state, in which a current from a current source is flowed from a first terminal of the output capacitor to a second terminal of the output capacitor, and a second connection state, in which a current from the current source is flowed from the second terminal of the output capacitor to the first terminal of the output capacitor; a switch control circuit configured such that, in each connection state of the switch circuit, if an output voltage has reached a predetermined threshold which is set in relation to an intermediate voltage, the switch control circuit controls the switch circuit to switch the connection state to the other connection state at least during a part of a predetermined period thereafter.