Abstract: A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. A single synchronization step is sufficient, provided that the frequency of the input clock signal is stable. Further, only one delay line is required to implement the DLL circuit. Therefore, the DLL of the present invention is both quick to “lock in” a clock signal and efficient in the use of hardware resources. Further, the present DLL is very accurate, because the same delay line is used to calculate the necessary additional delay and to generate the output clock signal.

Abstract: This present invention discloses a circuit for generating a delay signal, which includes a first delay line for generating a first delay signal, a second delay line for generating a second delay signal, a delay unit for generating an internal delay signal, a first phase detector for generating a first control signal, a second phase detector for generating a second control signal. There's a delay line monitor for generating the first delay control signal and the second delay control signal, and a DTC delay unit for generating the delay signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal that ramps between a first and second frequency in response to (i) a first control signal, (ii) a second control signal, and (iii) a first reference signal. The second circuit may be configured to generate the first and second control signals in response to a third control signal having a third frequency. The third frequency may reduce electromagnetic interference generated by the first circuit.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: A system to avoid unstable data transfer between digital systems. The present invention includes a system that enables digital systems to communicate while avoiding unstable data transfer, which can result in a loss of data or signal distortion. For instance, the present invention includes a system that enables detection of potentially unstable operating conditions for a digital receiver device during its reception of clock and digital data signals from a digital transmitter device. One embodiment of the present invention monitors the received clock and digital data signals in order to detect any potential violations of the internal input timing requirement of the digital receiver device. If any potential violations of the input timing requirement are detected, the present invention invokes measures to eliminate them by manipulating the phase of the clock signal utilized internally by the digital receiver device to sample the received digital data signals.

Abstract: A digital controlled oscillator (DCO) of a digital phase lock loop (PLL) is disclosed, wherein a fractional DCO structure is employed to provide the required target clock for comparing with the generated output clock. Comparison results of phase differences then enable a K-counter loop filter for changing its stored value. A control logic circuit is enabled to control a tapped-delay line for adjusting the currently output 'clock to coincide the requirement of the target clock when the stored value increases/decreases to K/−K. Additionally, signals from all-digital counter filter can be input to the fractional DCO structure to calibrate the frequency of the target clock according to environment without additional circuits.

Abstract: A delay locked loop (DLL) circuit (10) having an internal clock signal (D3) with positive and negative clock edges locked with an externally applied clock signal (D1) is provided. The DLL circuit (10) can include first phase decision circuit (1), a second phase decision circuit (2), an arbitrary phase generator circuit (3), and a variable pulse width circuit (4). First phase decision circuit (1) may receive external clock signal (D1) and internal clock signal (D3) and may generate a phase decision signal (D4) that may indicate whether a first edge of internal clock signal (D3) is to be sped-up or delayed. Arbitrary phase generator circuit (3) may provide a phase shifted signal based on phase decision signal (D4). Second phase decision circuit (2) may receive external clock signal (D1) and internal clock signal (D3) and may generate a phase decision signal (D5) that may indicate whether a second edge of internal clock signal (D3) is to be sped-up or delayed.

Abstract: The lock detector circuit for a phase-locked loop has two counters and a comparator, to which the counter readings of the two counters are fed. The lock detector circuit is symmetric and has two comparators in which the counter readings of the counters are checked separately in each case. If the difference between the counter readings exceeds a predetermined threshold value in one of the comparators, then the phase-locked loop is immediately set to the non-locked state and the counter readings are reset to zero. Frequency differences are detected immediately in the novel lock detector circuit, without a time delay and independently of the relative position of the reference edges of the signals to be compared. The phase-locked loop is thus quickly and reliably set to a locked or non-locked state. Furthermore, the functioning of the lock detector circuit is preserved when one of the two clock signals fails to appear, for example in the event of a crystal fault.

Abstract: An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured generate a first output signal having a first data rate and in response to (i) an input signal having a second data rate and (ii) a clock signal having the second data rate. The second circuit may be configured to generate a second output signal having a third data rate in response to (i) a divided version of the input signal and (ii) the clock signal. The logic circuit may be configured to generate the clock signal in response to (i) the first output signal and (ii) the second output signal.

Abstract: In a synchronous circuit constructed with a sequence circuit, for reproduce a clock signal synchronized with a synchronizing signal of such as television signal, an influence of variation of a d.c. component superposed on an edge of the synchronizing signal is reduced by obtaining phase errors at a falling edge and a rising edge of the synchronizing signal, arithmetically operating the phase errors and feeding back a result of the operation of the phase errors to a PLL. An influence of pseudo synchronizing signal is restricted by updating a phase error signal or holding a previous value according to the result of count of operation clocks during the synchronizing signal period.

Abstract: A frequency generation device (100) comprises a cascade of two phase-locked loops (104 and 108). The first PLL (104) is a frequency synthesizer while the second PLL, or offset loop (108), comprises a phase detector (208 or 306), loop filter (210 or 310), VCO (212 or 312) and a divider with near-unity modulus (204 or 308). In the case of a negative offset design, the near-unity divider (204) is placed in the offset loop feedback path. In a positive offset design, the near-unity divider (308) is placed in the path between the synthesizer VCO and the offset loop phase detector. Unlike existing art, there is no offset signal input to the second or offset loop (108).

Abstract: A built-in-self-test circuit aids in testing a phase locked loop circuit. The phased locked loop has a plurality of frequency multipliers. The built-in-self-test circuit includes a frequency divider and a multiplexer. The frequency divider has a plurality of divide-by-counters. For each frequency multiplier within the plurality of frequency multipliers there is a corresponding divide-by-counter. A ratio of a multiplier for each frequency multiplier to a divider of its corresponding divide-by-counter is a constant for all frequency multipliers and corresponding divide-by-counters. When a frequency multiplier within the plurality of frequency multipliers is selected, the multiplexer selects its corresponding divide-by-counter to produce a test output clock.

Abstract: A frequency multiplier is provided that increases operational stability by using a Delay Locked Loop (DLL). The frequency multiplier includes a phase detector for detecting a phase difference between an input signal and a feed-back signal, a loop filter for outputting a control signal based on the phase difference detected by the phase detector and a voltage-controlled delay unit for varying a delay ratio of the input signal and outputting divided signals in accordance with the control signal from the loop filter. A first SR flip-flop receives a pair of earlier output signals that are divided into 1/4 and 2/4 period signals from the voltage-controlled delay unit and outputs a first duty cycle signal. A second SR flip-flop receives a pair of later output signals that are divided into 3/4 and 4/4 period signals from the voltage-controlled delay unit and outputs a second duty signal.

Abstract: A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase locked loop (PLL) circuit in another implementation. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit generates a synchronized clock signal that is distributed throughout the programmable integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. The clock synchronization circuit improves the overall performance of the programmable logic integrated circuit.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: The present invention is directed to an improved PLL which produces an output signal that is in-phase with a reference clock input despite switching of the reference clock. A quadrature signal is generated using a quadrature decoder having a counter, a state decoder and a flip flop. A local oscillator having a local clock output having a frequency which is a multiple of the reference clock frequency is provided. The local clock output is divided down with a binary counter to match the reference signal frequency. The counter state is decoded using an AND in combination with a flip flop. The divided clock output is then re-synchronized with the reference clock using the local clock output coupled to the clock input of the flip flop. The output of the flip flop is an quadrature copy of the reference clock, and this quadrature signal is fed back to the phase detector.

Abstract: A high-speed data receiving circuit allowing correct and reliable data reception without the need for adjusting delays in circuits and interconnections is disclosed. A sampling circuit samples received data according to first, second, and third clock signals to produce first, second, and third streams of data. The first, second, and third clock signals sequentially have a predetermined phase difference between adjacent ones. A clock generator generates the first, second, and third clock signals having phases determined depending on a clock selection signal obtained by comparing the first, second, and third streams of data. The second clock signal is selected as an output clock signal and the second stream of data corresponding to said second clock signal is selected as an output data of the high-speed data receiving circuit.

Abstract: A device for the generation of a drive signal phase-shifted with respect to an external synchronization signal includes a first digital phase-locked loop to give a reference signal, servo-linked to the external synchronization signal by a current phase among N phases of a high frequency signal. The device includes a second digital phase-locked loop including a measuring circuit to measure the position of an active edge of the drive signal or a derived signal that is delayed with respect to an active edge of the reference signal. The second phase-locked loop also includes a circuit to compute the phase shift to be made and a phase-shift circuit. The measurement circuit includes a circuit for the rough measurement of the position, controlled by a fixed phase of the high frequency signal independent of the present phase of locking in the first loop. The digital computation circuit accounts for this shift between the fixed phase and the present phase.

Abstract: A phase locked loop is provided that includes a phase comparator for receiving an incoming signal with which is desired to lock. A loop filter processes a current error signal. An integrator adjusts the output to account for the error. The phase comparator, loop filter and integrator are formed from logic elements.

Abstract: An output of a flip flop (21) at a first stage is connected to a D-input of a flip flop (22) at a second stage, and an inverted-output of the flip flop (21) is connected to a D-input of a flip flop (23) at a third stage. A reference clock BCK is supplied to the D-input of the flip flop (21), and an oscillation clock OCK is inputted to each T-input of the respective flip flops (21) to (23). An XOR of the reference clock BCK and an output signal Q1 of the flip flop (21), and a logical product of an output signal Q2 of the flip flop (22) and an output signal Q3 of the flip flop (23) are used as a first comparison output PDU and a second comparison output PDD, respectively. With this arrangement, phase comparison can be achieved using a clock of any duty ratio.

Abstract: A phase-locked loop (PPL) utilizing a RAM is disclosed. The RAM is provided to store a reference clock and a clock to be controlled. The PLL further comprises a voltage-controlled oscillator section controls a phase of the clock to be controlled. The PLL further comprises a controller for retrieving, from the RAM, data of said reference clock and said clock to be controlled. The controller determines a phase difference between said reference clock and said clock to be controlled. Additionally, the controller generating a control signal so as to reduce said phase difference and applying said control signal to said voltage-controlled oscillator section.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal that ramps between a first and second frequency in response to (i) a first control signal, (ii) a second control signal, and (iii) a first reference signal. The second circuit may be configured to generate the first and second control signals in response to a third control signal having a third frequency. The third frequency may reduce electromagnetic interference generated by the first circuit.

Abstract: A system and method of stretching setup and hold times for input signals into synchronous digital circuitry.

Abstract: A clock/data recovery device employs a phase-locked loop that supplies a single clock signal and a control voltage signal to at least one clock/data recovery circuit. The clock/data recovery circuit has a voltage-controlled delay line or direct phase controlled voltage-controlled oscillator that generates a multiple-phase clock signal, which is used to recover a clock signal and data from a received data signal. The voltage-controlled delay line or direct phase controlled vottage-controlled oscillator has a cascade or ring of voltage controlled logic gates, with propagation delays controlled by the control voltage signal from the phase-locked loop, and additional logic gates that supply the clock signal from the phase-locked loop to a selectable one of the voltage-controlled logic gates.

Abstract: A frequency divider circuit, and a digital PLL circuit including the same, which can suppress jitter occurring in an output signal, including a first circuit module which drives D-FFs connected in series using an input signal as a reference clock signal and divides the input signal by a frequency division ratio selected by a frequency division ratio determining signal to produce a first divided signal; a second circuit module which drives D-FFs connected in series using the first divided signal as a reference clock signal and divides the first divided signal by a frequency division ratio corresponding to the number of D-FFs connected in series to produce an output signal; and an OR circuit which produces a frequency division ratio determining signal based on the outputs of the D-FFs of the second circuit module and a frequency division ratio selecting signal.

Abstract: A phase-locked loop includes a phase detector, a charge pump, a resistor-less loop filter and a voltage-controlled oscillator ("VCO"). The phase detector has a reference input, a feedback input, and a charge control output. The charge pump is coupled to the charge control output, and the resistor-less loop filter is coupled to the charge pump. The VCO has a control voltage input coupled to the resistor-less loop filter, a clock output coupled to the feedback input and a plurality of delay elements which are coupled together in series to form a ring oscillator. Each delay element includes a delay element output. A MOSFET gate oxide capacitance is coupled between each delay element output and the charge control output.

Abstract: The invention relates to methods and apparatus for synchronizing a local data clock with timing information from received data, during a fraction of a frame period. The apparatus includes a transition detect unit, a digital phase comparator, a phase regulator, and a control unit, for detecting the bit transitions of received data, determining the phase difference between timing information and a local data clock, advancing or retarding the local data clock, and enabling and disabling the synchronization in accordance with a predetermined rate.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: Compensating for phase nonalignment between VCO frequency divider and referenced frequency signal in a fractional-N PLL is provided by compensation implemented by a variable charge pump system. Phase comparator logic is configured to turn ON some of the charge pumps of the charge pump system early and the rest of the charge pumps later. This process effects an equivalent charge being turned ON at the exact point in time for properly compensating for the fractional charge.

Abstract: A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock.

Abstract: A PLL (phase locked loop) for recovering a clock preventing a DC value of an output voltage of a phase detector from being deviated in one-sided direction and maintaining a center frequency of a VCO, to thereby minimize the occurrence of timing errors, in the case where the period of a reference input signal to the phase detector is irregular and a part of a pulse column of the signal is omitted, in performing a clock recovery operation in a digital magnetic recording equipment or a digital communication system.

Abstract: A phase comparator compares phase of a clock signal and a generated comparison clock signal based upon rising edges. The output of the phase comparator may include a series of short up (U) pulses or down (D) pulses, depending whether the phase of the comparison clock is leading or lagging the clock. Up and down pulses U and D control an up/down shift register which in turn compensates phase difference by inserting or removing additional discrete delay elements in a variable delay line. Based upon delay signals generated by the variable delay line, a double frequency clock generator generates a 2.times. clock signal. The 2.times. clock signal is divided by 2 in a divider to supply the phase comparator with the generated comparison clock signal. The feedback scheme helps the digital delay lock loop of stabilize after a few clock cycles without additional external control.

Abstract: A digital signal reproducing circuit which enables precise measurement of a phase difference and jitter components of reproduction signals while realizing miniaturization of the circuit is disclosed. The digital signal reproducing circuit has a phase comparator for detecting a phase difference by using sampled values before and after an edge portion of a reproduction signal from an optical disc outputted from an A/D converter, and a jitter measuring section for detecting a jitter detection signal on the basis of unevenness of the phase difference obtained by the phase comparator.

Abstract: A correction circuit for controlling a correction required circuit includes an oscillator circuit, and a logic circuit which counts an oscillation frequency of the oscillator circuit and thus produces a control signal which causes the oscillator circuit to oscillate at a constant frequency. The control signal changes element values of elements of the oscillator circuit and the correction required circuit so that characteristics of the oscillator circuit and the correction required circuit can be controlled.

Abstract: An output clock signal is generated from a selected input clock signal using a phase-locked loop (PLL). The output clock signal is used to detect failures in the selected input clock signal. If a failure is detected, a backup input clock signal is used to generate the output clock signal. In one embodiment, a clock detector has a counter that is initialized based on the selected input clock signal and incremented based on the output clock signal. The clock detector detects a failure in the selected input clock signal if (1) the counter is reset too early or too late, as determined by the counter value, or (2) the signal level in the selected input clock signal does not change within a specified time period.

Abstract: A phase-locked loop circuit is constituted in such a manner that a delayed signal created by causing an input signal to loop through a delay stage a plurality of times is compared in terms of phase with the input signal, and an amount of delay in the delay stage is controlled in accordance with the comparison result of the delayed signal and the input signal. Therefore, the circuit size can be reduced with a reduced number of delay units constituting the delay stage.

Abstract: A phase locked loop (PLL) circuit performs a frequency pull-in operation with a simple structure. The PLL circuit has an oscillating part which oscillates at a frequency corresponding to a control input signal and a phase comparing part which detects a phase difference between an oscillation output signal of said oscillator and an input frequency signal and produces an error signal responsive to a detection value. The PLL circuit further includes a forcible pull-in part which adds values of the error signal and a forcible pull-in signal, and provides a signal based on a result of addition as the control input signal. The forcible pull-in circuit includes a reference value generating circuit which supplies a reference value determining a unit change width of an oscillation signal of the oscillating part, and a computing part which computes a value of the forcible pull-in signal based on the reference value.

Abstract: In a digital PLL circuit, a DCO 3a comprising a full adder 33 and a delay circuit 34 accumulate a frequency control data N, to generate digital phase data ACC which periodically changes at a rate corresponding to the frequency control data N, a latch circuit 11 latches the digital phase data ACC with the aid of an input digital signal .phi..sub.in, and outputs it as a digital phase difference signal PC, and a loop filter 2 removes components in an unwanted frequency band from the digital phase difference signal PC, to form the frequency control data which is applied to the digital control oscillator means. In the digital PLL circuit, the digital phase data ACC itself, being synchronized in phase with the input digital signal .phi..sub.in, is periodically changed.

Abstract: A method of achieving line-to-line synchronization having a high degree of synchronization accuracy. Synchronization is performed by a specific high-speed block of logic which signals the beginning of scans to a PELCLK-based logic at pel boundaries, and provides sub-pel shifting as it passes data between the pel generation logic and a laser control signal. The synchronization error is made as small as propagation delays through a single multiplexer element. Such delays can be controlled to values less than 1/2 ns. The need to stop and restart the clocks is eliminated. All complex pel generation logic is clocked with the relatively low frequency PELCLK without regard to the synchronization task.

Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock.

Abstract: A chip-to-chip Cycle Alignment Circuit is implemented on the CP chip with a phased lock loop so that a chip knows what is the cycle of a connected chip. Once the PLL is locked, the timing relationship is developed between a reference oscillator and the 3.5 ns on-chip clock which clocks three latches (latch 1,2,3). The Cycle Alignment Circuit has a first part for a rising edge detecting clock chopper and the second part for a self resetting toggle latch. The rising edge detecting clock chopper works by detecting the reference oscillator's rising edge after it has gone through a small delay. The purpose of this delay is to ensure that a latch 1 detects the rising edge on the second 3.5 ns cycle after the reference oscillator rises. A latch 2 is then used to generate a one (3.5 ns) cycle pulse at point that starts on the second 3.5 ns cycle and ends on the third 3.5 ns cycle. The pulse that is produced at that point forces a latch 3 to be reset to a 1 at the beginning of cycle 3.

Abstract: The present invention is a clock generator circuit using semiconductor integrated circuits and which has an input logic circuit to which an external clock signal is supplied; a delaying element chain in which a plurality of delay elements connected to the input logic circuit are serially connected together; a plurality of delay element selectors connected to each of the plurality of delay elements, respectively; a loop closing circuit connected to the delay element connected to a specific delay element selector which to a state indicating a selected status and to the input logic circuit, for forming a closed loop between the delay element chain and the input logic circuit; and an external output connected to the input logic circuit.

Abstract: A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.

Abstract: A method and phase locked loop for generating an eight-to-fourteen (EFM) data restoring clock signal. A frequency detector detects the number of clock pulses input during a pulse width of the EFM data signal, compares the detected number with predetermined maximum and minimum values, and outputs a signal indicative of the resulting comparison value. A voltage controlled oscillator varies an oscillating frequency in response to a DC control signal and outputs the clock pulses corresponding to the oscillating frequency. A programmable counter frequency-divides the clock pulses generated by the voltage controlled oscillator in response to a predetermined speed multiple and outputs the frequency-divided clock pulses. A phase detector detects a phase difference between the EFM data signal and the clock pulses generated by the programmable counter and outputs a signal indicative of the phase difference. A mixer mixes the output of the phase detector with the output of the frequency detector.

Abstract: To provide a PLL circuit with little jitter and a minimum frequency drawing time, a PLL circuit comprises: a phase comparator for generating an up-down signal, which is turned to logic HIGH when a reference clock signal is phase-advanced to an output clock signal and a phase lock signal, indicating synchronization of the output clock signal to the reference clock signal; a timing signal generator for generating a timing signal when the phase lock signal is generated for a certain period after said timing signal generator is initialized with a reset signal; an up-down counter for generating a count value which is incremented when the up-down signal is at logic HIGH and decremented when the up-down signal is at logic LOW according to each pulse of a count clock, memorizing the count value in a nonvolatile memory when controlled by the timing signal, and outputting the memorized count value when initialized by the reset signal; a D/A converter for outputting a control voltage in proportion to the count value; an

Abstract: A phase lock detector circuit is disclosed that generates delayed versions of both a reference clock signal and a synthesized clock signal. From the delayed signals, first and second control signals that are pulses are generated. The pulses are passed through respective delays of predetermined durations and then clocked into respective shift registers by the latched signal of the opposite input. The shift register outputs are logically combined and shifted into a third shift register. Outputs from the third shift register are logically combined to ascertain whether a phase-lock loop is phase lock. The lock detector circuit may include a lock-out circuit to disable the phase lock detector circuit upon detecting phase lock.

Abstract: A D flip-flop latches a reference clock signal in response to an output signal fed back from an output circuit. A pulse generating circuit generates a pulse in response to the output signal fedback from the output circuit. From the latched signal and the pulse generated by the pulse generating circuit, a count pulse is generated. The count pulse is output to an up/down counter. Based on the counting result of the up/down counter, a digital-to-analog conversion circuit generates a delay control signal. Using this delay control signal, the delay circuit synchronizes its output signal with the reference clock signal. It is possible to synchronize the output data signal with the reference clock signal regardless of variations in the reference clock signal, source voltage, and ambient temperature.

Abstract: A phase detector provides a digital output having a linear relationship to the phase difference between a reference signal and an applied input signal. The phase detector counts the number of cycles of the reference signal within a time interval determined by the difference in arrival times of corresponding amplitude transitions of the reference signal and the input signal. A digital output representing the number of counted cycles is produced. A dither generator adds random time variation to the time interval over which the reference signal cycles are counted to introduce a corresponding random variation in the digital output.

Abstract: A system is provided for generating an accurate and stable output clock signal of a desired output frequency in response to a system clock signal having a system clock period. The system uses an accurate and stable reference clock signal. The system comprises a measuring circuit and a ratio counter. The measuring circuit receives and processes the system clock signal and produces a measurement, referred to as the system clock measurement, that is indicative of the system clock period. The ratio counter receives the system clock signal and the system clock measurement and generates the output clock signal. The system is resistant to noise in the output clock signal caused by asynchronicity between the system clock signal and the reference clock signal. The system is resistant because it employs at least one of a lock-on unit and a synchronizing controller in operating the clock measuring circuit.

Abstract: A zero-delay buffer circuit includes a modified phase-locked loop (PLL) circuit configured to minimize clock skew among data output buffers of modules within a high-speed network switch system. Each module includes an application-specific integrated circuit (ASIC) chip that contains the modified PLL circuit; circuitry inserted within a feedback loop of the PLL is representative of a clock distribution tree that is common to the output buffers of the chip. The absolute delay of that tree typically differs among the ASICs because of process, voltage and temperature variations within the system. The circuitry inserted within the feedback loop effectively compensates for the absolute delay of the common distribution tree circuit components.