Abstract: Various embodiments for providing a data transfer and management system are described herein. An embodiment operates by determining that data of a column is stored in a column loadable format in which all of the data of the column is moved from the disk storage location to a memory responsive to a data request. A data vector that identifies a plurality of value IDs corresponding to at least a subset of the plurality of rows of the column, is identified. A page format that provides that a portion of the data of the column across a subset of the plurality of rows is moved from the second disk storage location into the memory responsive to the data request is determined. The entries of the data vector are requested, converted from column loadable format into the page persistent format, and stored across one or more memory pages.

Abstract: An apparatus includes a control clock generation circuit configured to generate a first toggling reference clock from a first internal clock and generate a second toggling reference clock from a first inverted internal clock, when a read operation is performed. The apparatus also includes a strobe signal generation circuit configured to generate a data strobe signal whose level transitions during a toggling period in synchronization with the first and second toggling reference clocks.

Abstract: Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.

Abstract: A circuit for generating at least two rectangular signals with adjustable phase shift, comprises a frequency divider circuit that receives a clock signal as input and provides a signal as output, at least two comparators that receive, respectively, a first threshold voltage and at least a second threshold voltage at one input, and a ramp signal, synchronized with the clock signal, at a second input, the at least two threshold voltages allowing the value of the phase shift between the at least two rectangular signals to be adjusted, and at least two D-type flip-flops that receive, respectively, the output signal from the first comparator and the output signal from the second comparator at their clock inputs, and the output signal from the frequency divider circuit at their D-input.

Abstract: A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.

Abstract: A clock transfer circuit receives input data synchronized with a first clock, and outputs, as output data, data synchronized with a second clock having a frequency different from that of the first clock. A write address controller is operating according to the first clock, and provides a write address to a memory. A read address controller is operating according to the second clock, and provides a read address to the memory. A cycle comparator compares the cycle of a predetermined event between the input data and the output data. Based on such a comparison result, the clock adjuster adjusts the frequency of the second clock.

Abstract: A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.

Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.

Abstract: A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.

Abstract: A clock signal from a first electronic subsystem is distributed to a second electronic subsystem. The second electronic subsystem is remote from the first electronic subsystem and coupled to the first electronic subsystem by a bidirectional signal path. A first clock signal is generated on the first electronic subsystem and a training signal is generated on the first electronic subsystem clocked by the first clock signal. The training signal is sent on the bidirectional signal path on a round trip to the second electronic subsystem and back to the first electronic subsystem. A phase of the training signal is adjusted symmetrically on the way to the second electronic subsystem in a first phase adjuster and on the way back to the first electronic subsystem in a second phase adjuster until the measured time for the round trip is equal to an even number of clock cycles.

Abstract: A clock signal from a first electronic subsystem is distributed to a second electronic subsystem. The second electronic subsystem is remote from the first electronic subsystem and coupled to the first electronic subsystem by a bidirectional signal path. A first clock signal is generated on the first electronic subsystem and a training signal is generated on the first electronic subsystem clocked by the first clock signal. The training signal is sent on the bidirectional signal path on a round trip to the second electronic subsystem and back to the first electronic subsystem. A phase of the training signal is adjusted symmetrically on the way to the second electronic subsystem in a first phase adjuster and on the way back to the first electronic subsystem in a second phase adjuster until the measured time for the round trip is equal to an even number of clock cycles.

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract: The ability of clock and data recovery (“CDR”) circuitry on an integrated circuit (“IC”) to handle jitter in a serial data input signal can be tested by using transmitter circuitry on the IC to produce a serial data output signal whose time base has been subjected to modulation. Loop-back circuitry on the IC may be used to apply the serial data output signal to the CDR circuitry as the serial data input signal of the CDR circuitry. Modulation circuitry on the IC may be used to cause the above modulation of the time base of the serial data output signal.

Abstract: A PLL circuit comprises a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage controlled oscillator (VCO), a frequency divider (FD) and a reset module. The PFD receives a first and a second input signals, and outputs a first and a second adjustment parameters according to phase and frequency difference between the first and the second input signal. The CP is coupled to the PFD, generates a current according to the first and the second adjustment parameters. The LPF is coupled to the CP, and generates a voltage according to the current. The VCO is coupled to the LPF, and generates an oscillation frequency according to the voltage. The FD receives and divides the oscillation frequency, and generates the second input signal. The reset module generates a reset signal to feed to the FD, wherein the reset module receives the first signal.

Abstract: Synchronization of oscillators based on anharmonic nanoelectromechanical resonators. Experimental implimentation allows for unprecedented observation and control of parameters governing the dynamics of synchronization. Close quantitative agreement is found between experimental data and theory describing reactively coupled Duffing resonators with fully saturated feedback gain. In the synchonized state, a significant reduction in the phase noise of the oscillators is demonstrated, which is key for applications such as sensors and clocks. Oscillator networks constructed from nanomechanical resonators form an important laboratory to commercialize and study synchronization—given their high-quality factors, small footprint, and ease of co-integration with modern electronic signal processing technologies. Networks can be made including one-, two-, and three-dimensional networks. Triangular and square lattices can be made.

Abstract: An apparatus comprising a first phase circuit, a second phase circuit, and a current steering circuit. The first phase circuit may be configured to generate a first portion of a phase interpolated clock signal in response to (i) a control signal, (ii) a first bias signal, and (iii) a feedback of said phase interpolated clock signal. The second phase circuit may be configured to generate a second portion of the phase interpolated clock signal in response to (i) the control signal, (ii) a second bias signal, and (iii) the feedback of the phase interpolated clock signal. The current steering circuit may be configured to generate the first bias signal and the second bias signal in response to a reference bias signal.

Abstract: A transmission/reception device includes a transmission circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals to be sent to another device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew; and a reception circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals sent from another transmission/reception device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew.

Abstract: A PLL circuit according to the present invention includes a VCO that outputs an VCO signal having a frequency according to an input voltage, a loop filter that feeds a voltage according to an input current to the VCO, a phase comparator that outputs a phase difference pulse having a width according to a phase difference between a first input signal and a second input signal, a charge pump circuit that receives the phase difference pulse, and inputs the current to the loop filter, and a phase-difference-pulse stop unit that stops the input of the phase difference pulse to the charge pump circuit in a non-input state in which an REF signal (reference frequency signal) is not input. The first input signal is the REF signal itself or a signal obtained by dividing the frequency of the REF signal, and the second input signal is the VCO signal itself or a signal obtained by dividing the frequency of the VCO signal.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference.

Abstract: A semiconductor memory device includes a system clock input block configured to be inputted with a system clock, a data clock input block configured to be inputted with a data clock, a first phase detection block configured to compare a phase of the system clock, generate a first phase detection signal, and determine a logic level of a reverse control signal in response to the first phase detection signal, a second phase detection block configured to compare a phase of a clock acquired by delaying the system clock by a correction time, generate a second phase detection signal, and determine a logic level of a clock select signal in response to the first and second phase detection signals, and a clock select block configured to select and output the data clock or a clock acquired by delaying the data clock.

Abstract: A signal circuit includes a clock terminal for transmitting a reference clock and a data terminal for transmitting an input/output data. In an embodiment, the frequency of the reference clock is one-eighth of the bit rate of the input/output data.

Abstract: A digital phase frequency detector includes a detection unit, a reset unit and a phase comparison unit. The detection unit detects edges of a reference signal and a feedback input signal to generate a reference edge signal and a feedback edge signal. The reset unit generates a reset signal resetting the detection unit based upon the reference edge signal and the feedback edge signal. The phase comparison unit generates first and second phase comparison signals based upon the reference edge signal and the feedback edge signal. The phase comparison unit includes a first flip-flop generating a first comparison signal based upon the reference edge signal and the feedback edge signal, a second flip-flop generating a second comparison signal based upon the reference edge signal and the feedback edge signal, and a latch block latching the first and second comparison signals to generate the first and second phase comparison signals.

Abstract: A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.

Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) an intermediate signal, and (ii) a clock signal. The second circuit may be configured to generate the intermediate signal and a digital complement of the output signal in response to (i) an input signal and (ii) the clock signal. The intermediate signal may form a feedback to ensure the output signal and the digital complement of the output signal are in complementary states during a power up.

Abstract: An improved charge pump based phase locked loop where the loop filter resistor noise is reduced by about an order is presented. The voltage controlled oscillator generates a clock signal, and this is input to the phase detector, which, compares the oscillator clock with the reference clock and using the Charge pump it generates a current output proportional to the phase difference. The loop filter converts this proportional current to a voltage and connects it to the oscillator input. The loop filter consists of a capacitor, resistor and the apparatus that bypasses most of the resistor noise.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an Onlx mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal is used to terminate the ForceSL and Onlx modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during Onlx exit, and resulting in faster DLL locking time.

Abstract: A method for synchronizing input sampling to desired phase angles of sinusoidal signals including determining a delay time period for converging a next sample point to a next desired phase angle based on a phase error value.

Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.

Abstract: A system in accordance with the present invention may include a phase-locked loop circuit, comprising a first input signal oscillating at a reference frequency, a second input signal received from a voltage-controlled oscillator (VCO) after passing through an N-divider, a phase detector and charge-pump, the phase detector comparing a phase of the first input signal and a phase of the second input signal, a loop filter in series with the phase detector and charge-pump, the loop filter having an integrator, a pole zero, and a post-filter, and a buffer in parallel with the integrator and in series with the post-filter, the buffer receiving an output signal from the integrator and isolating the integrator from an input impedance of the post-filter, and the buffer having a multiplexer for selecting between a plus and minus level shift signal, wherein the VCO is in series with the loop filter and the N-divider, and the VCO is configured to receive a tuning voltage signal from the loop filter.

Abstract: According to one embodiment, there is provided a DLL circuit including a delay chain, a plurality of phase comparators, and a controller. The plurality of phase comparators receive the reference clocks individually and receive respectively the clocks from the delay elements in mutually different stages, among the delay elements of the plurality of stages. The controller simultaneously receives comparison results of the plurality of phase comparators, determines the number of stages that generate the clock of which a phase is synchronized with a phase of the reference clock from among the delay elements of the plurality of stages, and selects the number of output stages from among the delay elements of the plurality of stages based on the determined number of stages so that a delay clock having a demanded delay amount with respect to the reference clock is output.

Abstract: A fractional-N frequency synthesizer having reduced fractional switching noise and spurious signals is provided. The synthesizer includes a voltage controlled oscillator for providing an output signal. A fractional-N divider is responsive to the voltage controlled oscillator for providing a divided output signal having fractional switching noise. A band pass filter is responsive to the fractional-N divider for reducing the fractional switching noise and non-linearities that result in spurious signals. A phase detector is responsive to a reference signal and the band pass filter for providing a control signal representative of the phase difference between the reference signal and the signal from the band pass filter. A loop filter is responsive to the phase detector for filtering the control signal to control the voltage controlled oscillator, the output of the loop filter having reduced fractional switching noise and spurious signals.

Abstract: A transmission/reception device includes a transmission circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals to be sent to another device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew; and a reception circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals sent from another transmission/reception device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew.

Abstract: A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module.

Abstract: In a PLL frequency synthesizer, a loop is constituted by a phase comparison unit, a gate unit, a charge pump, a capacitive element, a potential adjustment unit, a voltage-controlled oscillator, and a feedback division unit. In this loop, the gate unit and the charge pump are provided in parallel with the potential adjustment unit. A charging/discharging current is input from the charge pump to the capacitive element and the potential of a first end of the capacitive element is adjusted by the potential adjustment unit, so that a phase difference between a reference oscillation signal and a feedback oscillation signal input to the phase comparison unit is small.

Abstract: Provided is a PLL circuit driven with a differential controlled voltage. The PLL circuit includes a VCO. The VCO outputs an oscillation signal in response to a difference between first and second control voltages. The PLL circuit includes a first loop for generating the first control voltage, and a second loop for generating the second control voltage having a phase opposite to the first control voltage. Intermediate generated signals of the first loop and intermediate generated signals of the second loop which respectively correspond to the intermediate generated signals of the first loop have opposed phases.

Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Abstract: A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal.

Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.

Abstract: An electric circuit includes a first circuit, a second circuit, a synchronization detection circuit, a storage circuit, and a correction circuit. The first clock is configured to operate with a first clock, the second circuit is configured to operate with a second clock which is different in frequency from the first clock, and the synchronization detection circuit is configured to detect synchronization of the first and second clocks. The storage circuit is configured to store an output noise pattern of the second circuit, based on the synchronization detected by the synchronization detection circuit, and the correction circuit is configured to correct an output of the second circuit by using the output noise pattern.

Abstract: An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus.

Abstract: In the following B cycles, the second frequency-divided signal fA is maintained at a low level, while the third frequency-divided signal fB is maintained at a high level. The three-modulus prescaler 13 has a frequency division value (M?1) if the pseudo random values are negative values, and a frequency division value (M+1) if the pseudo random values are positive values, in accordance with the signs of the pseudo random values outputted from the ?? modulator 8. After that, the frequency division value becomes M. A frequency division value of (MN+A+Bx) including the pseudo random value Bx is obtained in the comparison frequency divider 4. A fractional frequency division operation can be realized through ?? modulation by using the pseudo random numbers including negative values, as they are.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.

Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.