Abstract: Non-iterative signal synchronization is disclosed. A system of one embodiment of the invention has a provider and a mechanism. The provider provides two signals. The mechanism non-iteratively synchronizes one of the signals with the other of the signals, based on a pulse indicative of a phase difference between the signals.

Abstract: A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling both the oscillator and the low power oscillator. The oscillator control circuit including at least one real time counter. The oscillator control circuit being so configured that the oscillator is energized when said oscillator control circuit is in a normal mode and that, when a power down signal is received: a) the oscillator control circuit measures an oscillation frequency of the low power oscillator, b) the oscillator control circuit uses the measured oscillation frequency of the low power oscillator to set the real time counter so as to maintain the power down mode for the predetermined time, c) the oscillator control circuit turns off the oscillator and uses the low power oscillator for the duration of the power down.

Abstract: Described are methods for accurately measuring the skew of clock distribution networks on programmable logic devices. Clock distribution networks are modeled using a sequence of oscillators formed on the device using configurable logic. Each oscillator includes a portion of the network, and consequently oscillates at a frequency that depends on the signal propagation delay associated with the included portion of the network. The various oscillator configurations are defined mathematically as the sum of a series of delays, with the period of each oscillator representing the sum. The respective equations of the oscillators are combined to solve for the delay contribution of the included portion of the clock network. The delay associated with the included portion of the clock network can be combined with similar measurements for other portions of the clock network to more completely describe the network.

Abstract: A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.

Abstract: A clock recovery method in digital signal sampling wherein the clock is generated from a phase-locking loop or PLL which multiples a given frequency by a whole number. The method includes comparing the relative position of the signals with respect to the clock so as to determine whether a selected type of the clock transitions is in phase with the same type of signal transitions by: producing over a clock period several zones, one zone corresponding to the selected type of transitions; analysing the signal transitions relatively to the clock uplink or downlink transitions; cumulating in the corresponding zone the analysis results; determining on the basis of the accumulation whether the sampling clock frequency and/or phase needs to be modified or not. The invention is applicable to signals derived from graphics cards.

Abstract: A delay-locked loop (DLL) may include: a variable delay line arrangement operable to receive a reference clock and to output a delayed local clock; a phase comparator device operable to compare said reference clock and said local clock and to provide an up/down indication; and a delay control circuit, responsive to said up/down count-indication, to provide a reduced-noise delay control signal to said variable delay line arrangement, said delay control circuit being operable to count said up/down indication using an escalator code arrangement.

Abstract: A frequency synthesizer for a programmable logic device includes a phase alignment circuit that is controlled by an asynchronous level-mode state machine. The state machine receives a start signal generated by the circuits that determine a concurrence cycle when reference and generated clock signals should be aligned. Then, at the concurrence cycle the state machine replaces a generated clock edge with a reference clock edge to bring the generated clock signal into hard phase alignment with the reference clock signal.

Abstract: A digital circuit for detecting a phase lock condition of a phase locked loop (PLL) circuit includes a pair of counters respectively receiving a digital signal produced by the PLL circuit, and a digital reference signal that is also received by the PLL circuit. A digital comparator is connected to the pair of counters for comparing count values contained therein at an end of a counting cycle, and for generating a first logic signal when the count values are the same and a second logic signal when the count values are different. A resettable memory receives the logic signals generated by the digital comparator and has a capacity sufficient to store a plurality of the logic signals resulting from successive comparisons.

Abstract: The present invention provides a register controlled delay locked loop (DLL) using an internal clock synchronized with an external clock as a delay monitoring clock source and a comparison standard clock source. The inventive register controlled DLL includes a first delay line; a second delay line; a delay model; a phase comparison means; a shift register control means; a master shift register; and a slave shift register.

Abstract: An integrated circuit including a phase lock loop or delay lock loop (PLL/DLL) circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal

Abstract: A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.

Abstract: The present invention has an object to perform phase synchronization pull-in at high speed and with good stability. A predetermined frequency band of a reproduced signal is emphasized by a waveform equalization means 1. Its output signal is sampled by an A/D converter 2 using a reproduction clock. Low-band noises of a sampled signal are suppressed by a low-band noise suppression means 3. Then, cycle information is detected from a specific pattern length or pattern interval using a cycle detection means with high precision and high efficiency. The obtained cycle information is converted into a frequency error by a frequency error detector 9. On the other hand, a phase error is detected by a phase error detector 10 from the output of the low-band noise suppression means 3. The frequency error and the phase error are passed through loop filters and thereafter added, whereby an oscillator 15 which generates a reproduction clock is controlled.

Abstract: A phase detector is comprised of two cross-coupled gates which are capable of phase discrimination down to a level of approximately 10 picoseconds. An arbiter circuit, responsive to the cross-coupled gates, generates mutually exclusive UP and DOWN pulse signals. The UP and DOWN pulse signals may be filtered and used to control the delay line of an all digital delay locked or phase locked loop. Methods of operation are also disclosed.

Abstract: A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is described. The configuration has a delay locked loop (DLL) circuit for synchronizing an internal clock between a respective circuit and an external clock of the circuit system according to the phase difference between the two clocks in a manner dependent on phase changes in the signals. A response sensitivity of the DLL circuit is defined by a filter, which enables a renewed synchronization only after the arrival of a plurality of phase change events. The filter provided for setting the response sensitivity of the DLL circuit is of a variable configuration.

Abstract: A clock signal is supplied from a clock oscillator to a gate circuit. In a period in which a reset signal is at the “H” level, the clock signal is supplied to an internal circuit. When the reset signal becomes at the “L” level, a control is performed by a gate control circuit so as to stop the supply of the clock signal. Consequently, even when a delay signal in the internal circuit becomes longer than one cycle of the clock signal, occurrence of an erroneous operation can be prevented.

Abstract: In accordance with the USB specifications, an accuracy of 0.25% is required for the data transmission rate. To generate a clock signal that allows this accuracy, the invention uses a clock generator unit that does not require a crystal. The clock generator unit includes an internal clock generator, a pulse counter that is connected to the internal clock generator, a pulse number memory, and a pulse filter. The pulse counter counts the number of internally generated clock pulses between two pulses of the synchronization signal, which are transmitted in accordance with the USB specification. The difference between the ascertained pulse number and a nominal pulse number is evaluated and is used for controlling the pulse-suppressing pulse filter. This results in a stabilized clock signal.

Abstract: The present invention provides a DLL and a semiconductor integrated circuit device of reduced power consumption suited for use in equipment that complies with DDR-II specifications. It also provides a DLL and a semiconductor integrated circuit device in which the occurrence of hazards at the time of tap changeover is suppressed, thereby preventing a deviation in output timing as well as malfunction. In accordance with one aspect of the present invention, a delay-locked loop device is provided for adjusting delay times of serially connected first and second delay lines in such a manner that a signal obtained by delaying an input signal by the first and second delay lines is in phase with the input signal, thereby outputting, from the first delay line, a signal that is the result of delaying the input signal by one half cycle of the input signal.

Abstract: A PLL frequency synthesizer able to automatically set an appropriate operating mode of the voltage controlled oscillator is provided. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The appropriate operating mode is selected based on an error signal detected by a phase/frequency detector of the PLL frequency synthesizer. A window comparator is used for switching to adjacent operating modes if the error signal exceeds or falls below predefined upper and lower error voltage limits.

Abstract: A digital phase detector compares the output clock signal of the oscillator with the reference clock signal, an analog phase detector, and a lock detection circuit connected to a digital phase detector and an analog phase detector for avoiding a phase quantization error. The lock detection circuit activates the analog phase detector to run simultaneously with a digital phase detector if the phase error is zero. The activated analog phase detector regulates the output clock signal of the digitally controllable oscillator in a continuously variable manner until the respective clock signal edges of the output clock signal and the reference clock signal are fully synchronous. The lock detection circuit deactivates the analog phase detector and continuously checks and regulates the digital phase detector until the phase error between the output clock signal and the reference clock signal is zero.

Abstract: A phase-locked loop circuit includes one loop for regulating phase of a VCO with respect to a reference source. In another loop, VCO frequency is compared to frequency of a crystal oscilator. Digital counters divide the frequency of the crystal oscillator and VCO to a common reference frequency. Once the frequency loop is locked, the counter at the output of the crystal oscillator is bypassed. The counter is bypassed by a flip-flop circuit clocked by the crystal oscillator and receiving a scaled input from the VCO. While the VCO frequency error is in the frequency range of correction capability of the Phase-locked loop, the output of the flip-flop will duplicate the output of the counter. Thus, the counter can be bypassed and shut off.

Abstract: The present invention is intended to provide a delay lock loop circuit which is capable of providing a minute delay amount with stability regardless of the variations in delay amount due to variations in temperature and power supply voltage for example and process conditions. On the basis of a up/down control signal from a delay amount detector, count value is counted from initial setting value up to maximum setting value or down to minimum setting value. When the count value has reached the maximum or minimum value, another count value is counted up and down, thereby cutting the noise component of the up/down control signal. Consequently, regardless of the variation in delay amount due to a delay line, a delay lock detector to which the latter count value is supplied operates normally, thereby outputting with stability a reference delay step count for obtaining a delay of 1T.

Abstract: A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time (discontinuous skipping thereof) if a metastable state should occur.

Abstract: Systems and method are described for clock recovery or detection of rapid phase transients.

Abstract: An integrated circuit includes a generator for providing a clock signal from a reference signal. The generator, which is of the phase-locked loop type, includes a frequency divider and a phase comparator connected together. A reset circuit is connected to the frequency divider and to the phase comparator for providing a reset signal thereto at each leading edge of the reference signal for synchronizing a low-frequency signal with the reference signal.

Abstract: A generator producing a clock signal whose frequency depends on a control voltage includes a comparator for comparing a period of the clock signal with a desired period, and for providing at least one first control signal based upon the comparison. The generator includes a sampler circuit for sampling the first control signal, and for producing a first sampled control signal. The generator also includes a voltage generator for providing the variable control voltage as a function of the first sampled control signal.

Abstract: The present invention provides a simple smaller-sized elastic integrated circuit having a lower power, to which data synchronized with a first clock is input and which outputs data synchronized with a second clock. The elastic integrated circuit includes a read address counter which operates with an internal clock to output a read address count value; a delay circuit to which the read address count value is input and which delays and outputs the read address count value by a predetermined time period; a write address counter which operates using the read address count value output from the delay circuit with a clock externally input so as to output a write address count value; and a memory circuit which writes data input thereto by the write address count value and reads data written therein by the read address count value.

Abstract: A phase-locked loop (PLL) 1 is provided with means for changing the frequency of the output signal to a desired frequency. The PLL 1 is operated during a first period with a feedback frequency division ratio set to an initial value N′ which controls the conduction time of the charge pumps during a first period having a predetermined length to place an amount of charge on the loop filter 6 during the first period sufficient to produce a control voltage for controlling the voltage-controlled oscillator 10 to output an output signal substantially at the desired output frequency. At the end of the first period, the feedback loop 11 is opened by disabling the charge pump 5 for a second period to allow the control voltage output from the loop filter 6 to settle. Subsequently the feedback loop 6 is closed and the feedback frequency division ratio is set to a proper value N2 such that operation of the PLL 1 subsequent to the second period locks the output frequency to the desired frequency.

Abstract: A clock generation circuit for generating clocks having a plurality of frequencies by which a suitable frequency to each of tasks can be supplied and the power consumption is reduced, comprising a clock generation unit for generating a clock with a constant frequency, a counter operating in synchronization with the clock for counting pulses of the clock, a comparator for comparing a counter value of the counter with the number of pulses of a clock having a desired frequency, and an output gate for controlling supply and stop of pulses of the clock input from the clock generation unit based on a comparison result of the comparator.

Abstract: An amplitude modulated source signal (102) is received, where this signal has a source frequency bandwidth and a source envelope. A dummy envelope is computed that would yield a constant if the dummy envelope and source envelope were to be combined. An amplitude modulated dummy signal (105) is generated, where this dummy signal exhibits the computed, dummy signal envelope and has a prescribed frequency bandwidth different than the source frequency bandwidth. The source and dummy signals are added to form a combined signal (113), which is directed to an input (114a) of a nonlinear circuit (114), that is, one that exhibits amplitude dependent nonlinearity. Signals of the dummy frequency bandwidth and any intermodulation products are filtered from the output, thereby providing a linearized output (118) corresponding to the original, source signal.

Abstract: An apparatus comprising an output circuit and a control circuit. The output circuit may be configured to generate an output signal oscillating at a frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to (i) a frequency of said input signal when in a first mode and (ii) a stored value when in a second mode.

Abstract: A clock signal generation apparatus includes a first device for extracting reference information from an input digital signal. A first oscillator generates a reference clock signal having a frequency depending on a control signal. A second oscillator generates a basic signal having a fixed frequency. A first circuit loop operates for generating a first error signal in response to the reference clock signal and the extracted reference information, and for feeding the first error signal in response to the reference clock signal and the control signal. A second device operates for enabling one of the first circuit loop and the second circuit loop and disabling the other.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

Abstract: A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.

Abstract: A filter using analog to digital conversion, digital filtering and oversampling noise reshaping is disclosed. Application of such a filter to a frequency locked oscillator is disclosed. Application of such a filter to an oscillator having a capability to synchronize with an external stimulus is disclosed.

Abstract: An integrated circuit including a phase lock loop or delay lock loop (PLL/DLL) circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal

Abstract: Phase-locked-loop based data and clock extraction comprising a phase detector that generates up and down pulses. Down pulses are maintained in width approximately equal to 1.5 unit intervals of a local sampling clock. Up pulses are allowed to vary with the phase relationship between the local sampling clock and an incoming encoded bit stream. The up pulses are allowed to vary between 1 and 2 unit intervals of the local sampling clock. The up and down pulses drive a charge pump D/A converter that generates a control voltage. The control voltage sets the frequency of the local sampling clock generated by a voltage controlled oscillator. Shift register controlled by a state machine and clocked by the local clock allows reception of complex data packets arriving by the encoded bit stream.

Abstract: A phase-locked loop (PLL) having a digitally controlled oscillator (DCO), where the DCO receives a digital control signal generated by the PLL and an externally generated oscillator clock signal and generates an output signal having a frequency greater than that of the oscillator clock signal. In one embodiment, the DCO is an analog PLL, such as a fractional-N frequency synthesizer, that receives a two-part digital control signal corresponding to the integer and fractional portions of a desired multiplier. The feedback path within the DCO has a dual-modulus divider that is controlled by a modulus controller to apply, over time, an effective divisor value that achieves the desired degree of multiplication. PLLs of the present invention are especially applicable to low-bandwidth, low-noise applications, such as high-multiplication frequency synthesizers and clock filtering, that are integrated into digital ASICs.

Abstract: A phase-locked loop ciruit having two requency dividing circuits which are reset in response to reset signals. The reset signals are produced by second and third frequency divided signal generated by combining the divided frequency of a reference clock signal and an output signal from a voltage controlled oscillator. The phase-locked loop ciruit adjusts rapidly the frquency and the phase of the output signal of the voltage controlled oscillator to correspond to that of the reference clock signal.

Abstract: A full digital phase locked loop includes a first counter for continuously counting pulses of a first clock pulse stream to produce a varying count number. A second counter counts pulses of a second clock pulse stream to produce a reference signal when a predetermined number of the pulses is counted. The augend input terminals of an adder receive the varying count number of the first. A comparison signal which appears at one of the adder's output terminals is applied to an exclusive-OR gate for detecting an interval between it and the reference signal. A resettable counter counts pulses of the second pulse stream during the detected interval and produces a count number at periodic intervals. Successively produced count numbers are differentiated and the differentiated count number is supplied to the addend input terminals of the adder as a frequency difference feedback signal.

Abstract: A clock synchronization device is disclosed that includes a phase detecting unit for detecting a phase difference between an external clock signal and an internal clock signal, a binary code generating unit for outputting a binary code value according to output signals from the phase detecting unit, a code converting unit for converting the binary code value from the binary code generating unit into a thermometer code value, a D/A converting unit for outputting a voltage corresponding to the thermometer code value from the code converting unit and a clock synchronization control unit for outputting the internal clock signal from the external clock signal according to the output voltage from the D/A converting unit. As the result, the clock synchronization device is controlled by employing the D/A converting unit for converting the binary code to the thermometer code in order to decrease the number of the registers, the leakage current and the chip size.

Abstract: A clock control circuit includes a ring counter for outputting a signal of N bits count value and a complementary signal thereof; a rescue & flag generating circuit for effecting rescue from a bit pattern that is outside of expectations and generating a flag signal JBTFLG having a value corresponding to a combination of bits in a 2N-bit signal; a decoder; a clock selector for outputting a pair of clocks from multiphase clocks based upon a selection control signal from the decoder circuit; an interpolator for outputting a signal having a delay time corresponding to a time that is the result of internally dividing the phase difference between the pair of clocks; a phase comparator for comparing the phase of the interpolator output and the phase of a reference clock; and an interpolator control circuit, the shift direction of which varies, for outputting an interior-division ratio control signal that sets the interior-division ratio of the interpolator based upon the phase comparison by the phase comparator

Abstract: A method and a digital circuit for synthesizing an input signal to produce an output signal are provided. The circuit includes a delay unit with a delay input and a delay output, a switch, and a controller. The selectively switch routes the input signal to the delay input whereafter the switch routes the delay output to the delay input. The controller controls the delay unit in response to the input signal and the output signal. A counter is provided to count a predetermined number of times the delay output is routed to the delay input whereafter the input signal is routed to the delay input to trigger the delay input. The digital circuit synthesizes the input signal to define a Delay-Locked loop (DLL) in which the delay unit is a voltage controlled delay line (VCDL). The invention extends to a computer program product executing the method and to an embedded circuit including the digital circuit.

Abstract: A time to digital converter (TDC) has a pair of digital oscillators. The periods of the oscillators differ by T&Dgr;. The oscillators are triggered by START and STOP pulses. A counter counts a number of pulses until reference points on the signals output by the oscillators coincide. Measurements may be made using a dual resolution method. Intrinsic jitter of the TDC can be determined by comparing sets of measurements in which the switch in resolutions is made at different points. A range extender circuit may be provided to extend a valid measurement range of the TDC.

Abstract: A prescaler (200) includes a first frequency divider (204, 206) configured to receive an input signal at an input frequency. The prescaler further includes a phase rotator (208) coupled to the first frequency divider to produce a plurality of signal phases in response to the input signal. A frequency control circuit (214) is configured as a one-hot decoder to select one signal phase of the plurality of signal phases. The one-hot decoder provides maximum speed of operation of the prescaler by eliminating decoding of the feedback signal.

Abstract: A method and device for synchronising the time between at least two integrated circuits (201, 202), which receive the same pulse signal. In the integrated circuits (201, 202) a counter (204, 206) is used to count the number of pulses in the received pulse signal to synchronise the common time between said integrated circuits.

Abstract: A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

Abstract: An apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal.

Abstract: A PLL device has a voltage-controlled oscillator, a reference generator that generates reference signals with different phases, and a main divider that divides the frequency of the output signal of the voltage-controlled oscillator by a frequency-division ratio N1. An auxiliary divider divides the frequency of the output of the main divider by a frequency-division ratio N2. A distribution circuit distributes the output of the auxiliary divider as feedback signals. Phase detectors compare the reference signals and the feedback signals, and generate error signals. Each of the main divider and the auxiliary divider has a programmable divider or a counter. The main divider and the auxiliary divider are both operative during start-up to shorten PLL lock-up time, and the auxiliary divider then powers down to reduce power consumption.

Abstract: A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

Abstract: A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.