Abstract: A reset device is disclosed which is part of a micro-controller formed on an integrated circuit. The reset device has a counter which outputs a count enable signal after counting a predetermined number of counts. In response to an input reset signal, an input device of the reset device provides a start signal to the counter for initiating count-down thereof. An output device outputs an output reset signal in response to the start signal and the count enable signal. The start signal is inhibited by a control signal, which is provided from a control device in response to an external reset signal received at an input pin of the micro-controller. The input device includes an AND gate which receives the input reset signal, an inverted delayed version of the input reset signal, and the disable signal. The reset device further includes an OR gate which receives the start signal and the count enable signal to provide an input signal to the output device for generation of the output reset signal.

Abstract: A oscillation circuit has a delay loop with a clock delay circuit for generating a delayed clock signal. The clock delay circuit has a selector and has multiple delay elements with delay times differing from each other. The clock delay circuit may produce a time lag which is less than the delay time of any single delay element, the time lag being based on the difference between the time delays of different delay elements. A phase comparator compares the phase of a signal associated the delay loop to that of a reference clock signal, generating a phase difference clock signal. A delay setting circuit can cause the selector to change the selection of one delayed clock signal according to the phase difference signal from the phase comparator in such a manner as to reduce the phase difference.

Abstract: An all-digital frequency following system is provided, which is capable of generating an output frequency which can be either an integral or an irrational multiple of an input frequency. The frequency following system is constructed entirely based on digital devices. It includes a frequency counter, a digital comparator, an up/down counter, and a digitally-controlled oscillator. The frequency counter is used to count the output frequency during each period of the input frequency. At the end of each period of the input frequency, the digital comparator will compare the current output of the frequency counter with a preset reference value to thereby generate a corresponding up/down trigger signal. The up/down counter is set at an initial count which is increased or decreased by one in response to the up/down trigger signal from the digital comparator.

Abstract: In the microcomputer with a PLL (1007), a frequency lock signal generation circuit (101) inputs a XINFAST signal (1025) and a PLLFAST signal (1026) of a L level transferred from the PLL (1007) while frequency oscillation of the PLL (1007) is in unstable state, and then outputs a lock signal (110) to indicate refreshing of counting down to a stable detection timer (107).

Abstract: In a frequency synthesizer, a first, constant frequency divider is connected to a reference frequency oscillator, and a second, variable frequency divider is connected to a voltage-controlled oscillator. A phase difference is detected by a phase detector between the frequency dividers and a first output pulse or a second output pulse is produced when the second frequency divider is leading or lagging the first frequency divider. A charge pump integrates the first and second output pulses to supply a phase difference signal to a lowpass filter which drives rates the voltage-controlled oscillator. An initial phase difference which occurs between the frequency dividers immediately after they are energized is detected and one of the frequency dividers is reset with the detected phase difference to align their phase. As long as the initial phase difference is detected, the passages of the first and second output pulses to the charge pump are blocked.

Abstract: A method and an apparatus for reading a given digital pulse signal of variable length in the domain of a first clock frequency and creating a pulse output signal that is synchronized in the domain of a second clock. The number of cycles the input pulse signal is active, in terms of the first clock, is the same number of cycles as the resulting output signal is active, where for the output signal the number of cycles is measured by the second clock.

Abstract: A phase locked loop is described for generating an output clock signal that is both synchronizing with a synchronizing signal and oscillating at substantially the same frequency as required by the system. The phase locked loop as disclosed compares the time durations of the output clock of a voltage-controlled oscillator with the system clock for N cycles. A correction signal is then generated by comparing these two time durations, and the correction signal is fed back to the voltage-controlled oscillator to eliminate the difference in the time durations. In addition, the voltage-controlled oscillator is also synchronized with the synchronizing signal by using the synchronizing signal as a reset.

Abstract: A signal production circuit for producing a control signal used in a driving and controlling circuit of a display device externally input to the driving and controlling circuit, using an external interface signal. There is a vertical synchronization signal having a predetermined frequency and a reference clock signal in synchronization with the vertical synchronization signal. The signal production circuit includes: a first counter circuit for counting a number of reference clock signal pulses up to a value of a parameter which is preset based on a time interval of one cycle of the vertical synchronization signal and a predetermined target period.

Abstract: An inventive digital delay locked loop (DLL) for outputting at least first and second output clocks includes delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor. A phase detector compares relative phases of the first output clock and the input clock and outputs count-up or count-down control signals in accordance therewith. First and second counters output respective first and second counts in response to the count-up or count-down control signals, and a first multiplexer selects and outputs the first output clock from among the first series of delayed clocks in accordance with the first count. Also, interpolation circuitry receives a portion of the first series of delayed clocks and outputs same, along with a plurality of interpolated clocks, in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor.

Abstract: A first detection circuit, a second detection circuit and a counter circuit. The first detection circuit may be configured to present a first control signal in response to (i) an input signal having a period, (ii) an output signal and (iii) an enable signal. The second detection circuit may be configured to present a second control signal in response to (i) the input signal, (ii) the output signal and (iii) the enable signal. The counter circuit may be configured to present a delay signal in response to (i) the first control signal, (ii) the second control signal and (iii) the output signal. The delay signal may be a fraction of the period of the input signal.

Abstract: A phase locked loop circuit comprises a voltage controlled oscillator generating an output signal having the frequency controlled by an applied control voltage, a comparing circuit for comparing an input signal with the output signal of the voltage controlled oscillator in phase or in frequency, and a charge pump and loop filter receiving an output signal of the comparing circuit for generating the control voltage applied to the voltage controlled oscillator. A control circuit is additionally provided which receives the output signal of the comparing circuit for controlling, on the basis of a pulse width of the output signal of the comparing circuit, a center frequency of a phase locked loop formed of the voltage controlled oscillator, the comparing circuit and the control voltage outputting circuit. Thus, the PLL circuit constructed of only a simple digital circuit and having an enlarged capture range and a high stability, can be realized.

Abstract: A clock pulse generator which has a signal controlled oscillator for producing output clock pulses at a repetition rate determined by the value of a control signal. Control means is operative in a calibration cycle to set the control signal to a low or high value and record the clock pulses counted in a period of predetermined duration, to set the control signal to a high or low value and record the clock pulses counted in a period of said predetermined duration, and to calculate rate of change data representing the rate of change of recorded clock pulses with reference to change in the value of the control signal.

Abstract: In the case of sending the sampled clock of transmission coded data together with the coded data and regenerating a clock synchronized with this sampled clock on the receiver side, the drawing-in is speeded up on the received side for the clock information items SCRn sent at unequal intervals. In the case of generating a control voltage of the VCXO in accordance with the received SCRn and the SCCn by the counter, the CPU calculates the amount of frequency fluctuation per unit time and generates a control voltage in accordance with this amount of fluctuation. Thereby, even if SCRn are received at unequal intervals, a rapid follow-up control of the PLL loop including the VCXO becomes possible.

Abstract: A phase-locked loop circuit with dynamic backup is disclosed. The phase-locked loop circuit with dynamic backup includes a phase comparator, a lowpass filter, a voltage-controlled oscillator, and a detection circuit. The phase comparator compares an input reference signal and a feedback output signal from an output of the phase-locked loop circuit for generating a voltage signal representing the phase difference between the input reference signal and the feedback output signal. After the voltage signal is filtered by the lowpass filter, the filtered voltage signal is sent to the voltage-controlled oscillator for generating the feedback output signal. Coupled to the phase comparator, the detection circuit detects whether or not the phase-locked loop circuit is in lock with the input reference signal.

Abstract: A dividing circuit comprises, connected in a ring, a plurality M of transistor stages, where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage has an input node connected to the output node of a preceding transistor stage in the ring, an enable node connected to the clock nodes of the transistor stages, and an output node connected to the input node of a subsequent transistor stage in the ring.

Abstract: Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops) and a logic circuit (comprising an exclusive OR circuit, AND circuits and an OR circuit), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesizer apparatus can be activated with low noise and can provide a short lockup time.

Abstract: A method and an apparatus for control a timing in a flat panel display system are disclosed. In an alternating current plasma display system for respectively driving a plurality of subfields at every field in three steps such as a) entering and for eliminating a whole pixel for a first predetermined time, b) entering data for a second predetermined time and c) maintaining a discharge at every subfield for times which are different from one another, a first clock generator generates a first clock signal having a high frequency. A second clock generator generates a second clock signal having a low frequency. A first counter counts the second clock signal in response to a vertical synchronizing signal, and generates both a first pulse signal which sets the first and second predetermined times respectively in steps a) and b) in the respective subfield sections and a second pulse signal which sets times in step c) in the respective subfield sections which are different from one another.

Abstract: A frequency standard generator for generating a high accuracy reference frequency by synchronizing a high accuracy atomic frequency standard or equivalent thereof and minimizing a phase difference between the generated reference frequency and the received atomic frequency standard.

Abstract: A phase locked loop unlock detector is provided for a data detection channel in a direct access storage device (DASD). The phase locked loop unlock detector includes a counter for generating a threshold reference relative to a reference signal. An unlock window generator is coupled to the counter for generating an unlock window signal. An unlock error detector is coupled to the unlock window generator for comparing a variable frequency signal with the unlock window signal.

Abstract: A circuit and method for performing a delay locked function for correcting phase differences between an input clock signal RCLK and an internally generated clock signal ICLK and for controlling the correcting step to maintain an accurate locking operation when a phase difference is below a threshold valve (the maximum time for which the internal step jitter may occur).

Abstract: A clock signal generating circuit generates a clock signal having a frequency other than frequencies obtained by dividing a predetermined frequency by natural numbers without using a PLL circuit. An oscillator generates a reference clock signal having a reference frequency. A counter counts the reference clock signal to divide the reference frequency of the reference clock signal. A count value output from the counter is reset when the count value reaches a predetermined number. Sine-wave data of a sine-wave is output when the count value is input, a set of the sine-wave data being output for successive numbers of the count value from zero to the predetermined number. The set of the sine-wave data corresponds to a predetermined number of waves of the sine-wave. A digital-to-analog converter converts the set of the sine-wave data into an analog sine-wave signal. A filter selectively filters a predetermined frequency component contained in the analog sine-wave signal.

Abstract: An oscillating means having an oscillator outputs a reference clock, and a frequency-dividing means sequentially frequency-dividing the reference clock into a half frequency. A temperature correction data creating means detects a temperature, calculates logical delaying/advancing data for a temperature change, and outputs the logical delaying/advancing data in every predetermined period. A temperature correction data input means receives the delaying/advancing data outputted by the temperature correction data creating means and outputs the logical delaying/advancing data to a logical delaying/advancing means. The logical delaying/advancing means operates a state of the frequency-dividing means in every predetermined period on the basis of the set logical delaying/advancing data to control the period of the frequency-divided output signal of the frequency-dividing means so as to be coincident with a desired period.

Abstract: An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another.

Abstract: A digital phase acquisition clock recovery circuit includes a digital phase-locked loop that employs a truth table decoder to set the actual delay through a plurality of individual delay elements to generate a plurality of clock phase signals approximately equally spaced in time over one reference clock cycle, and a data sampler circuit that generates a plurality of received data samples from an incoming data sample taken at the rising edge of the respective clock phase signals and synchronizes the data samples to reference clock on a bit period-by-bit period basis. A digital phase acquisition circuit includes an edge detector which evaluates the data samples over each bit period to detect the location of a transition between respective adjacent samples, wherein logic is employed to continually determine the "relative quality" of each data sample, based upon its sampling time being furthest from a detected edge transition.

Abstract: A prescaler which can be used in a PLL includes a counter section and an extender section. The counter section has a pair of staged, synchronous flip-flops which generate a frequency divided signal by frequency dividing an input oscillation signal by either two or three. The extender section has a plurality of staged, asynchronous flip-flops which generates a second frequency divided signal. A switching circuit connected between the extender section and the counter section controls whether the counter section operates as either a binary counter or a ternary counter. Power conservation is achieved by limiting the counter section to only a pair of flip-flops.

Abstract: A clock adjusting circuit is disclosed which is able to adjust automatically both the phase and pulse width of a balanced transmission clock, to be coincident with the reference clock. Phase comparison circuits 13, 14 detect the difference between the phase of a reference clock (REF) and a feedback signal of the clock output. Counters 15, 16 count based on the difference detected by the phase comparison circuits 13, 14, respectively. Delay circuits 11, 12 delay the clock input signals based on the counted value by the counters 15, 16. Clock output signal is obtained after selecting, by the selector 23, the result of OR or AND of the outputs of the delay circuit 11, 12.

Abstract: A method and circuitry are provided for generating a phase shift in the recovered clock in a high speed, digital data recovery phase locked loop. Since phase step injection can be done in a closed loop environment, the dynamic of the real time phase step response of the PLL can be analyzed using a phase meter. In an open-loop environment, the output of the phase meter with a step response of 60 degree phase shift tracks closely with the internal RC response at the multi-phase outputs of the PLL's phase-to-frequency converter. Since the register and capacitor values vary with process, the scheme for verifying the relative accuracy of the PLL's internal filters can be verified without actually probing the device.

Abstract: A digital phase-locked loop (1) has a counter (4) which counts pulses from a voltage controlled oscillator (8). The counter (4) is latched periodically with a period which is determined by an input signal (I) to the counter (4). The latched value is supplied to a compensation unit (5) which deducts a value which approximately corresponds to half the count counted by the counter circuit (4) when the phase lock is locked correctly. The compensated counts are supplied from the output of the compensation unit (5) to an integrator (6) and counter (9) which applies a control signal to the voltage controlled oscillator (8) via a D/A converter.

Abstract: An apparatus comprising a first circuit configured to receive a first clock signal and delaying the first clock signal by a first delay to generate a second clock signal, the first delay being a first function of a first signal; a phase-frequency detector configured to receive the first clock signal and the second clock signal and generate a second signal dependent on the first delay; a second circuit configured to receive tile second signal and generate a third signal, the third signal being a digital signal; and a current mirror configured to generate the first signal, the first signal being a second function of the third signal.

Abstract: A phase locked loop circuit for extracting a clock component from an input signal and generating a phase locked clock signal. Operates to detect a partial loss of the input signal and keep the input signal of a low-pass filter that is one component of the circuit zero. The clock signal is controlled to be far from an originally assumed signal while a partial loss of the input signal is detected. Hence, the pull-in operation of the PLL is expedited after the normal clock signal can be extracted.

Abstract: A method and apparatus for biasing the voltage controlled oscillator (VCO) (110) of a Phase Locked Loop (PLL) (100) includes a bias circuit (114) providing a peak minimum/maximum voltage detector (202) tied to the control line (116) of the PLL (100). During operation, the detector (202) detects a minimum or maximum voltage on the VCO control line (116) as the bias control voltage (118) applied to the VCO (110) is varied. Detection of such a minimum or maximum voltage is equivalent to the detection of a minimum or a maximum frequency, which in turn equates to the detection of an optimal bias condition for noise.

Abstract: A clock multiplier controls the frequency of an output clock signal according to the frequency of an input clock signal by means of two feedback loops. The first feedback loop, active during a fixed number of initial cycles of the input clock signal, counts cycles of the output clock signal during each cycle of the input clock signal, and controls the output clock frequency according to the resulting count values. The second feedback loop, used after the fixed number of initial cycles, divides the frequency of the output clock signal, and controls the output clock frequency according to the phase difference between the resulting divided signal and the input clock signal.

Abstract: A method and apparatus for controlling an output frequency of a phase locked loop is accomplished by determining a plurality of divider ratios which are based on an input frequency, parameters, and a desired output frequency. Each of the divider ratios is representative of a ratio between the output frequency and input frequency of the phase locked loop. Having determined the plurality of divider ratios, another determination is subsequently made to determine whether the plurality of divider ratios enable the phase locked loop to produce the output frequency within a given frequency tolerance, i.e., within an allowable error. The determination is based on whether changing the divider ratio from the one of the plurality of ratios to an adjacent ratio causes the output frequency to change more than the allowable error. If so, the plurality of ratios needs to be recalculated based on a change in the input frequency and/or one of the parameters.

Abstract: A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.

Abstract: A sampling timebase system uses the frequency stable clock signal present in digital systems to accurately reconstruct waveforms that are synchronous with the clock signal. The sampling timebase system provides a strobe signal having a precisely controlled time delay relative to a trigger event. An interval counter is programmed to count a specified number of the cycles of the clock signal, providing for coarse time delay adjustment of the strobe signal in time increments determined by the period of the clock signal. A fine delay generator triggered by the terminal count of the interval counter provides for fine adjustment of the time delay of the strobe signal. The interval counter and fine delay generator are programmable to progressively vary the time delay between the strobe signal and the trigger event relative to cycles of the waveform. The strobe signals, when applied to a sampler, enable sufficient samples to be acquired to reconstruct selected segments of the waveform.

Abstract: A clock signal received from an external terminal through an input buffer is delayed by delay circuits. A counter circuit is started up in accordance with the clock signal transmitted through the delay circuits to count an oscillation pulse having a frequency which is sufficiently high with respect to that of the clock signal. Further, the counter circuit reversely counts the count in response to a clock signal delayed by one cycle, which has passed through the input buffer. When its count once again reaches the counter value at the start of counting, the counter circuit generates an output timing signal and transmits it to an internal circuit through a clock driver. A delay time outputted from the delay circuits is set to a delay time corresponding to the sum of a delay time of the input buffer and a delay time of the clock driver.

Abstract: A clock control circuit 10 generates a reference clock signal CK.sub.2 in accordance with a clock signal CLK, performs a phase comparison with an oscillation signal S50 from a programmable mask generation circuit 50 at a phase comparator 20, generates an up signal S.sub.up or a down signal S.sub.dw in accordance with the result of comparison, and outputs the same to a counter 30. The counter 30 sequentially determines values of the bits from the most significant bit to the least significant bit, outputs the count S30 to a digital control delay line 40, and controls the frequency of an oscillation signal S40. After reaching the locked state, the counter 30 sequentially determines the values of bits from the least significant bit to the most significant bit in accordance with the up/down signal and tracks the reference clock signal CK.sub.2, therefore the lock up time of the digital PLL circuit can be shortened.

Abstract: A trapezoidal waveform synthesizer converts a digital phase error signal into a plurality of phase-separated trapezoidal analog waveforms. The trapezoidal waveform synthesizer includes an up/down counter that counts the positive and negative phase errors and generates a multi-bit, parallel digital counter output signal that indicates a cumulative current value of the phase errors. The counter output signal includes a least significant bit (LSB) portion and a most significant bit (MSB) portion. An upper PDM circuit converts the MSB portion of the output signal counter and a portion of the LSB portion of the counter output signal to a plurality of sets of serially-weighted multi-bit output signals. A lower PDM circuit converts the MSB and LSB portions of the counter output signal to a plurality of serially-weighted single-bit output signals.

Abstract: A digital device for initializing an integrated circuit supplied from a supply voltage, which comprises a module for generating a monitored clock signal including an initial phase .phi. of pre-oscillation followed by a string of periodic pulses and a module for generating a programable initialization signal receiving this monitored clock signal and makes possible to generate an initialization signal held at a true logic value for the duration of the initial phase .phi. of pre-oscillation increased by a specified number of periods of the string of periodic pulses.

Abstract: A phase synchronous circuit, in the process of locking an internal signal to an input signal by a PLL loop, makes a frequency of the internal signal stepwise approximate to a frequency of the input signal under digital PLL control at a first stage, and adjusting a phase under analog PLL control at a next stage, thus controlling a variable frequency oscillator at the two stages. A gain with which an analog PLL control system is burdened can be thereby reduced, and a gain of VCO may not be set larger than required even if a frequency of an output signal f.sub.out is high.

Abstract: A method and apparatus for synchronizing clock signals on first and second logic blocks connected via an asynchronous bus, wherein the second logic block includes a clock signal generator. The method comprises causing the clock signal on the first logic block to increment a first count; causing the clock signal on the second logic block to increment a second count; comparing the first and second counts; and adjusting the clock signal on the second logic block in response to the result of the comparison to synchronize the two clock signals, wherein the transfer of information between the logic blocks is carried out via the asynchronous bus.

Abstract: A fractional-N phase-lock loop (PLL) with a delay line loop (DLL) having a self-calibrating fractional delay element which controls the PLL feedback signal in such a manner that the delay intervals for the feedback signal are: increased when small fractional divisors (<1/2) causing a lagging phase relationship or large fractional divisors (>1/2) causing a leading phase relationship are sensed; and decreased when small fractional divisors (<1/2) causing a leading phase relationship or large fractional divisors (>1/2) causing a lagging phase relationship are sensed.

Abstract: A programmable delay line. The programmable delay line includes a series of delay cells which are programmably connected in series. The programmable delay line includes a main delay chain and auxiliary delay chains. The main delay chain includes unit delay cells. The auxiliary delay chains include a unit delay cell, and a delay cell which has a delay that is between one and two time greater than the delay through a unit delay cell. The delay resolution of the programmable delay line is less than the delay of a unit delay cell. The programmable delay line further includes a reference oscillator and calibration circuitry. The reference oscillator includes a series of unit delay cells, and generates a reference signal having a period which is an integer multiple of the delay of a unit delay cell. Variations in the delay of a unit delay cell influence the period of the reference signal.

Abstract: The invention provides a PLL circuit which can form a phase difference between input and output signals with a high degree of accuracy without employing a current source for a very weak current and eliminates dependency of the phase difference upon the input signal frequency. In the PLL circuit, phase difference forming current is added within a term of a fixed period to a selected one of charge-up current and charge-down current, selected by a phase comparison circuit, of a charge pump circuit, which charges up or charges down a loop filter under the control of an output signal of a phase comparison circuit, to form a phase difference between input and output signals of the PLL circuit which are to be compared in phase by the phase comparison circuit. The magnitude of the phase difference depends upon and is controlled by a term within which the phase difference forming current.

Abstract: A digital counter comprised of a synchronization judgement circuit and a counting circuit, the synchronization judging circuit receiving as an input signal the results of a comparison from a phase comparison circuit which compares the phase of a reference signal and an output signal of a frequency factoring circuit and outputting a phase synchronization judgement signal to the counting circuit, the counting circuit receiving as input the results of comparison and the phase synchronization judgement signal, performing a count based on the results of comparison, and successively determining a count from the most significant bit to the least significant bit. Also, a digital PLL circuit using the digital counter.

Abstract: Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops) and a logic circuit (comprising an exclusive OR circuit, AND circuits and an OR circuit), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesizer apparatus can be activated with low noise and can provide a short lockup time.

Abstract: The operating speed of an apparatus which operates with a clock is increased by obtaining a clock having a constant duty ratio. The maximum variable delay quantity of a first variable delay circuit 11 is set more than one cycle and less than two cycles of an input clock IN. The delay quantities of the first and second variable delay circuits 11, 12 are decreased with a control signal Vin. In addition, the ratio of the delay quantity of the second variable delay circuit 12 to that of the first variable delay circuit 11 is set to a constant value which is less than 1. A control portion 13 increases and decreases the control signal Vin in such a manner that the phases of an input clock IN and an output clock OUT-A of the first variable delay circuit are coincident with each other. An output clock OUT of the device is set by the output clock OUT-A of the first variable delay circuit, and is reset by an output clock OUT-B of the second variable delay circuit.

Abstract: A device for deriving a clock signal having a specific frequency, from an electrical signal, for example, a video signal, the device including an input terminal (1) for receiving the synchronizing signal; a phase comparator (5) having a first input coupled to the input terminal, a second input and an output; a voltage controlled oscillator (15) having an input coupled to the output of the phase comparator, and an output; a counter (23) having a first input coupled to the output of the voltage controlled oscillator, a second input for receiving a preset control signal, and an output coupled to the second input of the phase comparator; a preset control signal generator (30) having an input coupled to the input terminal, and an output coupled to the second input of the counter, the counter being adapted to set its count value to a preset value in response to the preset control signal applied to its preset control signal input.

Abstract: A clock generator contains a reference oscillator (10), a digital closed delay chain (12), a digital frequency divider (14) and a digital phase comparator (16). The frequency divider (14) is connected between the output of the adjustable delay chain (12) and one input of the phase comparator (16). The output of the reference oscillator (10) is connected to a further input of the phase comparator (16). Between the output of the phase comparator (16) and the delay chain (12) a digital up-down counter (18) is connected, the counting direction of which is determined by the output signal of the phase comparator (16) and by means of which the corresponding length of the delay chain (12) is adjustable.

Abstract: A system is provided for generating an accurate and stable output clock signal of a desired output frequency in response to a system clock signal having a system clock period. The system uses an accurate and stable reference clock signal. The system comprises a measuring circuit and a ratio counter. The measuring circuit receives and processes the system clock signal and produces a measurement, referred to as the system clock measurement, that is indicative of the system clock period. The ratio counter receives the system clock signal and the system clock measurement and generates the output clock signal. The system is resistant to noise in the output clock signal caused by asynchronicity between the system clock signal and the reference clock signal. The system is resistant because it employs at least one of a lock-on unit and a synchronizing controller in operating the clock measuring circuit.