Abstract: The present invention is intended to realize reduction of time for supplying the pulse signal to the internal circuit. The setup time for latching (holding) the signal can be eliminated by generating a pulse signal without latching (holding) the input signal. A semiconductor integrated circuit is provided, which has a signal input circuit for receiving an input signal and outputting an address signal as a function of the input signal without holding the output signal. A pulse signal generating circuit is coupled to the signal input circuit for generating a pulse signal based on the output signal and a first clock signal.

Abstract: A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be “disabled” by an inactive enable signal so they output a constant “0” level for the differential output clock. This disabling feature of the differential clock receiver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

Abstract: A method of generating a symmetrical output signal with a 50% duty cycle. The symmetrical output signal is generated without the need for the input signal to be at twice the frequency of the output signal. By utilizing the differential output of a circuit and cross-coupling this to the inputs of comparators a series of outputs are obtained. These outputs are then used to control a latch device by utilizing only a single edge. Because only a single edge is used to control the low to high and high to low transition, the delay is a fixed constant and the resulting output is a symmetrical output signal with a 50% duty cycle.

Abstract: A device generates pulses of high-precision with programmable duration. The device includes first, second and third pulse generator circuits. The first pulse generator circuit receives at an input a pulse generation command signal, and provides at an output a first pulse for loading the contents of a register in a counter. The second pulse generator circuit is triggered by the first pulse provided by the first pulse generator circuit. The third pulse generator circuit is triggered by a second pulse provided by the second pulse generator circuit, and generates a third pulse to restart the second pulse generator circuit. The second pulse provided by the second pulse generator circuit forms a clock signal for the counter to produce a decrement in the counter. The output signal from the counter is the pulsed signal to be generated. The duration of the pulsed signal is determined by the content of the counter.

Abstract: A signal shaping circuit for use in a transmission line driver and the like is disclosed. The input is pulse signal having a rising edge that triggers a delay circuit which produces a first sequence of multiple delayed outputs and a falling edge which triggers the delay circuit to produce a second sequence of multiple delayed outputs. Transition control circuitry is included which operates to control the transition time of the output signal in a first direction, such as the rise time, in response to the first sequence of multiple delayed outputs and to control the transition time of the output signal in a second direction, such as the fall time, in response to the second sequence of multiple delayed outputs. By controlling the first and second delayed output, the rise and fall times of the output signal can be precisely controlled.

Abstract: A clock pulse transmission circuit is provided which can automatically correct, in case the duty factor of transmitted clock pulses has an error, the duty factor error. In a receiving unit 2, a pair of positive and negative clock pulses Sp and Sn transmitted from a transmitting unit 1 are inputted to a receiver 12 which outputs, in response thereto, a pair of positive and negative clock pulses V3 and V4. The DC components of these positive and negative clock pulses are taken out by a first integrator circuit and a second integrator circuit respectively to transmit them to the transmitting unit 1 through a pair of transmission lines 25 and 26, respectively. In the transmitting unit 1, a difference between the direct current levels of the respective positive and negative clock pulses is found and integrated. The integrated value is supplied to a driver 6 as a threshold voltage Vth.

Abstract: A calibration generator responds to a digital signal by generating a diffntial calibration signal with respect to a reference value established by a reference source. The calibration generator includes an input for receiving the digital signal and a differential output for transmitting the differential calibration signal. A voltage divider connects between voltage sources of opposite polarity and equal magnitude for generating a constant magnitude signal across one resistor in the voltage divider. A switch establishes alternate sets of paths from the voltage divider to the differential output. A control responds to the digital signal for controlling the switch thereby to alternate the paths from the voltage divider to the differential output and generate an alternating, fully differential, constant magnitude calibration signal.

Abstract: A line card integrates subscriber line interface circuitry, A/D and D/A converters, and digital signal processing technology. The digital signal processing technology performs many line card tasks such as switch hook detection, ground key detection, DC feed control, polarity reversal, ringing tests, fault detection, power cross detection, and ring trip detection. Silent polarity reversal is achieved by modulating a digital DC feed current waveform in accordance with a programmable predetermined waveform to smoothly transition the DC voltage of subscriber loop conductors A and B between approximately ground and central office battery voltage. The modulated waveform includes little if any energy in audio frequencies. Additionally, the functionality of the line cards 308[m:1] may be implemented partially or completely in hardware of software.

Abstract: A low-skew single-ended to differential signal converter includes a conventional single-ended to differential converter that drives a pair of output driver circuits. Each driver circuit is formed from a pair of transfer gates that receive a supply voltage or a reference voltage, respectively. The transfer gates transfer only a portion of the supply or reference voltage in response to the inverted signal from the conventional converter. The portion of the transferred voltage is insufficient to trigger output members in the output drivers and the output voltages from the drivers do not transition in response to the noninverted signal. The inverted signal causes the outputs of the transfer gates to transition fully, triggering the respective output inverters. Because the inverted signal causes transitions of both of the output signals, skew of the output signals is reduced relative to skew of the inverted and noninverted signals.

Abstract: Pulse signal generating device includes a duty cycle calculator for calculating a target duty cycle at predetermined intervals, a duty cycle comparator for making a comparison between the target duty cycle calculated by the duty cycle calculator and a current duty cycle of a pulse signal being currently output from the device, and a pulse signal adjuster. The duty cycle comparator determines whether the target duty cycle has presented a variation (increase or decrease) from the current duty cycle by over a predetermined value. Once the duty cycle comparator detects that a difference between the target duty cycle and the current duty cycle is more than the predetermined value, the pulse signal adjuster adjusts the pulse signal, using a pulse rise point immediately before the detection as an adjustment reference point, in such a manner that the pulse signal assumes a duty cycle corresponding to the target duty cycle.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: A complementary clock system is disclosed for producing antiphase clock signals. The system includes a clock generator for producing a first clock signal (t3) and a second clock signal (t4). A first and second driver stage coupled to the clock generator for driving respective clock lines having a capacitive load that corresponds to a first load capacitance and a second load capacitance, respectively. A switchable current path coupled between the first and second clock lines which contains a gating circuit and at least one inductive element. The gating circuit being in a conducting state essentially during the switching intervals (ti) of the first and second clock signals (t3, t4).

Abstract: In an output circuit, a signal /.phi. opposite in phase to a signal /EN inputted through an input terminal 3 is generated by an inverter 1, and a signal .phi. in phase with the signal /EN is generated by two inverters 8 and 2. When the input signal /EN changes from a high level to a low level, a bipolar NPN transistor 35 is turned on instantaneously to decide an output terminal 5 at the low level forcedly. On the other hand, when the signal /EN changes from the low level to the high level, an NPN transistor 10 is turned on in advance of the other circuits to decide the output terminal 5 at the high level forcedly. Accordingly, it is possible to roughly equalize a delay time (from when the level of the input signal /EN changes at the input terminal 3 to when the level of the signal /.phi. changes at an output terminal 4) to another delay time (to when the level of the signal .phi. changes at the output terminal 5), thus realizing an ideal phase relationship between the two signals/.phi. and .phi.

Abstract: Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.

Abstract: A PECL buffer produces a PECL differential signal pair given a single-ended input signal. The buffer does not introduce any phase mismatch and thus no skew to the differential signal pair. Because no phase mismatch exists between the differential signal pair, the present invention is especially suited for high speed systems and circuits. The buffer also allows the differential signal pair to respond continuously to changes in the single-ended input signal.

Abstract: A pulse counter circuit has an invertor which inverts a pulse signal input thereto to form an inverted signal. One of the pulse signal and the inverted signal is selected in response to a selecting signal, and the selected signal is delivered as an output signal. Changeover of a signal to be selected between the pulse signal and the inverted signal is effected at timing of a change in level of the pulse signal. A counter counts pulses of the output signal. A pulse signal changeover circuit selects one of a pulse signal and an inverted signal obtained by inverting the pulse signal, in response to a selecting signal, and the selected signal is delivered as an output signal. The pulse signal is masked by being held at a predetermined level within a predetermined time period, and the inverted signal is masked by being held at the predetermined level within the predetermined time period.

Abstract: In this invention, in arranging a balance type input terminal group or output terminal group in an integrated circuit, the formation is provided with one terminal for grounding and two signal terminals adjacent to this grounding terminal on both sides. In connecting the output terminal group of the first integrated circuit and the input terminal group of the second integrated circuit with each other in such formation, the grounding terminals themselves and signal terminals themselves are respectively connected in one to one. Further, in the integrated circuit formed as mentioned above, among the bonding wires connecting the balance type input terminal group or output terminal group with an electrode group of an inner chip, the two bonding wires connecting the chip with the signal terminals are wired symmetrically with the bonding wire connecting the chip with the grounding terminal as a center.

Abstract: A single-to-differential converter for generating two balanced output signals from one single-ended input signal includes first (3) and second (6) output terminals for providing the balanced output signal, a first transistor (M1) having a control electrode coupled to an input terminal (4) for receiving the input signal, a first main electrode coupled to a supply voltage terminal (1) for receiving a supply voltage and a second main electrode coupled to the first output terminal (3). A second transistor (M2) is provided having a control electrode coupled to a bias voltage terminal (5), a first main electrode coupled to the control electrode of the first transistor (M1) and a second main electrode connected to the second output terminal (6). A diode-connected third transistor (M3) is provided having its main current path coupled to the first output terminal (3), and a diode-connected fourth transistor (M4) is provided having its main current path connected to the second output terminal (6).