Complementary Clock Inputs Patents (Class 327/201)
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Patent number: 11050414Abstract: A dynamic single input-dual output latch includes input, feedback, and output stages. In the input stage, operations are dependent on a clock signal (CLK) and a feedback signal (FB) from the feedback stage. For example, when FB is at a low voltage level and CLK switches to a high voltage level, the input stage enters a data capture mode. Once data has been captured, FB switches back to the high voltage level, placing the input stage in a data hold mode. In the output stage, operations are dependent on CLK but independent of FB. For example, instead of initiating output signal stabilization only after both CLK and FB are at high voltage levels, weak pull-down transistors (including at least one CLK-controlled pull-down transistor) are employed in the output stage to ensure output signal stabilization is initiated after data capture has begun but before FB switches to the high voltage level.Type: GrantFiled: May 22, 2020Date of Patent: June 29, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Uttam Saha, Mahbub Rashed
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Patent number: 10788877Abstract: Embodiments of the disclosure provide a low power multiplexer (MUX) circuit, including: a first data input coupled to an input of a first pass gate device; a second data input coupled to an input of a second pass gate device; a hold latch having an input coupled to a data output of the MUX circuit and an output coupled to an input of a supplemental pass gate device; and a pulse generator for generating a HOLD pulse signal, wherein the HOLD pulse signal is coupled to a control input of the supplemental pass gate device. The hold latch is configured to hold a previously valid output data signal of the MUX circuit until a valid input data signal is available at the first data input or the second data input.Type: GrantFiled: February 11, 2020Date of Patent: September 29, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Sebastian T. Ventrone, Lansing D. Pickup
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Patent number: 10432198Abstract: Disclosed is a lightweight bistable PUF circuit, comprising a decoding circuit, a timing control circuit, a PUF cell array and n sharing foot circuits. The PUF cell array is formed by m*n PUF cells arrayed in m lines and n columns. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the four PMOS transistors have the minimum width-to-length ratio of 120 nm/60 nm under a TSMC 65 nm process. Each sharing foot circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first two-input NAND gate and a second two-input NAND gate, and the four NMOS transistors have a width-to-length ratio ranging from 2 um/60 nm to 8 um/60 nm. The lightweight bistable PUF circuit has a reset function and the advantages of small area, low power consumption, small time delay and high speed.Type: GrantFiled: May 20, 2019Date of Patent: October 1, 2019Assignee: Ningbo UniversityInventors: Pengjun Wang, Gang Li, Huihong Zhang, Yuejun Zhang
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Patent number: 10193536Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.Type: GrantFiled: January 2, 2018Date of Patent: January 29, 2019Assignee: Intel CorporationInventors: Amit Agarwal, Steven K. Hsu, Simeon Realov, Iqbal R. Rajwani, Ram K. Krishnamurthy
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Patent number: 9966935Abstract: A latch circuit includes a first input node, a second input node, a first output node, a second output node, a first switching device coupled between the first output node and the second output node, and a first amplification circuit coupled with the first input node, the second input node, the first output node, and the second output node. The first switching device is configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal. The first amplification circuit is configured to cause a voltage difference across the first switching device based on voltage levels of the first input node and the second input node in response to the first state of the clock signal.Type: GrantFiled: February 25, 2015Date of Patent: May 8, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Tien-Chun Yang
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Patent number: 9825636Abstract: An apparatus for synchronizing an input signal that is asynchronous to a clock signal received by the apparatus. The apparatus comprising selection circuitry configured to select the input signal and to generate a pair of intermediate signals associated with the selected input signal. The apparatus also comprising resolution circuitry configured to provide differential signals based on the pair of intermediate signals and to resolve meta-stability associated with the differential signals. The apparatus also comprising arbiter circuitry configured to determine a dominant value associated with the differential signals and to generate an intermediate output signal based on the determination. The apparatus further comprising latching circuitry configured to generate an output signal based on the intermediate output signal.Type: GrantFiled: October 20, 2016Date of Patent: November 21, 2017Assignee: ARM LimitedInventors: James Dennis Dodrill, Amanda Ashley Scantlin
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Patent number: 9768781Abstract: An embodiment of the present invention is an identification circuit for generating an identification number (ID). The identification circuit includes a plurality of identification cells each comprising a latch having a first output and a second output that are opposite to each other. The first output and the second output are a function of process variations of the identification circuit. A first buffer and a second buffer are provided on both sides of the latch and connected to the first output and the second output of the latch, respectively.Type: GrantFiled: April 11, 2015Date of Patent: September 19, 2017Assignee: Casinda, Inc.Inventors: Jimmy Yong Xiao, Surendra Kumar Rathaur, Visvamohan Yegnashankaran
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Patent number: 9013219Abstract: A flip flop circuit has a first stage and a second stage. The first stage and the second stage each have interleaved filters.Type: GrantFiled: September 11, 2013Date of Patent: April 21, 2015Assignee: The Boeing CompanyInventors: Manuel F. Cabanas-Holmen, Ethan Cannon, Salim A. Rabaa
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Patent number: 9013218Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signal RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.Type: GrantFiled: June 23, 2014Date of Patent: April 21, 2015Assignee: Texas Instruments IncorporatedInventors: Steven Craig Bartling, Sudhanshu Khanna
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Patent number: 8994416Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.Type: GrantFiled: October 3, 2013Date of Patent: March 31, 2015Assignees: STMicroelectronics International N.V., STMicroelectronics SAInventors: Chittoor Parthasarathy, Nitin Chawla, Kallol Chatterjee, Pascal Urard
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Patent number: 8970276Abstract: Circuits and methods are introduced to allow for timing relationship between a clock signal and a synchronization signal to be observed. The observations may include observing the timing relationship between a capture edge of the clock signal and a transition of the synchronization signal. Based on the observations the timing of the synchronization signal transition may be adjusted. Observing the timing relationship may include providing a delayed synchronization signal and a delayed clock signal. The delayed synchronization signal may provide what happens before the capture edge of the clock signal. The delayed clock signal may provide what happens after the capture edge of the clock signal.Type: GrantFiled: December 17, 2013Date of Patent: March 3, 2015Assignee: Analog Devices, Inc.Inventors: Matthew D. McShea, Scott G. Bardsley, Peter Derounian
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Patent number: 8933740Abstract: A semi-dynamic flip-flop is provided. A selecting circuit selects an input signal from a data signal and a test signal. A charging/discharging circuit charges/discharges an intermediate node according to the input signal, a clock signal and a modulation signal. A first storage circuit stores electric potential of the intermediate node. An adjusting circuit generates an adjustment signal according to the clock signal and the potential of the intermediate node. An output signal adjusts electric potential of an output node according to the clock signal and the potential of the intermediate node. A second storage circuit stores the potential of the output node. A reset circuit sets or resets the potential of the output node. A switch, connected between the adjusting circuit and the charging/discharging circuit, is turned on when the semi-dynamic flip-flop is in a normal operation mode.Type: GrantFiled: March 24, 2014Date of Patent: January 13, 2015Assignee: MStar Semiconductor, Inc.Inventor: Wen-Pin Hsieh
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Patent number: 8928379Abstract: A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example.Type: GrantFiled: February 15, 2013Date of Patent: January 6, 2015Assignee: California Institute of TechnologyInventor: Bruce R. Hancock
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Patent number: 8829966Abstract: A current reuse frequency divider including a first latch circuit and a second latch circuit is provided. The first latch circuit includes a first transistor pair and a second transistor pair. The first latch circuit receives a first differential oscillation signal through bodies of the first transistor pair and the second transistor pair and divides the frequency of the first differential oscillation signal to generate a second differential oscillation signal. The second latch circuit is coupled to the first latch circuit and includes a third transistor pair and a fourth transistor pair. The second latch circuit receives the first differential oscillation signal through bodies of the third transistor pair and the fourth transistor pair and divides the frequency of the first differential oscillation signal to generate a third differential oscillation signal.Type: GrantFiled: December 27, 2012Date of Patent: September 9, 2014Assignee: Industrial Technology Research InstituteInventors: Chih-Hsiang Chang, Nai-Chen Cheng, Yu Lee, Ching-Yuan Yang
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Patent number: 8791739Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.Type: GrantFiled: February 24, 2010Date of Patent: July 29, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, Prashant U. Kenkare
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Patent number: 8742811Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.Type: GrantFiled: January 4, 2007Date of Patent: June 3, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Atsushi Umezaki
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Patent number: 8730404Abstract: In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.Type: GrantFiled: May 31, 2012Date of Patent: May 20, 2014Assignee: Silicon Laboratories Inc.Inventors: Clayton Daigle, Abdulkerim L. Coban
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Patent number: 8618855Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.Type: GrantFiled: January 4, 2007Date of Patent: December 31, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Atsushi Umezaki
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Publication number: 20130113538Abstract: A device and a method for eliminating transitions in discrete signals. The working of the device and method is based on allowing the charge of a capacitor with one state when the state opposite the state to which it has been assigned is produced and allowing their discharge through a corresponding capacitor when their state is active. The signal is advantageously consolidated without needing processors or programmes, is very simple, there is increased reliability, and the device can very easily be integrated in any sensor, such as those used in aircraft.Type: ApplicationFiled: November 8, 2012Publication date: May 9, 2013Applicant: Eads Construcciones Aeronauticas,S.A., Sociedad Un ipersnoalInventor: Eads Construcciones Aeronauticas,S.A., Socieda
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Patent number: 8436652Abstract: Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.Type: GrantFiled: June 2, 2011Date of Patent: May 7, 2013Assignee: STMicroelectronics, SAInventor: Sylvain Engels
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Patent number: 8432181Abstract: A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured.Type: GrantFiled: July 25, 2008Date of Patent: April 30, 2013Assignee: Thomson LicensingInventor: Dinakaran Chiadambaram
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Patent number: 8421513Abstract: A master-slave flip-flop circuit comprises a master stage for retaining a master signal, a slave stage for retaining a slave signal and a retention stage. During a normal mode of operation, the retention stage captures a retention signal having a value dependent upon the slave signal. During a retention mode of operation, the retention stage isolates the retention signal from changes in the stage signal and retains the retention signal. During the retention mode the retention stage also provides a master restore signal to the master stage and provides a slave restore signal to the slave stage. The master restore signal and the slave restore signal have values dependent on the retention signal for configuring the master stage and slave stage such that the master and slave signals have values corresponding to the retention signal.Type: GrantFiled: June 1, 2011Date of Patent: April 16, 2013Assignee: ARM LimitedInventor: Sumana Pal
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Patent number: 8421514Abstract: A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a D1 signal, an input to accept a clock signal, an input to accept an inverted shadow-D2 signal, and an output to supply a D2 signal. The master latch has an input to accept a shadow-D1 signal, an input to accept the clock signal, and an output to supply a shadow-D2 signal and the inverted shadow-D2 signal. The slave latch has an input to accept the D2 signal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the D2 signal or the shadow-D2 signal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.Type: GrantFiled: September 2, 2011Date of Patent: April 16, 2013Assignee: Applied Micro Circuits CorporationInventors: Alfred Yeung, Hamid Partovi, Luca Ravezzi, John Ngai
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Patent number: 8415978Abstract: A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.Type: GrantFiled: December 22, 2009Date of Patent: April 9, 2013Assignees: STMicroelectronics s.r.l., STMicroelectronics Design and Application s.r.o.Inventors: Ales Loidl, Ignazio Bellomo, Luca Giussani, David Vincenzoni
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Patent number: 8253464Abstract: A multi-threshold complementary metal-oxide semiconductor technology (MTCMOS technology) master slave flip-flop with a single clock signal includes a master storage element configured to store an input data in response to a clock signal transition and a slave storage element configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition. The master storage element includes low threshold voltage transistors, the slave storage element includes high threshold voltage transistors, and the master and the slave storage elements are provided with a single clock signal.Type: GrantFiled: June 30, 2010Date of Patent: August 28, 2012Assignee: STMicroelectronics International N.V.Inventor: Abhishek Jain
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Patent number: 8195990Abstract: In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels.Type: GrantFiled: August 18, 2011Date of Patent: June 5, 2012Assignee: Oracle America, Inc.Inventors: Ronald Ho, Ashok V. Krishnamoorthy, John E. Cunningham, Robert J. Drost
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Patent number: 8166286Abstract: The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time.Type: GrantFiled: June 11, 2008Date of Patent: April 24, 2012Assignee: Texas Instruments Deutschland GmbHInventors: Ingolf Frank, Gerd Rombach
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Patent number: 8089427Abstract: The invention provides display control circuits for Vacuum Fluorescent Displays (VFDs). The display control circuit controls a plurality of display units of the VFD and comprises an image signal generator generating a plurality of image signals, a clock signal generator generating a clock signal, and a plurality of control signal generators. Each control signal generator receives one of the image signals and the clock signal, generates a control signal for one of the display unit, and determines the duty cycle of the control signal according to the received image signal and the clock signal. The brightness of one display unit varies with the duty cycles of the corresponding control signal. The clock signal generator comprises a plurality of flip-flops coupled in series and a plurality of logic gates.Type: GrantFiled: September 25, 2007Date of Patent: January 3, 2012Assignee: Princeton Technology CorporationInventor: Yen-Ynn Chou
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Patent number: 8063685Abstract: A flip-flop circuit includes a data input, a clock input for receiving a clock signal having active edges and inactive edges, a data output, an input circuit, a pulse generator, and a latch. The input circuit sets first and second nodes to different initial logic states in response to an inactive edge of the clock signal, and selectively changes the logic state of either the first node or the second node in response to a pulse input signal to control the state of a third node, such that the selection depends on the logic state of the data input. The pulse generator circuit enables the pulse input signal in response to an active edge of the clock signal, and disables the pulse input signal in response to detecting the change in the initial logic state of either the first node or the second node. The latch stores a data output signal for output at the data output, the data output signal depending on the logic state of the third node.Type: GrantFiled: August 8, 2010Date of Patent: November 22, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Kapil Narula, Amol Agarwal, Sumeet Aggarwal, Sunit K. Bansal, Sabaa Sandhu, Harkaran Singh
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Patent number: 8044694Abstract: A semiconductor integrated circuit includes a flip-flop circuit, a capacitive element, and a switch circuit. The switch circuit includes a first switch circuit which couples the capacitive element to two nodes of the flip-flop circuit at a first timing, and a second switch circuit which short-circuits ends of the capacitive element connected to the two nodes at a second timing different from the first timing.Type: GrantFiled: July 21, 2009Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventor: Junji Monden
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Patent number: 8026752Abstract: Disclosed is a delay circuit. The delay circuit includes a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit. The pulse generating unit is configured to generate a pulse signal having a preset width in response to a rising edge of an input signal. The timing adjusting unit is configured to activate an output signal in response to the pulse signal after a predetermined time has lapsed. The pulse width adjusting unit is configured to adjust a pulse width of the output signal in response to the activation of the output signal.Type: GrantFiled: June 30, 2009Date of Patent: September 27, 2011Assignee: Hynix Semiconductor Inc.Inventor: Yun Seok Hong
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Patent number: 8024623Abstract: In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol.Type: GrantFiled: November 3, 2008Date of Patent: September 20, 2011Assignee: Oracle America, Inc.Inventors: Ronald Ho, Ashok V. Krishnamoorthy, John E. Cunningham, Robert J. Drost
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Patent number: 7990180Abstract: A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations.Type: GrantFiled: September 9, 2009Date of Patent: August 2, 2011Assignee: VIA Technologies, Inc.Inventors: James R. Lundberg, Imran Qureshi
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Patent number: 7979754Abstract: A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.Type: GrantFiled: January 12, 2009Date of Patent: July 12, 2011Assignee: Oracle America, Inc.Inventors: Robert J. Drost, Ronald Ho, Justin M. Schauer
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Patent number: 7969210Abstract: A master stage 101 comprises a differential circuit composed of transistors 1 and 2, a differential circuit composed of transistors 3 and 4, a differential circuit composed of transistors 5 and 6, a load circuit 7 (a first load circuit), a load circuit 8 (a second load circuit), and a current source transistor 9. The load circuit 7 (the first load circuit) is composed of an inductor 7A (a first inductor), an inductor 7B (a fifth inductor), and a capacity 7C (a first capacity). The inductor 7B and capacity 7C cooperates together in forming a parallel resonance circuit (a first LC parallel resonance circuit), while the parallel resonance circuit is connected in series to the inductor 7A.Type: GrantFiled: September 1, 2006Date of Patent: June 28, 2011Assignee: Panasonic CorporationInventors: Yoshifumi Hosokawa, Noriaki Saito, Yoshito Shimizu
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Patent number: 7808273Abstract: Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal input, and to output a data signal from said sequential circuitry at said data output in response to said clock signal. The sequential circuitry is responsive to a predetermined value at said clamp signal input to switch to a low power mode and to set said data output to a forced value, while retaining said sequential state within said circuitry, said forced value being selected to reduce leakage power from combinatorial circuitry arranged to receive said output data signal.Type: GrantFiled: February 20, 2008Date of Patent: October 5, 2010Assignee: ARM LimitedInventor: David Walter Flynn
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Patent number: 7772905Abstract: It is made possible to provide a flip-flop circuit capable of implementing the error correction function with a small area increase as far as possible and a pipeline system using such a flip-flop circuit. A flip-flop circuit includes: a flip-flop configured to operate based on a rising edge or a falling edge of a first clock signal; a decision circuit configured to compare an input of the flip-flop with an output thereof and output a request signal when the input of the flip-flop is different from the output thereof; and a control circuit configured to receive a second clock signal from outside and generate the first clock signal and a confirmation signal. When the request signal is sent from the decision circuit after the flip-flop has been activated, the control circuit inverts the first clock signal, sends the confirmation to the decision circuit, and makes the decision circuit cancel the request signal.Type: GrantFiled: September 24, 2007Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Yasuda, Keiko Abe
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Patent number: 7768331Abstract: A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and standby mode operation. The system further comprises a standby mode control circuit to control the state of the master and slave flip flops during active and standby mode operation based on at least two control signals. A first transfer gate determines the current flow to and from the master flip flop based on the output of the standby mode control circuit. Similarly, a second transfer gate determines current flow to and from the slave flip flop based on the output of the standby mode control circuit. A first power supply powers the master flip flop during active mode operation.Type: GrantFiled: January 23, 2008Date of Patent: August 3, 2010Assignee: Marvell International Ltd.Inventor: Manish Biyani
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Patent number: 7768330Abstract: For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.Type: GrantFiled: December 26, 2007Date of Patent: August 3, 2010Assignee: Hitachi, Ltd.Inventors: Fumio Yuuki, Hiroki Yamashita, Masayoshi Yagyu, Koji Fukuda
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Patent number: 7719337Abstract: A semiconductor device includes a circuit having a first data holding node and a second data holding node; a first MOS field-effect transistor coupled to the first data holding node; a second MOS field-effect transistor coupled to the second data holding node; and a clock generation circuit coupled to a first gate electrode of the first MOS field-effect transistor for outputting a clock signal, wherein the first gate electrode is coupled to the second data holding node via the second MOS field-effect transistor, and a second gate electrode of the second MOS field-effect transistor is coupled to the first data holding node via the first MOS field-effect transistor.Type: GrantFiled: October 16, 2008Date of Patent: May 18, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 7719342Abstract: An input latch circuit of a semiconductor device includes a setup time adjusting unit configured to selectively delay a clock signal and a hold time adjusting unit configured to selectively delay an input signal. The input latch circuit also includes a latch unit configured to latch an output signal of the hold time adjusting unit according to an output signal of the setup time adjusting unit. The input latch circuit changes and delays the clock signal and the input signal by cutting a fuse within the setup time adjusting unit and the hold time adjusting unit without requiring a change to a circuit in order to adjust a setup time and a hold time.Type: GrantFiled: June 30, 2008Date of Patent: May 18, 2010Assignee: Hynix Semiconductor Inc.Inventor: Hoe Gwon Jeong
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Patent number: 7688125Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a preamplifier circuit, a latch circuit and a current re-use circuit. The current re-use circuit applies a current to the preamplifier circuit during a transparent phase, and applies a similar current to the latch circuit during a latch phase.Type: GrantFiled: January 25, 2007Date of Patent: March 30, 2010Assignee: Texas Instruments IncorporatedInventor: Robert F. Payne
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Patent number: 7626433Abstract: A flip-flop circuit arrangement having a total of four differential amplifiers (1, 2, 3, 4), which are connected to one another to produce a D flip-flop, is specified. According to the suggested principle, the two shared emitter nodes (E1, E2) of the differential amplifiers (1, 2, 3, 4) are connected via a switch pair (S1, S2) to supply potential and are activated by a differential input clock signal at a control input (CN, CP). The present flip-flop circuit is operable using especially low supply voltage (VCC) and is preferably suitable for constructing frequency dividers or shift registers.Type: GrantFiled: February 19, 2004Date of Patent: December 1, 2009Assignee: Austriamicrosystems AGInventor: Wolfgang Hoess
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Patent number: 7622975Abstract: A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion.Type: GrantFiled: July 10, 2007Date of Patent: November 24, 2009Assignee: QUALCOMM IncorporatedInventors: Fad Ad Hamdan, Anthony D. Klein
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Patent number: 7619455Abstract: By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.Type: GrantFiled: April 19, 2007Date of Patent: November 17, 2009Assignee: Honeywell International Inc.Inventors: Roy M. Carlson, David O. Erstad
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Patent number: 7521976Abstract: A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of the circuit to improve the driving capability of the overall latch in the presence of loading capacitances. The latch circuit, when used in a system or stand alone divider, will consume very low power while reducing the silicon die area. Possible applications include but are not limited to frequency dividing and counting applications. Of particular interest is the use of this high-speed latch in a prescaler divider as a part of a charge pump phase-locked loop design for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.Type: GrantFiled: December 7, 2005Date of Patent: April 21, 2009Assignee: NanoAmp Solutions, Inc.Inventors: Douglas Sudjian, David H. Shen
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Patent number: 7501871Abstract: A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D?). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q?). One of the outputs (Q?) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.Type: GrantFiled: January 25, 2005Date of Patent: March 10, 2009Assignee: NXP B.V.Inventors: Mihai Adrian Tiberiu Sanduleanu, Eduard Ferdinand Stikvoort, Idrissa Cissé
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Patent number: 7492192Abstract: A logic processing circuit including a plurality of flip-flop including a front stage flip-flop and a rear stage flip-flop, a logic gate circuit network adapted to process data stored in the front stage flip-flop, a result of the process being stored in the rear stage flip-flop, and switching means for switching between a power-on period and a power-off period, the power-on period being a period in which power is being provided to the logic gate circuit network, the power-on period corresponding to either a low-level state period of a clock signal or a high-level state period thereof, the power-off period being a period in which the power is being turned off, the power-off period corresponding to the state period other than the state period corresponding to the power-on period.Type: GrantFiled: August 22, 2006Date of Patent: February 17, 2009Assignee: Sony CorporationInventor: Ichiro Kumata
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Patent number: 7489174Abstract: A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level inverted from that of the digital data signal within a period within which the clock has a second level; a second control stage configured to output a signal of a first level within the period within which the clock has the second level and a signal of a level within another period within which the clock has the first level; a third control stage configured to output an output signal of the first level within a period within which the signal outputted from the second control stage has the second level; and a phase adjustment circuit configured to adjust the phase to produce a second clock and supply the second clock to the third control stage.Type: GrantFiled: February 23, 2007Date of Patent: February 10, 2009Assignee: Sony CorporationInventor: Atsushi Yoshizawa
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Publication number: 20080258788Abstract: A dynamic latch includes a first stage for receiving an input data value and for providing true and complement logic values representing the input data value; a second stage for receiving the true and complement logic values into first and second dynamic node, when a control signal is active; and a holding that outputs the true and complement logic values while the control signal is active. The second stage may provide a feedback signal to the first stage to block propagation of changes in the input data value after the true and complement logic values have been received. The feedback signal may be derived, for example, from logic values on the dynamic nodes. A holding circuit may be provided.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventors: Ajay Bhatia, Uttam Saha