Abstract: A state retention power gated (SRPG) cell includes an input control circuit having an input coupled to an input signal and an output. The input control circuit includes has transistors configured as a first inverter transmission gate. The transistors also connect in series at least one transistor controlled by a power gating signal. A first latch has an input coupled to the output of the input control circuit and an output. A transmission gate has an input coupled to the output of the first latch and an output that is an output of the SRPG cell. A second latch has an input coupled to the output of the transmission gate and an output that also is an output of the SRPG cell. A second inverter transmission gate has an input coupled to the output of the second latch.

Abstract: The present invention provides a clamp circuit including, a switching section including first and second switching elements connected parallel between a current supply source and a clamp capacitor; a first control section that controls the first switching element to connect the current supply source and the clamp capacitor, when the voltage of an input signal input through the clamp capacitor is lower than a first reference voltage; and a second control section that stores voltage information based on the input signal when the voltage of the input signal is lower than a second reference voltage, and that controls the second switching element to connect the current supply source and the clamp capacitor for a period predetermined based on the voltage information, when the input signal is equal to or higher than the first reference voltage.

Abstract: A system and method to perform scan testing using a pulse latch with a blocking gate is disclosed. In a particular embodiment, a scan latch includes a pulse latch operable to receive data while a pulse clock signal has a first logical clock value and a blocking gate coupled to an output of the pulse latch. The blocking gate is operable to propagate the data from the output of the pulse latch while the pulse clock signal has a second logical clock value.

Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.

Abstract: Sense amplifier-type latch circuits are provided which employ static bias currents for enhancing operating frequency. For example, a sense amplifier-type latch circuit includes a latch circuit that captures and stores data during an evaluation phase of the sense amplifier-type latch circuit, and outputs the stored data to differential output nodes. An input differential transistor pair has drains connected to the latch circuit and sources commonly connected to a coupled source node. A static bias current circuit is connected to the coupled source node to provide a static bias current which flows through the differential transistor pair and cross-coupled inverters of the latch during a precharge phase. A switch device, which is connected to the coupled source node, is turned off during the precharge phase and turned on during the evaluation phase by operation of a clock signal to increase current flow through the differential transistor pair.

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract: A semiconductor integrated circuit includes a first retention flip-flop configured in a first type in which a retention flip-flop is able to retain data based on one of a low-level clock signal and a high-level clock signal, and unable to retain data based on another one of the low-level clock signal and high-level clock signal, and a second retention flip-flop configured in a second type in which a retention flip-flop is able to retain data based on the low-level clock signal and also able to retain data based on the high-level clock signal.

Abstract: Disclosed herein are a delay latch circuit and a delay flip-flop circuit arranged to inhibit the increase in power consumption while preventing malfunction under low voltage conditions. An internal signal output circuit outputs as an internal signal an inverted signal of a data signal starting from an internal transparency start timing until an internal transparency end timing. From the internal transparency end timing until the internal transparency start timing, the internal signal output circuit outputs a fixed value signal as the internal signal. A transistor delays the output internal signal over a time period which ranges from a hold instruction delay timing to the issuance of a data transparency instruction and which includes the internal transparency end timing therebetween.

Abstract: In a clear period, transistors NT38 and PT38 turn on and state retention nodes HQ and H/Q are cleared to an L level and an H level, respectively. In this clear period, a transistor NT21 is off. Consequently, a precharge node PS maintains itself at an H level. Thus, transistors PT31 and NT32 are off, thereby preventing a short circuit from occurring in a clear period. A short circuit is also prevented from occurring in a preset period.

Abstract: The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.

Abstract: An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver. In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

Abstract: Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

Abstract: A semiconductor device includes: a first master-slave flip-flop having a first master latch which receives and latches first data signal in synchronism with first clock and a first slave latch which receives and latches the first data signal from the first master latch in synchronism with second clock; and a second master-slave flip-flop disposed side by side with the first master-slave flip-flop and having a second master latch which receives and latches second data signal in synchronism with third clock and a second slave latch which receives and latches the second data signal from the second master latch in synchronism with fourth clock, and wherein the second slave latch of the second master-slave flip-flop is disposed adjacent to the first master latch of the first master-slave flip-flop and the second master latch of the second master-slave flip-flop is disposed adjacent to the first slave latch of the first master-slave flip-flop.

Abstract: A low-hysteresis high-speed latch circuit is disclosed which isolates a sample stage and hold stage from one another during a latch clock phase and simultaneously shorts the output nodes together during the latch clock phase to reduce hysteresis of the latch.

Abstract: A delay circuit includes a delay unit configured to delay a reference input signal and generate a reference output signal and a storage unit configured to store a plurality of input signals in response to the reference input signal and output the stored signals in response to the reference output signal.

Abstract: A semiconductor device according to one aspect of the present invention includes: a flip-flop; a clock control circuit that controls a clock signal supplied to the flip-flop; and a controller that supplies a data retention signal to the flip-flop and controls the clock control circuit. When the flip-flop is driven by a negative edge of the clock signal and retains data when the clock signal is at a high level, the controller controls the clock control circuit so as to supply a high-level clock signal to the flip-flop after the input clock signal is fixed and before the flip-flop retains data. This prevents the occurrence of unintended latching of data when the flip-flop having a retention function retains data.

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: A flip-flop circuit includes an input portion that receives a first external input signal through a first external input terminal, a storage portion that stores a signal transmitted from the input portion, and an output portion that outputs the signal stored in the storage portion through an external output terminal as a logic operation result with respect to a second external input signal received through a second external input terminal of the input portion. The output portion includes a logic gate directly connected to the external output terminal and an input terminal of the logic gate receives the signal stored in the storage portion.

Abstract: A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit.

Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract: A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a D1 signal, an input to accept a clock signal, an input to accept an inverted shadow-D2 signal, and an output to supply a D2 signal. The master latch has an input to accept a shadow-D1 signal, an input to accept the clock signal, and an output to supply a shadow-D2 signal and the inverted shadow-D2 signal. The slave latch has an input to accept the D2 signal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the D2 signal or the shadow-D2 signal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.

Abstract: In a clear period, transistors NT38 and PT38 turn on and state retention nodes HQ and H/Q are cleared to an L level and an H level, respectively. In this clear period, a transistor NT21 is off. Consequently, a precharge node PS maintains itself at an H level. Thus, transistors PT31 and NT32 are off, thereby preventing a short circuit from occurring in a clear period. A short circuit is also prevented from occurring in a preset period.

Abstract: A level shifting flip-flop for generating a level-shifted output signal based on an input signal includes a master stage and a slave stage. The slave stage has an integrated level shifting circuit. The slave stage level shifts a signal as it passes through the flip-flop, which eliminates the need of level shifting the signal after it is output from the flip-flop.

Abstract: A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.

Abstract: A repeater circuit is disclosed. The repeater circuit includes an input circuit coupled to receive a data input signal and a clock signal, and an output circuit configured to, when activated, drive an output signal on an output node. The input circuit is further configured to activate the output circuit in order to initiate a logical transition of the data output signal. A deactivation circuit is configured to deactivate the output circuit at a delay subsequent to activation. A latch is coupled to the output circuit and it is configured to change a latch output state responsive to activation of the output circuit. The latch is configured to hold a state of the output node subsequent to deactivation of the output circuit. The input circuit is configured to activate the output circuit dependent on the clock signal. The deactivation circuit is configured to deactivate the output circuit independent of the clock signal.

Abstract: In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements, the use of STG may be used to reduce dynamic power consumption.

Abstract: Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source of the third transistive element is coupled to the drain of the fourth transistive element; and a fifth transistive element coupled in parallel to the fourth transistive element. Control logic coupled to the first transistive element, the burn subcircuit, and the fourth transistive element selectively enables the second transistive element, selectively enables the fourth transistive element, and selectively enables the fifth transistive element to enable a read mode or a program mode.

Abstract: A flip-flop circuit includes an evaluation part connected to a first node and a second node to discharge the second node according to a voltage level of the first node, a conditional delay part connected to the second node to discharge a third node to have a voltage level different from a voltage level of the second node, and a keeper logic part connected to the second node and third node to maintain a voltage level of one of the second and third nodes being not discharged.

Abstract: A soft error recoverable storage element suitable for use in latches, flip-flops, static ram memory cells and microprocessor pipeline stages. The storage element employs a redundant copy of the stored data value and a feedback loop. One embodiment employs an interlocking four inverter loop with gating devices that blocks the propagation of a soft error induced change of state and causes the storage element to recover its original stored data state.

Abstract: A latch module comprising a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals, a level-shift module for producing a differential output signal at output terminals, and a regenerative pair of transistor elements coupled together and with the input pair for holding the output signal through the level-shift module. The latch module also includes a pair of gate transistor elements connected in series respectively with the sense pair of transistor elements and with the regenerative pair of transistor elements and responsive to an alternating differential gate signal to activate alternately the sense pair during sense periods and the regenerative pair during store periods. A current injector provides asymmetric operation by injecting current between at least one of the gate transistors and the corresponding sense or regenerative pair of transistor elements so that the sense periods are of different duration from the store periods.

Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.

Abstract: The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator.

Abstract: A prescaler circuit according to an exemplary aspect of the present invention includes a first flip-flop circuit that detects second output data and outputs the detected data as first output data, and a second flip-flop circuit that detects the first output data and outputs the data as the second output data. The first flip-flop circuit includes a master-side latch circuit that generates intermediate data, a slave-side latch circuit that detects the intermediate data and outputs the data as the first output data, and a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4. The master-side latch circuit generates the intermediate data based on the second output data and the control signal.

Abstract: The present invention relates to a switch control device. The switch control device controls a switching operation of a power switch. The switch control device includes an auxiliary power device. The auxiliary power device includes a parasitic capacitor, and charges the parasitic capacitor by receiving a power voltage to generate an auxiliary power voltage. The switch control device includes a control pulse generator driven by the auxiliary power voltage and generating a set pulse and a reset pulse according to an input signal that is input for controlling the switching operation of the power switch. The switch control device generates a gate signal that turns on the power switch by being synchronized with the set pulse and generates a gate signal that turns off the power switch by being synchronized with the reset pulse.

Abstract: A flip-flop for transmitting a scan input and data for scan-testing a semiconductor circuit is provided. The flip-flop includes a first pulse signal generator which generates a first pulse signal in response to a scan enable signal and an inversed scan input signal. A second pulse signal generator generates a second pulse signal in response to the scan enable signal and a scan input signal. A signal transmitter receives a data signal and transmits the data signal to a first node in response to either one of the first and second pulse signals. A signal latch unit receives the data signal transmitted to the first node, and latches and outputs the data signal in response to another one of the first and second pulse signals.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: A flip-flop circuit includes a charge injection module, a sense amp module, and a latch module. The charge injection module is configured to, in response to a clock signal, selectively provide electrical charge from a power supply to a first node. The sense amp module is configured to adjust a voltage of a second node in response to detecting a voltage of the first node crossing a threshold while the charge injection module is providing the electrical charge to the first node. The latch module is configured to in response to the clock signal, store a value based on a voltage of the second node. The latch module is also configured to provide the value as an output of the flip-flop circuit.

Abstract: Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the feedback loop at multiple points, and propagated in parallel from those points to other points in the feedback loop.

Abstract: A control unit alternately repeats a first state in which a first switch and a third switch are on and a second state in which a second switch and a fourth switch are on. A voltage detection unit compares the output voltage that occurs at one terminal (OUT terminal) of an output capacitor with a negative threshold voltage, and generates an abnormality detection signal which is asserted when the output voltage is higher than the threshold voltage Vt. When the abnormality detection signal is asserted, the control unit switches the on resistance of the first switch to a value that is higher than that in a normal state.

Abstract: Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and generates a pulse signal with a high level that may be converted into a second level higher than the first level. The flip-flop may further include a latch that latches input data with a high level equal to a third level lower than the second level and outputs output data with a high level that may be converted into the second level in response to the pulse signal. The third level may be equal to the first level. A supply voltage of the second level may be used as a supply voltage to the latch.

Abstract: A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device, and a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device, and a keeper circuit. The first output is operatively connected to the second input. The keeper circuit is operatively connected to the first output, and the keeper circuit is driven from the second output. The feed-back circuit includes a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output, and a fourth-inverting-stage with a fourth input and a fourth output. The fourth input is operatively connected to the third output. The fourth output is connected to the third input to form a storage node.

Abstract: A clock data recovery circuit. The clock data recovery circuit comprises a transmission line, a phase locked loop, a voltage controlled oscillator, a phase selector, and a D flip-flop. The transmission line receives an input signal. The phase locked loop receives the input signal via the transmission line and a reference clock and generates a first clock signal. The voltage controlled oscillator receives the input signal via the transmission line and a control voltage from an internal node of the phase locked loop, and generates a clock signal. The phase selector receives the input signal via the transmission line and the clock signal from the voltage controlled oscillator, and generates a clock output signal. The D flip-flop receives the input signal via the transmission line and the clock output signal, and generates a data output signal.

Abstract: A latch circuit has: a data input unit to which an input data is input; and a data retention unit including a node connected to the data input unit. The data input unit transmits a data depending on the input data to the node, when both of a first clock signal and a second clock signal that are driven independently from each other are at a first level. The data retention unit holds a data at the node, when at least one of the first clock signal and the second clock signal is at a second level that is an inverted level of the first level.

Abstract: An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies.

Abstract: The domino logic of the general inventive concept receives a feedback signal and an input signal and outputs any one of the feedback signal and the input signal as an output signal in response to an enable signal and a clock signal. The feedback signal is an output signal of a previous cycle of a clock signal. When an enable signal is a first level, the domino logic maintains an output signal of a previous cycle instead of an input signal. According to the present general inventive concept, the domino logic having a data hold function can be embodied.

Abstract: A low power pulse-triggered flip-flop comprises a latch containing a first conductive line and a first connection point and a pulse generator linking to the latch. The pulse generator includes a first N-transistor, a second N-transistor, a third N-transistor, a first inverter and a first P-transistor located on the first conductive line. The first N-transistor is connected to the first connection point and first conductive line. The second N-transistor and the third N-transistor are connected to the first conductive line, a second conductive line and a third conductive line. The first inverter is connected to the second conductive line. The present invention aims to reduce leakage power in a high level fabrication process, and can save power consumption and power-delay-product more than 17% over the conventional pulse triggered flip-flop, and also provides a smaller size of total transistors to lower average leakage current power consumption by 2.4 times.

Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a third node to couple the first data signal to the third node. The first node is decoupled from the second node and a first step of latching the first data signal at the third node is performed, wherein the first step of latching is through the second node while the second node is coupled to the third node. The second node is decoupled from the third node and a second step of latching is performed wherein the first data signal latched at the third node while the second node is decoupled from the third node.