Abstract: A latch device having a selectable feedback path includes a retaining device and system isolation device. The retaining device retains within the feedback path a logical value to be written out. The logical value is latched during an active clock signal. The system isolation device disconnects the retaining device from the feedback path during a write operation. Then, when the logical value is written out, the system isolation device reconnects the retaining device. Thus, the feedback path of the latch device may be disconnected to allow for a change in the latch state without overdriving a feedback inverter.

Abstract: A static logic signal to dynamic logic interface that produces a monotonic output. An inverse of a dynamic logic evaluate clock is fed to the clock input of a transparent latch with clock and enable inputs. A delayed version of the inverse of the evaluate clock is generated by a delay element. The delayed inverse of the evaluate clock is fed to the enable input of the latch. The input to the latch comes from static logic and the output of the latch is fed to the dynamic logic. The net result is a latch that is open until the evaluate clock is instructing the dynamic logic to evaluate, and remains closed until a delay element delay time after the evaluate clock instructs the dynamic logic to reset.

Abstract: In a flip-flop circuit, a master latch has a data input circuit that reads data when a clock input signal is at a first level. When the clock input signal is at a second level, a first data holding circuit holds the data, and a signal switching circuit transfers the data to a slave latch. The slave latch reads the data from a data output circuit when the clock input signal is at the second level. When the clock input signal returns to the first level, a second data holding circuit holds the data read from the data output circuit.

Abstract: A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

Abstract: A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

Abstract: CMOS integrated circuitry responsive to a clock source having an approximately 50% duty cycle includes a one shot having an input terminal connected to be responsive to the clock wave source. The one shot derives a pulse train in response to cycles of the clock. Each pulse in the pulse train has a duration substantially less than one-half cycle of the clock wave, is initiated in response to and during a clock wave transition, and persists for a period after the transition has been completed. Latches respond to plural data signals and the pulse train so each latch is activated to be responsive to its associated data signal only during the pulses.

Abstract: The present invention provides a dual clock D type flip-flop which outputs an active signal after the occurrence of an event on a first data input line triggered by an edge (e.g., a rising edge) of a first clock signal. Thereafter, the output is unchanged by the state of the first data input line and/or the first clock signal until an event is detected on the second data input line based on a second clock signal. The output remains active until the occurrence of another event on the second data input line triggered by an edge (e.g., a rising edge) of the second clock signal. Thereafter, the output remains unchanged by the state of the first data input line and/or the first clock signal until an event is again detected on the first data input line based on the first clock signal. Thus, the dual clock D type flip-flop operates on two separate clock signals and/or data signals without incurring latencies normally present with prior art circuits.

Abstract: A GTL I/O transceiver circuit having a pulsed latch receiver. A pulse generator generate a first pulse and a second pulse within the first pulse in response to a rising edge of the bus clock. The first pulse turns on the differential amplifier of the receiver circuit just long enough to provide a valid amplifier output signal. The second pulse controls a tristate latch such that the value of the amplifier output signal is latched before the differential amplifier is turned off. The pulsed latch receiver turns the differential amplifier on for only a fraction of the period of the bus clock such that power dissipation of the pulsed latch receiver circuit is significantly reduced. By using the pulsed latch receiver in VLSI components having hundreds of I/Os, significant reduction in overall component power dissipation can be achieved and static DC power is eliminated. The GTL I/O transceiver is useful for interfacing VLSI CMOS components to a terminated bus.

Abstract: The semiconductor integrated circuit device of the present invention for accepting an external signal synchronously with an external clock signal, comprises: an internal clock signal circuit for detecting a change in the external clock signal and generating an internal clock signal having a predetermined pulse width; a latch circuit for accepting the external signal in advance and latching the external signal for the period of time corresponding to the predetermined pulse width according to the internal clock signal; and an internal signal generating circuit for generating an internal signal which reflects the logic of the external signal and has the predetermined pulse width, according to the internal clock signal.

Abstract: A data storage circuit (50) has a data input (12′) for receiving a data voltage (D″) and a node (44) for receiving an interim voltage in response to the data voltage. The data storage circuit also includes an output enable circuit (34) for providing at least one conditional path coupled to the node and for coupling the interim voltage to the node. The output enable circuit has a transistor (40p) having a first threshold voltage and operable to provide a conductive path along the at least one conditional path. The data retention circuit (46 and 48) has at least one transistor having a second threshold voltage higher in magnitude than the first threshold voltage. The data storage circuit includes a second node (58) for receiving a second interim voltage in response to the first interim voltage. A second output enable circuit (52) provides at least one conditional path for coupling the second interim voltage to the second node.

Abstract: A novel latch circuit configuration that substantially reduces inverter-based setup and hold times. The latch circuit includes first and second input switches connected to an effective sense amplifier configuration. It is possible for the input switches to receive complementary signals of a balanced input signal. The latch circuit operates in initialization and output modes based on the signal level of an alternating clock signal. The output mode produces an output signal having a first or second signal magnitude based on the magnitude of the input signal at the end of the initialization mode. Also, disclosed is a high-speed serial-to-parallel converter based on this latch circuit.

Abstract: A first latch circuit (15) and a control latch circuit (16) are used to control another circuit (18) in a self-timed circuit arrangement (10). The first latch circuit (15) produces a first latch circuit output signal (L1) responsive to a first clock signal (C1) in a multiple-clock system. The control latch circuit (16) responds to the second clock signal (C2) to latch the first latch output signal (L1) and produce a reset control signal which is used to produce both a reset signal (RE) and a control output signal (L2). The reset signal (RE) resets the first latch circuit (15), while the control output signal (L2) may be used to control the other circuit (18) even after the first latch circuit is reset.

Abstract: A data storage circuit (30) has a data input (12′) for receiving a data voltage (D′) and a node (17′) for receiving an interim voltage in response to the data voltage. The data storage circuit also includes an output enable circuit (32) for providing at least one conditional path coupled to the node and for coupling the interim voltage to the node. The output enable circuit has a transistor (32p) having a first threshold voltage and operable to provide a conductive path along the at least one conditional path. The data storage circuit also includes a data output (19′) for providing an output voltage in response to the interim voltage at the node and a data retention circuit coupled between the node and the data output. The data retention circuit (18′ and 20′) has at least one transistor having a second threshold voltage higher in magnitude than the first threshold voltage.

Abstract: A shut-off circuit included in a dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce noise on either output terminal during a portion of the evaluation phase. Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious input signals have no affect on the output signal levels. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from a precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.

Abstract: The present invention provides a clock input buffer for a self-timed memory core that is configured to store data. The self-timed memory core generates a reset signal for resetting the clock input buffer. The clock input buffer includes a latch functioning block and a model latch functioning block. The latch functioning block receives a clock signal for generating a control signal for triggering the self-timed memory core to perform an I/O operation. On the other hand, the model latch functioning block receives the clock signal and the control signal for generating a delayed inverse clock signal. The model latch functioning block provides the delayed inverse clock signal to the latch functioning block for generating the control signal. The model latch functioning block is configured to have the same delay and a delay that varies at approximately the same rate as a delay in the latch functioning block.

Abstract: A flip-flop circuit 10 is provided with a discord detecting circuit DDC and a clock control circuit CCC. The discord detecting circuit DDC detects the discord of a data input signal DIS of the flip-flop circuit 10 with a data output signal DOS thereof. When the data input signal DIS discords with the data output signal DOS, the clock control circuit CCC supplies a short pulse to the flip-flop circuit 10 as an internal clock signal ICLK in synchronism with the rising of an external clock signal ECLK. On the other hand, when the data input signal DIS coincides with the data output signal DOS, the clock control circuit CCC supplies a low level signal to the flip-flop circuit 10 as the internal clock signal ICLK. Thus, it is possible to suppress electric power consumption required to supply a clock signal, and to prevent errors from being caused in a flip-flop operation.

Abstract: An improved master-slave flip-flop that is characterized by a novel clock generator. The improved flip-flop preserves the true master-slave relationship by ensuring a two step latching process is executed by non-overlapping clocks. The clock generator features an inverter in combination with a current limiter. The current limiter has the effect of shifting the trip point of the inverter such that non-overlapping clocks may be derived from a single master clock signal or a master clock signal and its complement.

Abstract: A state machine operates in synchronization with a reference clock signal (110) to switch between n numbers of states and maintain any one of these states. Every time a condition for transition to each of the n numbers of states is satisfied, a signal output circuit (100) makes one of n numbers of transition condition satisfying signals (111W, 111Z, 111Y . . . ) active and outputs it. One of a plurality of D-type flip-flops (101-1, 101-2, 101-k . . . ) makes active any one of nu numbers of state signals (W, Z, Y . . . ) indicating the corresponding n numbers of states, and holds the corresponding one state. A synchronization pulse generation circuit (102) generates a one-shot synchronization pulse signal (112) in synchronization with the reference clock signal (110), when a transition condition for transition to one state is satisfied.

Abstract: A top clock stacked circuit is provided that substantially prevents charge sharing and that prevents any deleterious bipolar effect. The top clock stacked circuit comprises a primary pre-charge circuit coupled to a primary node, a first device coupled between the primary node and a first secondary node, and a second device coupled between the first secondary node and a second secondary node. A second pre-charge circuit is coupled to the first secondary node and a pre-discharge circuit is coupled to the second secondary node. In response to a first clock polarity, the primary and the second pre-charge circuits pre-charge the primary and the first secondary nodes, respectively, and the pre-discharge circuit pre-discharges the second secondary node. Thereafter, in response to a second clock polarity, the first device creates a path between the primary node and the first secondary node. Because both nodes are pre-charged to the same voltage, charge sharing is substantially prevented.

Abstract: A circuit configuration for storing data has a first clocked register structure connected in parallel with a second register structure. The second register structure is operated in a push-pull mode relative to the first register structure. As a result, changes in the state of an input signal at the input are stored for each clock phase of a clock signal. Therefore, the clocking of the input signal of the circuit configuration can be done at the clock rate of the clock signal.

Abstract: A low power, high performance flip-flop includes a first branch having a number of transistors connected in series, and a second branch having a number of transistors connected in series. A clock signal and a data input signal are coupleable to the first and second branches of the circuit, the circuit generating a stable logic one or logic zero. The circuit has low power consumption and high performance speed.

Abstract: A scan flip-flop circuit includes first and second master latches, a slave latch, and first, second, and third switches. The first master latch latches a data input signal and outputs it to the first output terminal in normal operation. The second master latch latches a scan input signal and outputs it to the second output terminal in a scan test. The slave latch latches an output from the first master latch that is input to a first input terminal, thereby outputting it to a third output terminal in normal operation, and latches an output from the second master latch that is input to a second input terminal, thereby outputting it to the third output terminal in a scan test. The first switch disconnects the first output terminal of the first master latch from the first input terminal of the slave latch in a scan test. The second switch disconnects the first output terminal of the second master latch from the second input terminal of the slave latch in normal operation.

Abstract: A first latch circuit latches output data in response to a leading edge of a clock signal. A second latch circuit latches the output data in response to a trailing edge of the clock signal. When the first latch circuit latches a low level, an n-channel MOS transistor is turned to an on-state in order to supply the transmission path to the low level. When the first latch circuit latches a high level, a p-channel MOS transistor is turned to an on-state during a period during which the second latch circuit latches the low level. The transmission path is supplied to thq high level.

Abstract: A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal.

Abstract: An input buffer and an input-output buffer in full compliance with IDDQ testability are provided, which use a signal fed back to a P-type or N-type controllable switch to turn on or turn off the switch so as to obtain a desired resistance by using an equivalent circuit for the buffer. The problem of reduced operating speed due to the use of a high-impedance resistor is then avoided. Hence, the IDDQ testing results will not be affected by using the input buffer or the input-output buffer, no matter the circuit is operated in an output mode or input mode. Furthermore, the input signal, either in the low state or in the high state, has no effect on the IDDQ testing results either.

Abstract: In a known bitable flip-flop, a first inverter stage (1) is driven by an input signal (D), a second inverter stage (2) by a clock signal (CLK), and a third inverter stage (3) by an output signal (INV2) of the second inverter stage (2). In order to buffer the output signal levels of the inverter stages, the first and third inverter stages (1, 3) can be switched into a disabling state by the clock signal (CLK) and the second inverter stage (2) by an output signal (INV1) of the first inverter stage (1). The new bistable flip-flop is to be set independently of the input signal. For setting the flip-flop, preferably of CMOS design, field-effect transistors (M10, M11) are provided in the third and second inverter stages (3, 2) which inhibit disabling of the third inverter stage (3) by a set signal (SET) and a signal (SETN) that is complementary to it and which allow disabling of the second inverter stage (2) independently of the output signal (INV1) of the first inverter stage (1).

Abstract: A differential flip-flop having reduced circuit complexity, clock loading, and power consumption. The circuit is particularly well adapted for systems requiring high-speed differential flip-flops. The proposed flip-flop uses the parasitic capacitors associated with circuit nodes to dynamically store information. The differential flip-flop uses only one current source, as opposed to the two typically required by its conventional counterpart, saving fifty percent of the total power requirement. This power saving is a tremendous advantage at high frequencies, since current must be high to ensure high-speed operation of the transistors in the circuit. Furthermore, the new flip-flop presents a significantly reduced (fifty percent) load to the clock driver, thus further enhancing the power performance of the systems in which it is used.

Abstract: The electronic circuit contains dual edge triggered flip-flop, which loads data on both the rising edge and the falling edge of a clock signal. The clock signal is supplied by a clock supply circuit with an enable input and a source input for receiving a source signal. The clock supply circuit toggles the clock signal as from an earliest available edge of the source signal after the enable signal at the enable input switches to an active state, irrespective of a polarity of said earliest available edge.

Abstract: An edge triggered latch has an improved transparency window, which is essentially the delay of the N-stack pull-down tree. This minimizes the delay yet guarantees that the circuit will have enough time to evaluate the input data, since the evaluation is limited by the pulse width. This circuit eliminates early mode failure for latches placed in series, without the requirement of delay padding.

Abstract: A prescaler system (100) has a prescaler circuit (102) coupled to a divider (104), wherein the divider includes an improved dynamic flip flop divider (118). The divider (118) includes a TSPC nine-transistor D-flip-flop (10). The divider further includes a tenth transistor such as N channel device (41) having a source coupled to ground (43), a drain coupled to a junction between a drain of a P channel device (34) and a drain of another N channel device (37). The divider also includes an eleventh transistor such as N channel device (42) having a source coupled to ground and a drain coupled to a junction between the drain of a P channel device (35) and the drain of a N channel device (39), the junction providing a feedback signal to a N channel device (36), wherein the eleventh transistor further has a gate coupled to the output signal (/Q.sub.A).

Abstract: A high-speed flip-flop is provided that implements a low power consumption and a high-speed response caused by an interior capacitance reduction. A D flip-flop includes a first latch that receives a clock signal and a data signal to produce a first output signal. A second latch receives the first output signal and the clock signal to produce a second output signal. A third latch receives the second output signal and the clock signal to produce a third output signal. An inverter receives the third output signal to produce the data signal on a rising or falling edge of the clock signal. The first and second latches are preferably ratioed latches having series coupled pull-up and pull-down elements. The third latch is preferably a clock operated latch.

Abstract: A method of implementing a single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes receiving a data-input signal and a clock signal. During the precharge phase, an input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, an output signal that either remains at a logic high level or else transitions from high-to-low is generated by the input stage. The output signal and the clock signal are received by the precharge stage from the input stage. During the precharge phase, a logic high level output signal is generated the precharge stage independently of the signal received from the input stage.

Abstract: A method of implementing a scan flipp for use with logic gates includes configuring the flip-flop into a scan mode or data mode. Then the flip-flop enters the precharge phase in which a dynamic input stage is precharged and a static output stage maintains the output signal from the previous evaluation phase. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. During the evaluation phase in the scan mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the scan input signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

Abstract: A novel latch circuit configuration that substantially reduces inverter-based setup and hold times. The latch circuit includes first and second input switches connected to an effective sense amplifier configuration. It is possible for the input switches to receive complementary signals of a balanced input signal. The latch circuit operates in initialization and output modes based on the signal level of an alternating clock signal. The output mode produces an output signal having a first or second signal magnitude based on the magnitude of the input signal at the end of the initialization mode. Also, disclosed is a high-speed serial-to-parallel converter based on this latch circuit.

Abstract: An output signal is output to a selected one of first and second output nodes in response to an event in which a control node transitions from a first logic state to a second logic state. The selected one of the first and second output nodes is selected in response to a logic state of an input node during the event. A minimum setup time for the logic state of the input node to be stable before the control node transitions to the second logic state is shorter than a minimum time for inverting the logic state of the input node.

Abstract: A clock control circuit is provided in a flip-flop circuit, since a first clock signal supplied to a master latch circuit is generated by an OR logic between a reference clock signal and a skew adjustment clock signal, a second clock signal supplied to a slave latch circuit is generated in accordance with the reference clock signal, the first clock signal has a phase advanced from the second clock signal by exactly an amount of a skew margin. An input signal is fetched into the flip-flop circuit at the rising edge of the first clock signal, then is output at the rising edge of the second clock signal. By this, malfunction due to the clock skew is prevented. The flip-flop circuit can operate as in the normal mode by holding the skew adjustment clock at a logic "0".

Abstract: A current-sensing static amplifier-based flip-flop is useful for high-performance VLSI circuitry. The flip-flop has a short latency and a small hold time, advantageous features in high-performance microprocessors. A flip-flop circuit includes an amplifier stage and a static stage. The amplifier stage has a data input terminal and a clock input terminal. The amplifier stage includes a dual-output amplifier having two output lines connected respectively to two current pulldown paths and a gate connected between the current pulldown paths. The static stage is connected to the amplifier stage and including a static latch.

Abstract: A dynamic pulse register which uses a standard clock signal and exhibits reduced propagation delay. The dynamic pulse register includes a precharge logic block configured to precharge an evaluate signal and an evaluate complement signal during a precharge phase. During an evaluate phase, a pulldown logic block is configured to discharge either the evaluate or evaluate complement signal in response to a valid data input to the pulse register. A driver logic block is configured to convey a data out signal as the complement of the evaluate complement signal, and a data out complement signal as the complement of the evaluate signal. Either the data out signal or the data out complement signal is thus charged (thereby producing the rising edge of the output pulse) in response to the discharging performed by the pulldown logic block.

Abstract: A dynamic pulse register which uses a standard clock signal and exhibits reduced propagation delay. The dynamic pulse register includes a precharge logic block configured to precharge an evaluate signal and an evaluate complement signal during a precharge phase. During an evaluate phase, a pulldown logic block is configured to discharge either the evaluate or evaluate complement signal in response to a valid data input to the pulse register. A driver logic block is configured to convey a data out signal as the complement of the evaluate complement signal, and a data out complement signal as the complement of the evaluate signal. Either the data out signal or the data out complement signal is thus charged (thereby producing the rising edge of the output pulse) in response to the discharging performed by the pulldown logic block.

Abstract: A dynamic CMOS register implemented on a silicon die that requires the use of only two input signals, a data-in signal and an inverse clock signal. Each embodiment includes a self-timed clock circuit having a CMOS PNN tier of FETs with a P channel and two N channels connected serially (sources of P channel at one end connected to bus and N channel at the other end connected to ground, and gate of end N channel connected to bus), a first inverter to receive inverse clock with output connected to gate of P channel, a second inverter connected to drain of P channel, and a NOR gate with one input receiving inverse clock, second input connected to output of second inverter and output connected to gate of center N channel. In one embodiment, a single self-timed clock circuit interfaces with and controls a plurality of CMOS registers.

Abstract: A low-voltage latch adapted for differential mode with a supply voltage of 2.5V and a voltage swing of 200 mV to 3000 mV is described. Two inverters, are used, each having a non-inverting and an inverting input terminal and a non-inverted and an inverted output terminal. The non-inverted output terminals are connected to the input of an OR structure, and the inverted output terminals are connected to the input of another OR structure. The input terminals of one inverter form the input terminals of the latch. The input terminals of the other inverter are connected to the output terminals of the OR structures and form the output of the latch. The supply voltages of the inverters are varied, so that at any given time, only one inverter has an appropriate supply voltage. This inverter then controls the output of the latch. In this way, a latch function is achieved.

Abstract: A staticized flop circuit converts a dynamic signal appearing across the output of a logic circuit into a static signal, and includes a dynamic-to-static convertor which minimizes glitching in the static output. The dynamic-to-static convertor includes a pull-down device, operatively coupled between an output node and a ground, which is closed while an input node is at a precharge potential and which is open while the input node is at a ground potential, and a pull-up device, operatively coupled between a source voltage and the output node, which is closed while the input node is at the ground potential and which is open while the input node is at the precharge potential.

Abstract: A dynamic latch circuit or a dynamic flip-flop circuit of the present invention includes a transfer gate to be controlled by a clock and provided with a complementary configuration using a P-channel and an N-channel MOS (Metal Oxide Semiconductor) transistor. The transfer gate allows the individual node included in the circuit to fully swing between a high potential power source and a low potential power source. This causes a minimum of decrease to occur in an ON current for driving the respective node and thereby realizes high-speed operation. Further, the balance of the rising time and falling time of an output signal is improved, reducing the deviation of the duty of the output signal from 50%. The circuit is therefore operable with sufficient operation margins at positive- and negative-going edges. Consequently, the entire macrocircuit using the circuit of the present invention can have its operation frequency and therefore power consumption lowered.

Abstract: A flip-flop circuit with scan circuitry for use with static logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal, a scan input signal, a scan enable signal, a data enable signal and a single-phase clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data or the scan signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal.

Abstract: In a flipflop circuit, each of master and slave latch/hold circuits is constituted of differential pairs consisting of transistors each connected between VCC and VSS without being in series with another transistor between VCC and VSS. A clock driving circuit has a pull-down function responding to a pair of complementary clocks so as to pull down the level of a pair of complementary data signals supplied to each latch/hold circuit. With this arrangement, the flipflop circuit composed of bipolar transistors can operate with a low voltage of not greater than 1 V.

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths.

Abstract: The present invention provides a latching mechanism for use in high-speed domino logic pipestages. The latching mechanism allows time borrowing across latch boundaries, provides sufficient hold time for the output to be sensed by the next stage, and provides a circuit configuration in which race conditions related to the latching mechanism have inherent positive margin. The latching mechanism of the present invention is applicable to fully self-resetting domino logic, globally resetting domino logic, or any combination thereof. The latching mechanism is a set dominant latch having its set input driven by the output of the last domino logic gate in a pipestage, and having its reset input driven by the output of the last domino logic gate in a pipestage ANDed with a delayed version of the pulsed clock that triggers the domino chain of the pipestage.

Abstract: An integrated circuit provides for doubled data throughput by clocking data on both edges of an attached clock signal. The circuit includes an upper latch stack, responsive to the clock rising edge, and a lower latch stack responsive to the clock falling edge, each latch stack outputting a respective set and clear signal. An active overlap filter logically ORs the set and clear signals from the upper and lower latch stacks to a third set and clear signal which controls operation of an output latch. Data lines are connected to the upper and lower latch stacks, such that a first data signal is clocked to the circuit output during a clock rising edge transition and a second data signal is clocked to the output during a clock falling edge transition. Filter circuitry between the latch stacks and the output latch ensures that set and clear are not asserted simultaneously, thus providing for "glitch" free operation of the circuit.

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

Abstract: A status latch with one-phase control signal is constructed only from purely static gates, thus has great security against interference in the stationary state, and is thus suited in particular for low-voltage operation. In the one-phase latch, the power loss is particularly low due to the lower wiring capacity of the control lines, for which reason it can be advantageously used in particular in digital circuits with high data rates. Advantageously, a low number of transistors is required.