Abstract: Methods, apparatus, systems and articles of manufacture for distributed training of a neural network are disclosed. An example apparatus includes a neural network trainer to select a plurality of training data items from a training data set based on a toggle rate of each item in the training data set. A neural network parameter memory is to store neural network training parameters. A neural network processor is to generate training data results from distributed training over multiple nodes of the neural network using the selected training data items and the neural network training parameters. The neural network trainer is to synchronize the training data results and to update the neural network training parameters.

Abstract: The present disclosure includes storage circuits, such latches. In one embodiment, a circuit includes a plurality of latches, each latch including a first N-type transistor formed in a first P-type material, a first P-type transistor formed in a first N-type material, a second N-type transistor formed in a second P-type material, and a second P-type transistor formed in a second N-type material. The first and second N-type transistors are formed in different P-wells and the first and second P-type transistors are formed in different N-wells. In other storage circuits, charge extraction transistors are coupled to data storage nodes and are biased in a nonconductive state. These techniques make the data storage circuits more resilient, for example, to an ionizing particle striking the circuit and generating charge carriers that would otherwise change the state of the storage node.

Abstract: A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.

Abstract: A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.

Abstract: A shift register comprises: a first generation circuit generating a first clock signal and providing the same to a shift register logic circuit; a second generation circuit generating a second clock signal and providing the same to the shift register logic circuit; and a first control signal terminal (EN1), a second control signal terminal (EN2), a third control signal terminal (EN3) and a fourth control signal terminal (EN4) providing controls to ensure that the first clock signal and the second clock signal are out of phase to each other, and the clock signals can have different frequencies at different time intervals.

Abstract: A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.

Abstract: In general, techniques are described for enabling performance tuning of a storage device. A storage device comprising one or more processors and a memory may perform the tuning techniques. The one or more processors may be configured to receive a command stream including one or more commands to access the storage device. The memory may be configured to store the command stream. The one or more processors may be further configured to insert a delay into the command stream to generate a performance tuned command stream, and access the storage device in accordance with the performance tuned command stream.

Abstract: Systems and methods for controlling a sense amplifier are provided. First and second MOS transistors of a first type are connected in series between a first voltage potential and a node. A gate terminal of the first MOS transistor is coupled to a first data. A gate terminal of the second MOS transistor is coupled to a second data line. A third MOS transistor of a second type is connected between the node and a second voltage potential. The third MOS transistor has a gate terminal coupled to the first data line. A fourth MOS transistor of the second type is connected between the node and the second voltage potential in a parallel arrangement with the third MOS transistor. The fourth MOS transistor has a gate terminal coupled to the second data line. A control signal provided to a sense amplifier is based on a voltage of the node.

Abstract: Disclosed are a switching apparatus including an internal circuit using an inductive element and a control method thereof. The switching apparatus includes a switch that regulates a current of the inductive element, and a signal control circuit that arithmetically calculates a turn-off time point of the switch by using a monitoring voltage corresponding to the current of the inductive element, a sampling voltage of the monitoring voltage, and a reference voltage corresponding to a target average current of the inductive element, and controls the switch.

Abstract: An AC input voltage detecting device includes a first input, a second input, a determining unit, a first voltage-detecting unit, and a second voltage-detecting unit. The first input and the second input are electrically connected to a neutral line and a live line of an AC power, respectively. The determining unit includes a first power switch, a second power switch, and an output, the first and second power switch are electrically connected in series, and the output is coupled to the second power switch. The first voltage-detecting unit is electrically connected to the first input and the first power switch, the second voltage-detecting unit is electrically connected to the second input and the second power switch. A signal for indicating that the AC power supplies normally is generated from the determining unit while the voltages conducted by the live line and the neutral line are normal.

Abstract: A CNFET based pulse generator, including a first Carbon Nanotube Field Effect Transistor (CNFET), a second CNFET, a third CNFET, a fourth CNFET, a fifth CNFET, a sixth CNFET, a seventh CNFET, an eighth CNFET, a ninth CNFET, a tenth CNFET, an eleventh CNFET, a twelfth CNFET, a thirteenth CNFET, and a fourteenth CNFET. The first CNFET, the third CNFET, the fifth CNFET, the seventh CNFET, the tenth CNFET, the twelfth CNFET, and the thirteenth CNFET are P-type CNFETs. The second CNFET, the fourth CNFET, the sixth CNFET, the eighth CNFET, the ninth CNFET, the eleventh CNFET, and the fourteenth CNFET are N-type CNFETs.

Abstract: Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract: A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.

Abstract: A latch circuit may include a first inverting unit configured to drive a second node in response to a level of a first node, a second inverting unit configured to drive the first node in response to a level of the second node, an initialization unit configured to drive the first node at a first level in response to activation of an initialization signal, and a power breaker configured to break a supply of power of a second level to the second inverting unit when the initialization signal is activated.

Abstract: A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge.

Abstract: A system and method have been provided for passively isolating a latch circuit. The method provides a latch having a first input, an output, and a reset port. The latch first input is selectively connected to a first reference voltage. While the latch first input is connected to the first reference voltage, the latch is reset. Subsequent to disconnecting the latch first input from the first reference voltage, a first node is selectively connecting to the latch first input. In response to selectively connecting the first node, a first analog signal is supplied to the latch first input. Subsequent to resetting the latch, the first analog signal is captured and the latch output supplies a digital signal responsive to the captured first analog signal.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

Abstract: Some of the embodiments of the present disclosure provide a D-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed.

Abstract: An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: An internal pulse waveform shaping circuit provided to an IC chip generates an internal pulse monitor signal that changes in a predetermined direction at a rise timing of an internal pulse signal during a period in which a first enable signal is asserted and a second enable signal is de-asserted and then continues in the changed state for a predetermined period of time or longer, and generates the internal pulse monitor signal that changes in the predetermined direction at a fall timing of the pulse signal during a period in which the first enable signal is de-asserted and the second enable signal is asserted and then continues in the changed state for the predetermined period of time or longer. The generated internal pulse monitor signal is output to a tester for detecting the pulse width of the internal pulse signal.

Abstract: The latch circuit includes a transistor whose channel region is formed with an oxide semiconductor (OS). Data is held in a node that is electrically connected to an output terminal and one of a source and a drain of the transistor and brought into a floating state when the transistor is turned off. Note that the oxide semiconductor has a band gap wider than silicon and an intrinsic carrier density lower than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized.

Abstract: A differential SR flip-flop 100 receives a set signal S and a reset signal R, and generates a differential output pair Q and #Q. A first flip-flop FF1 generates a non-inverted output signal Q1 and an inverted output signal #Q1. A second flip-flop FF2 generates a non-inverted output signal Q2 and an inverted output signal #Q2. An averaging circuit 10 averages one output signal (Q1) of the first flip-flop FF1 and one output signal (Q2) of the second flip-flop FF2 so as to generate a first output signal Q3, and averages the other output signal (#Q1) of the first flip-flop FF1 and the other output signal (#Q2) of the second flip-flop FF2 so as to generate a second output signal #Q3. As a differential output pair, the differential SR flip-flop 100 outputs a signal that corresponds to the first output signal Q3 and a signal that corresponds to the second output signal #Q3.

Abstract: An input priority determination circuit is configured such that: (i) when a set signal S is asserted and a reset signal R is negated, an intermediate set signal S? is asserted and an intermediate reset signal R? is negated; (ii) when the set signal S is negated and the reset signal R is asserted, the intermediate set signal S? is negated, and the intermediate reset signal R? is asserted; (iii) when a control signal P indicates a set priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is asserted and the intermediate reset signal R? is negated; and (iv) when the control signal P indicates a reset priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is negated and the intermediate reset signal R? is asserted.

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Abstract: Integrated circuits with delay circuitry are provided. Delay circuitry may receive a clock signal and generate a corresponding delayed clock signal. The delayed clock signal generated using the delay circuitry may exhibit reduced duty cycle distortion in comparison to conventional systems. The delay circuitry may include a pulse generation circuit, a delay circuit, and a latching circuit. The pulse generation circuit may generate pulses in response to detecting rising edges or falling edges at its input. The pulses may propagate through the delay circuit. The latching circuit may generate (reconstruct) a delayed version of the clock signal in response to receiving the pulses at its control input. The delay circuitry may be used in duty cycle distortion correction circuitry, delay-locked loops, and other control circuitry.

Abstract: The invention describes self-timed RS-trigger with the enhanced noise immunity. Declared effect is achieved due to that circuit containing storage unit (1), indication unit (2), paraphase data input (3, 4), paraphase data output (5, 6), and indication output (7), is modified by adding two inverters (8, 9) and preindication unit (10). Inverters increase output capability of the trigger's paraphase data output and provide an electric isolation of the outputs of the storage unit from an external environment that leads to increasing immunity of the data stored in the trigger to influence of noises at signal wires. The preindication unit provides the trigger's indicatability.

Abstract: The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

Abstract: An input priority determination circuit is configured such that: (i) when a set signal S is asserted and a reset signal R is negated, an intermediate set signal S? is asserted and an intermediate reset signal R? is negated; (ii) when the set signal S is negated and the reset signal R is asserted, the intermediate set signal S? is negated, and the intermediate reset signal R? is asserted; (iii) when a control signal P indicates a set priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is asserted and the intermediate reset signal R? is negated; and (iv) when the control signal P indicates a reset priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is negated and the intermediate reset signal R? is asserted.

Abstract: Various methods and apparatus can be used for amplifying a time interval in a variety of applications. In an embodiment, a feedback device is implemented in a time amplifier in conjunction with an output device of the time amplifier.

Abstract: A digital latch circuit substantially reduces leakage current in output stages of edge-triggered digital switching devices. The circuit comprises first and second NAND gates for receiving first and second input signals and providing first and second output signals. The first NAND gate includes a first A input for receiving the first input signal, a first B input connected to a second NAND gate output, a first leakage current control input connected to a second A input of the second NAND gate, and a first NAND gate output for providing the first output signal. The second NAND gate includes the second A input for receiving the second input signal, a second B input connected to the first NAND gate output, a second leakage current control input connected to the first A input of the first NAND gate, and the second NAND gate output for providing the second output signal.

Abstract: A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and drain connected to a third circuit node and the second circuit node, respectively. A fifth transistor has a gate and drain connected to the first and third nodes, respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement.

Abstract: A logic circuit includes two two-terminal switching devices and receives first and second pulses as inputs. Each of the two devices has two different stable resistivity values for each applied voltage that is greater than a first threshold voltage (Vth1) and is smaller than a second threshold voltage (Vth2) that is larger than Vth1. Each switching device, when a voltage less than or equal to Vth1 is applied, becomes in a first state having the higher resistivity of the two resistivity values, whereas when a voltage more than or equal to Vth2 is applied, becomes in a second state having the lower resistivity of the two resistivity values. The two devices are connected in series in a direction with uniform polarity to each other. The first and second states are selectively generated in the first and second devices by a combination of inputs of the first and second pulses.

Abstract: A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.

Abstract: A high speed flip-flop circuit and a configuration method thereof are provided. A small number of transistors may be used to configure a flip-flop circuit, so that the flip-flop circuit may be operated at a high-speed. Additionally, an area occupied by the flip-flop circuit may be reduced, and power consumption may be reduced. Accordingly, the flip-flop circuit may be integrated together with a microwave frequency integrated circuit using a Gallium Arsenide (GaAs) compound semiconductor process.

Abstract: The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

Abstract: A differential SR flip-flop 100 receives a set signal S and a reset signal R, and generates a differential output pair Q and #Q. A first flip-flop FF1 generates a non-inverted output signal Q1 and an inverted output signal #Q1. A second flip-flop FF2 generates a non-inverted output signal Q2 and an inverted output signal #Q2. An averaging circuit 10 averages one output signal (Q1) of the first flip-flop FF1 and one output signal (Q2) of the second flip-flop FF2 so as to generate a first output signal Q3, and averages the other output signal (#Q1) of the first flip-flop FF1 and the other output signal (#Q2) of the second flip-flop FF2 so as to generate a second output signal #Q3. As a differential output pair, the differential SR flip-flop 100 outputs a signal that corresponds to the first output signal Q3 and a signal that corresponds to the second output signal #Q3.

Abstract: A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal.

Abstract: The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth1) is applied, becomes in a first state having a higher resistivity, whereas when a larger second threshold voltage (Vth2) or more is applied, becomes in a second state having a lower resistivity; a resistance connected in series to the switching device; a terminal for applying a bias voltage (Vt) to both ends of a series circuit of the switching device and the resistance; a first pulse inputting terminal; and a second pulse inputting terminal. The invention provides a simple realization of a flip-flop circuit for a sequential logic circuit.

Abstract: Provided is a semiconductor device equipped with a pull-down circuit capable of reducing its area. The pull-down circuit is formed of a depletion type NMOS transistor in which a gate thereof is connected to a ground potential, and an enhancement type NMOS transistor in which a gate and a drain thereof are connected to a source of the depletion type NMOS transistor and a source thereof is connected to the ground potential. An overdrive voltage of the depletion type NMOS transistor is reduced by a threshold voltage of the enhancement type NMOS transistor, whereby a size of the depletion type NMOS transistor can be reduced. Accordingly, an area of the pull-down circuit can be reduced.

Abstract: A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor.

Abstract: A noise filter circuit includes a latch circuit that receives an input signal. The latch circuit includes first and second logic circuits (e.g., NAND circuits). The first and second NAND circuits are configured so that the capability of a P-type transistor that receives a set signal or a reset signal is lower than the capability of an N-type transistor that receives the set signal or the reset signal and the capability of an N-type transistor connected in series with the N-type transistor that receives the set signal or the reset signal (total capability). The noise filter circuit may include a waveform adjusting circuit that receives an output signal from the latch circuit.

Abstract: A FIFO buffer circuit is provided which, in data transmission between two circuit areas having different combinations of a power supply voltage and an operation clock frequency, can perform voltage level and clock rate conversion at the same place and time. In an input side area are a plurality of data entry registers, a write entry management circuit and a full signal generating circuit. In an output side area are a read entry management circuit, an empty signal generating circuit and an output selector. On the boundary between the input and output sides are entry management flag circuits that manage the presence or absence of effective data in the respective data entries; and voltage level converting circuits that convert voltage levels of the outputs of the data entry registers to the voltage levels of the output side. In this way, the clock rate replacements and voltage level conversions are performed.

Abstract: DLL circuit operating more stably at reset. Voltage comparator circuit 21 outputs comparison result signal to hold circuit 22 at first level when power supply voltage VAA is not higher than reference voltage REF and at second level when power supply voltage VAA exceeds reference voltage REF. Hold circuit 22 outputs reset signal RST that it has received to DLL circuit 23 as it is when comparison result signal indicates first level and at second level, hold circuit 22 holds reset signal RST until comparison result signal becomes first level and then outputs it to DLL circuit 23.

Abstract: A circuit for filtering glitches that corrupt a digital input signal includes an enable path input with the digital signal and a reset signal. The enable path generates a corresponding active output signal when the reset signal is null and the digital signal assumes a logic active value, or a null output signal when the reset signal is asserted. The circuit also includes a delay line producing an internal signal as delayed replica of the output signal. The circuit further includes a disable path enabled or disabled by the internal signal, which receives the digital signal and, when enabled, asserts the reset signal when the digital signal becomes null.

Abstract: An embodiment of a device for memorization of a memory bit is provided, comprising a bistable circuit having complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.

Abstract: An integrated circuit (400) includes at least one clocked latch circuit (410). The clocked latch circuit (400) includes a first stage (415) including a latch node (420) positioned between a first pull up device (416) and a first (417) and at least a second pull down device (418), wherein the first stage (415) is operative to receive inputs comprising a data signal (D), a clock signal (CLK) and a clocked complement of the data signal (CDXX). A second stage (441) includes a second pull up device (442) and a third pull down device (445) having the latch node (420) therebetween, wherein at least one gate of the first pull up device (416) and the first (417) and second pull down device (418) is directly coupled to a gate of the second pull up device (442) or the third pull down device (445). An output inverter is coupled to the latch node (420).

Abstract: A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.

Abstract: A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.