Abstract: A circuit and method are provided for ensuring a non-desired output state of a latch or flip-flop cannot be produced. The latch can be configured as a set dominant, reset dominant, or memory dominant circuit by simply placing programmed voltage values on select transistors of the latch. The programmed values will cause either the set input, the reset input, or both set and reset inputs to have a complimentary effect on the output signals even though the set and reset inputs are at the same logic level. The set, reset, and memory dominant circuit is identical in structure; however, the set, reset, and memory dominant features are derived solely by placing programmed values on corresponding transistors within the identical structure. A generic latch circuit can, therefore, be said to operate in one of three dominant ways depending on the programmed values chosen by a selector and fed to a prioritizer.

Abstract: A binary digital logic level sensitive latch comprising a first inverter that provides an output (O1). At least one input signal (I1) and an activation signal (Clk) are provided to the first inventer both being capacitively coupled to an input of the first inverter and a switching threshold of the first inverter. The capacitance of the couplings being predetermined such that the output of the first inverter (O1) is a NOR function of the inputs signals and the activation signal O1={overscore (I1+Clk)}. A second inverter has as inputs capacitively coupled the output of the first inverter (O1), the activation signal (Clk) and an inverted pervious output signal (P) to provide output (O2). A switching threshold of the second inverter and the capacitance of the couplings being predetermined such that the output of the second inverter (O2) takes the function of: O2={overscore ((Clk×P)+O1)}.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A redundant latch circuit resistant to SEUs includes a plurality of latches, a majority voting circuit having inputs connected to the latch outputs, and a feedback reset circuit connected to the latch outputs and driving the latch reset inputs. The majority voting circuit indicates a set state for the redundant latch circuit based upon a majority of the latches being in the set state and indicating a reset state otherwise. The feedback reset circuit may have inputs connected to the outputs of the latches, and outputs connected to the reset inputs of the latches. The feedback reset circuit may switch at least one latch back to the reset state, from an SEU-induced change to the set state, when at least one other latch remains in the reset state to thereby provide resistance to SEUs.

Abstract: Flip-flops both operable at high speed and reliable at low voltage levels. A first flip-flop includes first and second cross-coupled latches. Whenever a high value is passed to one node of a latch in the flip-flop, a low value is passed to the other node of the latch. Therefore, the latches can safely ignore all high input values, which permits the flip-flops of the invention to function at very low voltages. Because writing a high value is normally slower than writing a low value, the flip-flops of the invention also function at very high clock rates, even at very low voltages. In some embodiments, pull-ups and pull-downs are coupled directly to the nodes of the latches, enabling the use of inverters instead of NAND and NOR gates to implement set and reset flip-flops, and thereby increasing the operating frequency of these flip-flops.

Abstract: A pulse generator circuit, in particular for use in or for integrated circuits, which, in the usual way, has a number of inverting elements connected in series, a logic combining element and a delay element. A buffer circuit provided in accordance with the invention ensures that a minimum pulse length of the output pulse generated in response to the input signal is ensured even in the case of an input signal of a very short duration.

Abstract: A low-voltage divide-by-64/65 prescaler fabricated with a 0.35 &mgr;m standard CMOS technology is presented to lower power dissipation. A new dynamic D-flip-flop (DFF) using the dynamic back-gate forward bias method has been developed for low-voltage operation. The prescaler including a preamplifier measured at 1 V supply voltage has a maximum operating frequency of 170 MHz and its power dissipation is only 0.9 mW.

Abstract: A flip-flop (14) is disclosed that includes an input circuit (50), a sense amplifier (52) and an output circuit (56). The input circuit (50) is operable to receive a data input signal and to generate complementary data signals. The sense amplifier (52) is coupled to the input circuit (50). The sense amplifier (52) is operable to receive the data signals from the input circuit (50) and to generate complementary amplified signals based on the data signals. The output circuit (56) is coupled to the sense amplifier (52). The output circuit (56) is operable to receive the amplified signals from the sense amplifier (52) and to generate complementary output signals based on the amplified signals.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A static clock pulse generator comprises a plurality of stages, each of which comprises a reset-set flip-flop and a gating circuit. Complementary outputs of the flip-flop control the gating circuit for supplying clock pulses from a clock input to the output of the stage. When the gating circuit is switched off, it holds the output at a default level. The flip-flop has a set input which receives the output from the preceding stage and a reset input which receives the output from the following stage.

Abstract: A multiple input set/reset circuit is described that includes cross-coupled inverters connected between set and reset nodes. The set/reset circuit also includes at least one set input circuit coupled to the set node configured to receive a set signal and to drive the set node to a first logic state in response to the set signal asserted, and at least one reset input circuit coupled to the reset node configured to receive a reset signal and drive the reset node to the first logic state in response to the reset signal asserted. Incorporated into the set/reset circuit are a first switching circuit to change the logic state of one of the nodes to a second logic state when the other node changes the logic state to the first logic state, and a second switching circuit to disable the first switching circuit after the first and second nodes have completed a logical state change in response to a set or reset signal asserted.

Abstract: A method and apparatus for providing noise immunity for binary signals being transmitted on a chip. A single signal is split into two complementary signals and transmitted from the transmitting portion to the receiving portion. At the receiving portion is a new type of flip-flop, termed a UV flip-flop, similar to an SR flip-flop, but having two memory states for input states 0-0 and 1-1. The Q output of the UV flip-flop is coupled to the receiving point. Since 0-0 and 1-1 are both memory states, positive and negative noise glitches will have no effect on the output of the UV flip-flop.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: Automatic test equipment suitable for testing high speed semiconductor devices. The test equipment includes a formatter circuit with a flip flop that produces an output in the desired format even if the edge signals that control the setting and resetting of the flip flop overlap. The flip flop allows the test system to generate outputs with narrow pulses, and can generate output pulses that are narrower than the controlling edge signals.

Abstract: A SR flip-flop using a device which has negative resistance between two output electrodes provided on one of two semiconductor regions in a fixed reversible reverse breakdown condition of the semiconductor junction formed between the two semiconductor regions. The SR motion is controlled by applying trigger pulses directly to two output electrodes. In this manner, the circuit is simplified and the operation speed is raised.

Abstract: An improved SR latch has a two stages. A generation block generates Q and {overscore (Q)} signals from a set signal and a reset signal. The generation block also has an inactive state. A storage block receives the Q and {overscore (Q)} signals and maintains the Q signal and {overscore (Q)} signals at the voltage level that was output by the generation block prior to when the generation block blocks becomes inactive. In another embodiment, an improved D flip-flop has a sensing block with the improved SR latch of the present invention.

Abstract: The present invention provides a clock input buffer for a self-timed memory core that is configured to store data. The self-timed memory core generates a reset signal for resetting the clock input buffer. The clock input buffer includes a latch functioning block and a model latch functioning block. The latch functioning block receives a clock signal for generating a control signal for triggering the self-timed memory core to perform an I/O operation. On the other hand, the model latch functioning block receives the clock signal and the control signal for generating a delayed inverse clock signal. The model latch functioning block provides the delayed inverse clock signal to the latch functioning block for generating the control signal. The model latch functioning block is configured to have the same delay and a delay that varies at approximately the same rate as a delay in the latch functioning block.

Abstract: An S-R flip-flop circuit is provided using two stacks of gates 2, 6 with an internal signal Int stored therebetween. Feedback from the output O is used to switch the state of the internal signal Int in a manner that provides an edge-triggered response for at least one of the inputs.

Abstract: Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion.

Abstract: An electronic system is described for a flip-flop circuit having a data input stage with a clock input and a data input, coupled to an output stage which generates at least one data output, a reset circuit coupled to said data output stage for resetting the logic state of the data outputs to a predetermined desired condition, and a shutoff circuit coupled to said data input stage blocking data input from being acted on by said data input stage. An alternate embodiment includes a data processing circuit with a feedback mechanism coupled with the reset circuit of the flip-flop which informs the flip-flop that data is no longer required.

Abstract: A self-timed latch circuit according to the present invention includes a first inverter for inverting a set signal, a second inverter for inverting a reset signal, a first main driver driven by an output signal from the second inverter and the set signal, a second main driver driven by an output signal from the first inverter and the reset signal and a static latch cross-coupled with first and second output terminals of the first and second main drivers. The self-timed latch circuit according to the present invention reduces the power consumption and increases the operation speed of the circuit by removing a back-to-back connection and a serial connection of transistors applied to the conventional art. Further, since the static latch consists of cross-coupled inverters, the self-timed latch circuit according to the present invention prevents signal fighting during the logic transition of output signals and also reduces a leakage current generated during the operation of the circuit.

Abstract: A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and Q. These signals have equal rising and falling transitions with the same delays for the Q signal and the Q signal. The second stage has symmetrical pull-up and pull-down circuits.

Abstract: A method for processing a signal transitioning from a high state to a low state is described, comprising the steps of detecting a transition of the signal from a high state to a low state, setting a timer for a predetermined interval, sampling, while the timer is running, the signal to determine whether the signal remains in a low state, determining, by reading the timer, whether the predetermined interval has elapsed, repeating the sampling and determining steps until the predetermined interval has elapsed; and concluding, if the signal remains in a low state for each instance of said sampling step, that the transition is valid.

Abstract: A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output terminal of the master-slave portion is fed back.

Abstract: An RS flip-flop has an inverter, connected to an input terminal of the RS flip-flop, a NOR gate having an Enable-Set input, a NAND gate having an Enable-Reset input, and a first and a second transistor connected to the inverter. The outputs of the NOR and NAND gates are connected, via the gate paths of the first and second transistors, to the gate electrode of a third and a fourth transistor, respectively. The third and the fourth transistor are connected in series and form a holding element, whose common connection point is connected to the output of the inverter and to the output terminal of the flip-flop.

Abstract: A feedback circuit is provided which is capable of realizing handshake functions, flip flop functions, and other functions using a smaller number of elements and chip surface. The threshold circuit is provided with an electrode which is electrically floating and a plurality of input electrodes which are connected with the floating electrode via capacity elements, and the circuit has a mechanism for essentially determining the potential of the floating electrode by means of the potentials applied to the input electrodes, and the output of the circuit is determined by the potential of the floating gate; the output of the threshold circuit is connected to at least one of the plurality of input electrodes, either directly, or via at least one circuit of some type.

Abstract: A dynamic set/reset circuit is provided with a first feedback line and a second feedback line. The first feedback line provides an interlocked feedback signal which permits high frequency operation of the set/reset circuit. The second feedback line prevents the interlocked feedback signal from causing the circuit to improperly change state until the next cycle of the circuit. In this manner, the circuit will operate properly despite an unexpectedly wide pulse on an input line. The dual feedback can be used on the set or reset inputs of a set/reset circuit, or both, and the set/reset circuit can be used in various logic and high speed applications, such as within a microprocessor.

Abstract: A J-K flip/flop type storage register includes an input register and an output register. The input register is active when a clock pulse applied thereto is below a predetermined level defining a logic 0 state and inactive when the clock pulse signal is above the first predetermined level. The output register is active when the level of the clock pulse signal is above a second predetermined level and inactive when the clock pulse signal is below the second predetermined level. There exists a well-defined voltage range during which both the input and output registers are inactive. The transfer of information from the input register to the output register only occurs during the transition from a logic 0 level to a logic 1 level clock pulse signal. The SET and RESET inputs are only enabled when the clock pulse signal is at a logic 0 level.

Abstract: A single chip IC includes a bipolar logic, a complementary metal-oxide semiconductor (CMOS) logic, and a level translator which interfaces the bipolar logic with the CMOS logic. The single chip IC comprises a MOS transistor logic, provided in the bipolar logic, for receiving a control signal which controls an operation of the bipolar logic. The control signal issues from the CMOS logic and bypasses the level translator and is applied to the MOS transistor logic.

Abstract: The bias control means determines the operating mode only when the trigger input comes into a valid state or the inverted output signal is low level, and determines the power saving mode in other cases. During the power saving mode, the comparator does not operate since a bias current is not supplied, therefore, the pulse generator of the present invention can attain a low power consumption. Also, the pulse generator of the present invention can generate an output signal having a desired width regardless of the width of the trigger input.

Abstract: A flip-flop circuit able to commute in correspondence with any logic transition of the input signal using a flip-flop and a logic gate of the EXNOR type receiving at its input a signal and the inverted output of the flip-flop. To the output of the EXNOR gate is connected a set-reset flip-flop which allows a reset to be effected after each commutation of the circuit in order to prepare it for the next transition.

Abstract: A latchable comparator including a comparator and a circuit having a reset input. When the comparator produces a first state, it is latched when the reset input is in the non-reset state. In this state, the comparator receives a comparison signal having a high or low value and a latch signal being outside the range of voltages extending between the low and high values. A reset signal causes the latch signal to be replaced by a comparator reference signal. Further disclosed is a latchable comparator including a comparator and a flip-flop. The comparator has a ramp input, a control input, a first reference input and a second reference input. The flip-flop provides latch signals to each of the first and second reference inputs when its reset input is in the non-reset state and said comparator is generating a first state and maintains the latch signals until a reset signal is received.

Abstract: A dynamic latch circuit design minimizes set and restore power without sacrificing speed. The dynamic latch circuit provides two significant power saving advantages over traditional dynamic latch designs. The first regulates dynamic restore power with the state of the latch. If the dynamic internal node of the latch has not been discharged, then the restore signal applied to the input of the latch is not transferred to the restore device attached to the node. By isolating the restore device under these conditions, additional power is not wasted boot-strapping up the already precharged node. Second, by design, the restore path and set path are separate. The input signals used to set the latch are different and isolated from those performing the restore. Therefore, there is no conducting path between the voltage source and circuit ground as the restore device turns on.

Abstract: A timer comprised of first and second gated SR (set-reset) latches each including two pair (S1, S2 and R1, R2) of inputs and a pair of outputs (Q, QN), the Q output of the first latch being connected to the R2 input of the second latch, and the QN output of the first latch being connected to the S2 input of the second latch, the Q output of the second latch being connected to the S2 input of the first latch, and the QN output of the second latch being connected to the R2 input of the first latch, apparatus for applying a delayed representation of a first pulse signal to the S1 input of the first latch and apparatus for applying a delayed representation of a second pulse signal to the R1 input of the first latch, apparatus for applying an inverted representation of the pulse signal to the S1 input of the second latch and apparatus for applying an inverted representation of the second pulse signal to the R1 input of the second latch, whereby timed output signals representing a differential between leading edges

Abstract: A bistable logic network of the sequential type, responsive to the edges of input signals, comprising first and second input SR flip-flops which are connected to an output SR flip-flop through two transfer and block logic gates.Each of said logic gates has two input terminals connected to the output terminal and to one input terminal of an input flip-flop.The output terminals of the output flip-flop are feedback connected to the other input terminals of the two input flip-flops.

Abstract: A differential RS latch circuit has a series structure wherein a first differential transistor pair, a second differential transistor pair and a third differential transistor pair are connected in three stages, and jointly function as one current switch. A first diode serving as a first level shift element is provided in a first current path between a power source node and a grounding node, and second and third diodes serving as second and third level shift elements are provided in a second current path between the power source node and the grounding node. The number of elements provided in the first current path is equal to that of elements provided in the second current path. As a result, the first and second current paths are equal to each other in response speed to a signal, and thus an hazard is prevented from occurring even at the time of the switching operation between the first and second current paths.

Abstract: A control circuit for a power transistor, connected between two supply terminals in series with a load. The control circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, which produces a signal at two levels relative to the node between the power transistor and the load. The level shifter comprises a flip-flop the output of which controls the power transistor, and an electronic switch, for example a MOSFET transistor, connected between the "set" input of the flip-flop and the node and controlled by the "reset" input of the flip-flop in such a way as to be closed when the "reset" input is greater, by a predetermined value, than that of the node. The electronic switch prevents the parasitic current flowing through the set and reset inputs from erroneously switching the power transistor.

Abstract: A semiconductor memory device with an address transition detector comprises a flip-flop circuit (FF) having set and reset input terminals and a delay circuit (3). A pulse signal is input to a set input terminal (S) of the flip-flop circuit (FF) and an output signal (P) of the flip-flop circuit (FF) is input through the delay circuit (3) to a reset terminal (R) of the flip-flop circuit (FF), whereby a constant width signal which is independent of a waveform of an address signal and which responds only to the change of address can be obtained as an address transition signal of a SRAM (static random access memory). An internal circuit of the SRAM is initialized by the constant width signal, thereby preventing a malfunction caused by the fact that an initialization time depends on the waveform of the address signal.

Abstract: A microprocessor circuit is provided that allows the internal microprocessor clock speed to vary depending upon a register that can be programmed by software. In addition, the drive strength of the internal clock generator may similarly be varied by software programming. The programmer or user of the microprocessor may change the internal clock speed such that the microprocessor operates at a first frequency or at a second frequency depending upon the performance requirements. A lower frequency of operation may be selected for low power consumption and low EMI, while a higher frequency of operation may be selected for computational intensive and high performance applications.

Abstract: A semiconductor integrated bipolar flip-flop circuit prevents or suppresses erroneous operation arising from a current induced by external noise and flowing through a parasitic capacitance associated with a p-type diffused resistor. The semiconductor integrated circuit includes bipolar transistors that are directly involved with set and reset operations of the flip-flop circuit having bases connected to a two-stage inverter including bipolar transistors so that the bases of the bipolar transistors involved in setting and resetting are not connected directly to a p-type diffused resistor.

Abstract: A hazard-free digital pulse divider circuit is provided which enables an output having a period one and one-half times that of the input pulse signal. Means for selectively extending output pulse in full or half period increments are also provided.

Abstract: A synchronizing means is provided for synchronizing an asynchronous interrupt signal to a synchronous clock signal for a computer system or the like. The synchronizing means includes a plurality of latch subsystems, where each of the latch subsystems has a sample input terminal for receiving a synchronous clock signal and a hold terminal for receiving a complementary synchronous clock signal. Set logic means are provided for generating a set output signal in response to certain predetermined output signals of the synchronizing means having a predetermined relationship therebetween, which occurs when an input interrupt signal has a duration greater than 1.5 periods of the synchronous clock signal. The set logic means includes AND gates and OR gates. Reset logic means are provided for generating a reset output signal. The reset logic means includes AND gates and OR gates.

Abstract: A regenerative comparator provides the capability of operating faster than a traditional regenerative comparator and the hysteresis points can be individually set and fine tuned. The regenerative comparator includes a current mirror having an input transistor connected to first and second output transistors, a first and second reference current sources which are set at a first and second predetermined level, respectively. An outputs of the first and second output transistors are provided to the latch through an inverter. The output of the latch transitions from a first logical output state to a second logical output state when an input current increases from a magnitude less than the first predetermined level to a magnitude greater than the first predetermined level.

Abstract: A clock switcher circuit for providing at least one set of clock signals selected from a plurality of clock sources. A first clock signal having a first pulse length and a second clock signal having a second pulse length are circuit inputs. Another circuit input is a clock selection input. When the clock selection input indicates a new output clock signal, different from the then current output clock signal, should be output by the circuit, the circuit provides a means for switching to output the new output clock signal. In switching to output the new output clock signal, the circuit prevents the occurrence of the output clock signal ever having a pulse shorter than the normal pulse length of the then current output clock signal, whether the then current output clock signal is the first clock signal or the second clock signal.