Abstract: A first reception processing unit performs a process of receiving a first signal transmitted on a first transmission line, a second reception processing unit performs a process of receiving a second signal transmitted on a second transmission line, and an output speed control unit controls output speeds of the first signal and the second signal subjected to the reception process. A system switching unit selects and outputs the first signal or the second signal subjected to a reception process, and an output processing unit performs a process for output to another apparatus on the output from the system switching unit. A reception side clock output unit outputs a clock signal giving a processing timing of each process, and a clock frequency control unit adjusts a frequency of the clock signal giving the processing timing to the output processing unit.

Abstract: Multi-input downconversion mixers, systems, and methods are provided with input switching in the intermediate frequency or baseband domain. One illustrative mixer embodiment includes: multiple differential pairs of transistors and multiple pairs of switches. Each differential transistor pair has their bases or gates driven by a differential reference signal, their emitters or sources connected to a common node having a current or voltage driven based on a respective one of multiple receive signals, and their collectors or drains providing a product of the differential reference signal with the respective one of the multiple receive signals. Each of the switch pairs selectively couples differential output nodes to the collectors or drains of a respective one of the multiple differential pairs, enabling the differential output nodes to convey an output signal that is a sum of products from selected ones of the multiple differential pairs.

Abstract: A method includes connecting inputs of a first plurality of interpolation branches to a first clock signal, connecting inputs of a second plurality of interpolation branches to a second clock signal, and connecting inputs of a third plurality of interpolation branches to a third clock signal. The method also includes combining outputs of the first plurality of interpolation branches, the second plurality of interpolation branches, and the third plurality of interpolation branches to produce an output clock signal and adjusting a phase of the output clock signal by connecting an input of an interpolation branch of the third plurality of interpolation branches to the second clock signal.

Abstract: A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

Abstract: A phase shifter capable of improving phase accuracy by a simple method is provided. The phase shifter includes a hybrid coupler circuit including inductors with mutual inductances, an amplifying circuit, an impedance matching circuit provided between the hybrid coupler circuit and the amplifying circuit. The impedance matching circuit includes a first resistance element connected to an output node of the hybrid coupler circuit, a capacitance element connected between the first resistance element and the ground line in series, another inductor connected in parallel with the first resistance element, and a second resistance element provided between the inductor and the ground line in series.

Abstract: Phase effect interference is determined at a listening location between signals from at least two audio objects; and a modified position is computed for at least one of the audio objects such that the determined phase effect interference at the listening location is altered as a result of the modified position. For each audio object for which the position is modified at least phase of at least one frequency component of the respective signal is adjusted in correspondence with the modified position so as to eliminate the determined phase effect interference. The signals from the at least two audio objects are formed after this adjusting; and then the formed signals are provided to a sound system comprising multiple audio transducers so as to render the formed signals at the listening position where the phase effect interference is eliminated during rendering.

Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.

Abstract: A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

Abstract: A power signal source may provide current to a transmit coil to support wireless power transmission. The power signal source may include one or more modulators in parallel that may be phase delayed by an angle with respect to one another. The phase delay angle allows for adjustment of the magnitude of the current. The current provided to the transmit coil may be independent of the load of the transmit coil.

Abstract: A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a triggering unit configured to generate a pair of second reference clocks from the pair of first reference clocks, a pulse detector configured to generate a duty detection signal based on a phase difference between the pair of second reference clocks, a correction code generator configured to generate a reference correction code based on the duty detection signal, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

Abstract: According to one embodiment, a semiconductor device includes: an inverter gate circuit which inverts and outputs a logic level of an input signal, the inverter gate circuit includes a constant current source and a switch unit which are connected in series between a first power supply wiring and a second power supply wiring, and, according to the control signal, the switch unit switches real values of a gate length and a gate width of a switch transistor configured by a transistor to which a current outputted from the constant current source is applied among a plurality of transistors.

Abstract: An I2C interface is provided which has a data line and a clock line, the clock line having a first input buffer, and the data line having a second input buffer and an output buffer, the data line being provided for the transmission of a data input signal and a data output signal, the clock line being provided for the transmission of a clock signal, the clock line having a first delay element, and the data line having a second delay element and a third delay element. A method for operating an I2C slave interface is also provided.

Abstract: An apparatus for synchronizing an incoming signal with a clock signal comprises two or more synchronizer circuits, wherein each synchronizer circuit receives the incoming signal and the clock signal. Each synchronizer circuit generates a synchronized signal, wherein the state of each synchronized signal changes on a different phase of said clock signal in response to a change of the state of said incoming signal. A decision mechanism circuit receives the synchronized signals generated by each synchronizer circuit, wherein the decision mechanism circuit determines the output signal in response to the change of the state of the incoming signal. The decision mechanism circuit further comprises a memory element having a state which is set according to a previously detected state of said signal, wherein the output signal is determined according to the state of the memory element.

Abstract: System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.

Abstract: A Phase Interpolator (PI) may be employed as a precisely-controlled delay element in a transmit path, for example in clock forwarded serial links. Methods and circuits are disclosed for estimating a delay needed to correct duty-cycle/and or phase errors of the received clock. These corrections or delta values may be transmitted back to the transmitter side, preferably expressed directly in terms of PI phase codes, for convenient adjustment in the transmitter clock circuitry. Various techniques also are disclosed for measuring and mitigating the effects on PI integral non-linearity.

Abstract: In various embodiments, an active vector generator may comprise a vector component switch and a first amplitude adjustment component in parallel with a second amplitude adjustment component. The first and second amplitude adjustment components may operate with different ranges of amplitude. For example, the first amplitude adjustment component may have a full range of amplitude and the second amplitude adjustment component may have a partial range of amplitude. The vector component switch may operate to receive two signals and route the signals to the various amplitude adjustment components based on the relative magnitudes of the two signals. A benefit of having two amplitude adjustment components with selectable signal pathways is that the all the phase states may be obtained but using less robust and expensive amplitude adjustment components.

Abstract: A current-driven load such as LEDs or laser diodes is driven by a current driver having a two stages (or phases), the outputs of which have ripple which is forced to be out-of-phase with one another. In analog embodiments, an output (ripple or switching) of a master stage hysteresis controller is phase-shifted and scaled, and modulates the input of a slave stage hysteresis controller so that the slave stage pulls into a ripple-canceling phase. In digital embodiments, a faster of the two phases is designated “master”, maximum and minimum thresholds are set, and the slave phase's on time is based on a previous cycle's slave phase ON time, the master stage OFF time and an offset. The slave controller may “lock” to the anti-phase of the master stage (or phase). The ripple currents at the summed output of the master and slave stages substantially cancel.

Abstract: Active directional couplers are provided. In accordance with certain embodiments of the invention, the subject active directional couplers are tunable. The tuning is accomplished via varactors connected to the lines of the active directional couplers. Active directional elements are provided between different lines of the subject active directional couplers to control a signal path between ports of the different lines. The active directional elements are selected from diodes, transistors, inverting amplifiers, non-inverting amplifiers, differential amplifiers, and active baluns. The lines include a phase shift element between the two ports of each line. The phase shift element is selected from a transmission line, a delay line, and a phase shifter. Advantageously, the subject lines do not have to be designed for ideal phase shifting and can be designed at near 90° or near ?/4 values.

Abstract: Multi-protocol driver slew rate calibration systems for calibrating slew rate control signal values are provided. Embodiments include generating, by a first phase rotator, a first clock signal; generating, by the second phase rotator, a second clock signal; initially setting, by a calibration controller, phase selector amounts such that the first clock signal is delayed relative to the second clock signal; determining whether the first clock signal is delayed relative to the second clock signal; if the first clock signal is delayed, changing the second phase selector amount; and if the first clock signal is not delayed, using the first clock signal and the second clock signal to calibrate values of control signals provided to control a slew rate of a calibration clock delay line such that the slew rate of the calibration clock delay line substantially matches a target slew rate.

Abstract: In one embodiment, an apparatus includes a clock generator to generate differential clock signals. The apparatus also includes a distributed polyphase filter to obtain phase-corrected multi-phase clock signals based on the differential clock signals.

Abstract: The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before-make (BBM) circuit ensures that the differential I/Q signals (LO—0, LO—90, LO—180, LO—270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-over-lapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (?) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT—0, LT—90, LT—180, LT—270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (?) equal to zero.

Abstract: A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.

Abstract: A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.

Abstract: The present invention provides a phase shift circuit that supports multiple frequency ranges. The phase shift circuit receives a plurality of control bits and causes a phase shift in a received signal, the phase shift corresponding to a number of time steps, the number depending on the control bits, and the time step is selected from a plurality of different time steps based on a frequency range associated with the received signal.

Abstract: A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.

Abstract: In various embodiments, an active vector generator may comprise a vector component switch and a first amplitude adjustment component in parallel with a second amplitude adjustment component. The first and second amplitude adjustment components may operate with different ranges of amplitude. For example, the first amplitude adjustment component may have a full range of amplitude and the second amplitude adjustment component may have a partial range of amplitude. The vector component switch may operate to receive two signals and route the signals to the various amplitude adjustment components based on the relative magnitudes of the two signals. A benefit of having two amplitude adjustment components with selectable signal pathways is that the all the phase states may be obtained but using less robust and expensive amplitude adjustment components.

Abstract: A phase interpolation circuit based on injected passive capacitances and an inductance for forming a resonator. The circuit conducts at least a first reference signal having a first phase component and a second reference signal having a second phase component shifted from the first phase component. By selectively switching the first reference signal and/or the second reference signal through one or more capacitances, an interpolated third signal having a third phase component between the first phase component and the second phase component can be generated. An inductor is connected with one or more of the capacitances for forming a resonant circuit to boost the signal level of the interpolated third signal. By utilizing resonance, an improved signal-to-noise ratio may be obtained for the interpolated third signal. An additional amplification stage, secondary to the resonant circuit, may be incorporated for further amplifying the signal level of the interpolated third signal.

Abstract: A method for estimating inter-channel delay and an apparatus for estimating inter-channel delay and an encoder are provided by the embodiments of the present invention. The method includes: obtaining signal sound field information from a cross-correlation function and a cumulative cross-correlation function of synthetic signals of left and right sound channels respectively; obtaining adjustment information of the cumulative cross-correlation function according to the sound field information that is respectively obtained; adjusting the cumulative cross-correlation function by using the adjustment information, so as to obtain the adjusted cumulative cross-correlation function; and determining a time corresponding to a maximum value in the adjusted cumulative cross-correlation function as an inter-channel delay. Therefore, the delay between the signals of the left and right sound channels can be estimated correctly, so as to improve the stability of the synthetic stereo sound field.

Abstract: A phase generating apparatus generates an output clock having a desired phase according to a digital signal. The apparatus includes a phase selecting unit and a phase generating unit. The phase selecting unit selects one of a plurality of input clocks according to a portion of bits of the digital signal to generate a reference clock. Each of the input clocks respectively has a difference phase. The phase selecting unit divides the frequency of the reference clock, and selectively delays the frequency-divided reference clock according to another portion of bits of the digital signal to generate the output clock.

Abstract: Systems and methods are disclosed for improving the accuracy of phase spacing of multiphase clocks. In one example, method includes receiving a reference clock having a first frequency and sampling the reference clock with a plurality of multiphase clocks having a second frequency to generate a plurality of samples. The second frequency is a non-integer multiple of the first frequency. The method also includes detecting transitions of the reference clock occurring between the samples generated from a plurality of pairs of the multiphase clocks and counting the transitions to generate a transition count for each pair of the multiphase clocks. The method also includes summing a set of the transition counts to generate a measured phase for a first multiphase clock, calculating a reference phase for the first multiphase clock, and generating a phase skew value for the first multiphase clock based on the measured phase and the reference phase.

Abstract: A stabilized quadrature RC/CR phase shifting network for generating quadrature RF and microwave signals. The network uses offset biasing of postamplifiers following the phaseshifter to fine tune quadrature-phase, and further uses an output quadrature-phase detector to stabilize quadrature-phase with negative feedback by using the quadrature-phase error signal to drive the quadrature-phase fine tuning control. In an alternative embodiment, the stability of quadrature-phase can be enhanced without the output quadrature-phase detector by making the quadrature-phase fine tuning control dependent upon the amplitude-difference negative feedback error signal.

Abstract: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

Abstract: An error amplification circuit includes an integrated circuit and a phase compensation capacitor. The integrated circuit includes an error amplifier to amplify a difference between a predetermined reference voltage and an input feedback voltage for output; a current generator circuit to generate a bias current for supply to the error amplifier; a phase compensation resistor; a bias-current control terminal; and a phase compensation terminal connected to an output terminal of the error amplifier via the phase compensation resistor. The phase compensation capacitor is connected to the phase compensation terminal, the phase compensation capacitor being provided outside the integrated circuit.

Abstract: System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.

Abstract: In a case where two constant envelope signals corresponding to an input signal are generated through analog signal processing, variation in detection sensitivities of amplitudes of those signals is suppressed. At least one of a mixer (24) for detecting an amplitude of a first intermediate signal S1 and a mixer (26) for detecting an amplitude of a second intermediate signal S2 detects an amplitude of a given reference signal, and sampling hold circuits (36, 38) hold a voltage related to those amplitudes. Then, detection sensitivities of the mixer (24, 26) are corrected based on the held voltage.

Abstract: A current-driven load such as LEDs or laser diodes is driven by a current driver having a two stages (or phases), the summed outputs of which have ripple which is forced to be out-of-phase with one another. In analog embodiments, an output (ripple or switching) of a master stage hysteresis controller is phase-shifted and scaled, and modulates the input of a slave stage hysteresis controller so that the slave stage pulls into a ripple-canceling phase. In a digital embodiment, a faster of the two phases is designated “master”, maximum and minimum thresholds are set, and the slave phase's on time is based on a previous cycle's slave phase ON time, the master stage OFF time and an offset. The slave controller preferentially “locks” to the anti-phase of the master stage (or phase) and the ripple current at the summed output substantially cancels.

Abstract: An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; loop filters for generating and transmitting respective DC voltage feedback signals; current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.

Abstract: A signal processing circuit includes: a phase modulating path arranged to adjust a phase component of an input signal to generate an adjusted phase component such that a phase difference of the input signal falls within a target phase difference range; and an amplitude modulating path arranged to exchange a sign of an amplitude component of the input signal corresponding to the phase component to generate an adjusted amplitude component when the phase modulating path adjusts the phase component.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A differential signal generation circuit includes: an inverter array configured to sequentially invert an input signal to generate a plurality of delayed signals; and a phase mixer configured to mix a phase of a first delayed signal and a phase of a second delayed signal among the plurality of delayed signals at a preset mixing ratio to generate a first differential signal. The first delayed signal has a first delay from the input signal and the second delayed signal has a second delay from the input signal. The differential signal generation circuit is configured to generate a third delayed signal having a third delay from the input signal corresponding to a medium of the first and second delays, and the third delayed signal is further delayed to generate a second differential signal.

Abstract: In a case where two constant envelope signals corresponding to an input signal are generated through analog signal processing, variation in detection sensitivities of amplitudes of those signals is suppressed. At least one of a mixer (24) for detecting an amplitude of a first intermediate signal S1 and a mixer (26) for detecting an amplitude of a second intermediate signal S2 detects an amplitude of a given reference signal, and sampling hold circuits (36, 38) hold a voltage related to those amplitudes. Then, detection sensitivities of the mixer (24, 26) are corrected based on the held voltage.

Abstract: An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.

Abstract: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

Abstract: A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.

Abstract: A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: A signal processing circuit includes: a phase modulating path arranged to adjust a phase component of an input signal to generate an adjusted phase component such that a phase difference of the input signal falls within a target phase difference range; and an amplitude modulating path arranged to exchange a sign of an amplitude component of the input signal corresponding to the phase component to generate an adjusted amplitude component when the phase modulating path adjusts the phase component.

Abstract: A signal processing circuit includes: a first operation circuit for receiving a phase component of an input signal, and generating an adjusted phase component and at least one weighting factor according to the phase component of the input signal; a second operation circuit, coupled to the first operation circuit, for receiving the adjusted phase component and converting the adjusted phase component into a frequency component corresponding to the adjusted phase component; a third operation circuit, coupled to the first operation circuit, for receiving an amplitude component of the input signal, and adjusting the amplitude component according to the at least one weighting factor to generate an adjusted amplitude component; and a fourth operation circuit, coupled to the second operation circuit and the third operation circuit, for generating an output signal according to the frequency component and the adjusted amplitude component.

Abstract: A reference signal is split and input to first and second variable phase shifters 10, 20. The first and second variable phase shifters output to first and second inputs 31, 32 respectively of a phase comparator 30. Initially, the first and second variable phase shifters 10, 20 are preferably set to the same phase. The first and second phase shifters are then aligned, e.g. by adjusting the calibration of one or both of the phase shifters so that the phase comparator 30 indicates that they output the same phase. The phase of the first phase shifter 10 is then adjusted by one step and a phase delay section 60 is placed between the output of the second phase shifter 20 and the second input 32 of the phase comparator 30. The first and second phase shifters 10, 20 are then aligned again.

Abstract: A clock circuit with delay functions includes a first clock tree and a delay module. The first clock tree provides a first clock signal and includes a first clock root and a plurality of first sub-trees. The delay module is coupled to the first clock root or a designated sub-tree among the plurality of first sub-trees for delaying the first clock signal. The delay module includes at least two delay segments, wherein each delay segment includes a delay and a connection net. The delay time caused by each delay segment is substantially the same.