Abstract: A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

Abstract: Embodiments of a circuit, system, and method are disclosed. A beam switch to a beam with a beam configuration from another beam with another beam configuration is detected. In response to the detected beam switch: a tuner setting is determined for an antenna tuner of an antenna element in an antenna array which transmits the first beam with the first beam configuration based on the first beam configuration, the tuner setting associated with the first beam configuration; and an indication of the tuner setting is provided to an impedance matching system of the antenna tuner to compensate for a mismatch between an impedance of the antenna element and impedance of one or more other radio frequency (RF) components of an RF front-end having the antenna element and antenna tuner.

Abstract: A battery cell monitoring circuit comprises an input pin; a reset command detection circuit comprising an integrator circuit coupled to the input pin; a counter circuit coupled to an output terminal of the integrator circuit; and a one-shot circuit coupled to an output terminal of the counter circuit; a logic gate coupled to an output terminal of the one-shot circuit; and a reset circuit coupled to the logic gate.

Abstract: A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

Abstract: A quadrature phase clock generator includes a tunable polyphase filter and a phase detector. The tunable polyphase filter is configured to receive an input clock signal and generate four quadrature phase clock signals. The phase detector is coupled to receive at least two of the four quadrature phase clock signals and generate a control signal adapted to tune the polyphase filter based on the received quadrature phase clock signals. Further, the phase detector is configured to provide the control signal to the polyphase filter in a feedback loop. Based on the control signal from the phase detector, the tunable polyphase filter generates four tuned quadrature phase clock signals as output phase clock signals.

Abstract: An error path characteristic model correction control unit determines the deviation of the phase of an actual transfer function from the phase of an error path characteristic model, from a cross correlation between an error signal output from a microphone and a signal in which the error path characteristic model is applied to a noise cancellation sound to be output and a cross correlation between the error signal and a signal in which a transfer function having a phase characteristic deviating by +90 degrees from the phase characteristic of the error path characteristic model is applied to the noise cancellation sound. The error path characteristic model correction control unit then corrects the error path characteristic model so that the determined deviation is reduced to ±90 degrees.

Abstract: A variable gain amplifier having stabilized frequency response for widened gain control range. A resistor-capacitor compensation network is provided between two differential current input ports and corresponding emitter nodes of cross-coupled four transistors in the variable gain amplifier to desensitize the gain control voltages to the system noise and provide compensation to the VGA frequency response when the differential gain control voltage varies the gain setting, yielding a substantially stabilized frequency response over a ?3 dB bandwidth ranging from 1 GHz to 60 GHz with a widened gain control range up to 12 dB without increasing power consumption.

Abstract: A multiport amplifier MPA is provided with an N-input input network, INET, an N-output output network, ONET, and N amplifiers interposed between the INET and the ONET, the MPA comprising N wanted signal paths and N.(N?1) null signal paths wherein N is divisible by 2, half of the N amplifier paths comprise a signal inversion with respect to the other half of the N amplifier paths, the INET and the ONET each comprise one or more quadrature hybrid couplers, QHC, wherein a pair of amplifier paths is arranged between the output of a first QHC in the INET and the input of a second QHC at the ONET, and each signal inversion is arranged in one of the amplifier paths of each pair of amplifier paths such that the ideal amplitude gain of at least one of the N.(N?i) null signal paths is zero.

Abstract: Methods and systems for controlling variable gain amplifiers include setting a phase at a phase shifter in each of multiple of front-ends of a phased array transceiver, accounting for a constant phase shift of a phase-invariant variable gain amplifier. A gain is set at the phase-invariant variable gain amplifier in each of the multiple front-ends to perform tapering of beam pattern side lobes. A resistance in the phase-invariant variable gain amplifier is set to provide a phase shift that is independent of gain.

Abstract: Disclosed is a differential driver circuit including an input module to receive an input signal and split the input signal into high and low components, a first level shifter to receive the high signal component and output a high side input signal to a high side driver, a delay module to receive the low signal component and output a low side input signal to a low side driver, and a multi-voltage domain phase detector to measure a phase difference between the high side input signal and the low side input signal to provide feedback to the input module and output a phase adjusted output signal to match a first delay timing of the first level shifter.

Abstract: A circuit comprises a phase combiner and four output ports. The phase combiner adds an in-phase positive input and a quadrature positive input to obtain an in-phase positive output, adds an in-phase negative input and a quadrature negative input to obtain an in-phase negative output, adds the in-phase negative input and the quadrature positive input to obtain a quadrature positive output, and adds the in-phase positive input and the quadrature negative input to obtain a quadrature negative output. The four output ports, are respectively configured to output the in-phase positive output, the in-phase negative output, the quadrature positive output, and the quadrature negative output.

Abstract: A phase frequency detector realizes a highly linear conversion from noise-shaped ?? modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.

Abstract: Clock alignment circuitry may include phase comparator circuitry with a first input terminal that receives as first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree. The phase comparator circuitry may compare the first and second clock signals and generate different control signals based on the first and second clock signals. The integrated circuit may further include phase interpolator circuitry that generates an output clock signal based on at least one of the control signals received from the phase comparator circuitry. Edges of the generated output clock signal may align with edges of either the first clock signal or the second clock signal.

Abstract: A method of feedforward phase recovery on a data stream is described. Phase estimation base points are calculated, at a phase detector, for each block of the received data stream. A current phase, at a phase interpolator, between two phase estimation base points. Data stream delays within the phase detector are matched with delays within the phase interpolator.

Abstract: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.

Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.

Abstract: According to one embodiment, a low frequency drive control circuit for use with an inductive load comprises a comparator configured to receive a high frequency signal at a first input and a smoothly varying low frequency signal for modulating the high frequency signal at a second input. The comparator is further configured to produce a pulse width modulated output of the low frequency drive control circuit for use in generating a smoothly varying low frequency load current in the inductive load. In one embodiment, the inductive load can comprise a DC brushed motor. In one embodiment, the low frequency drive control circuit can be implemented as part of an integrated circuit further comprising a switching circuit configured to use the pulse width modulated output of the comparator to generate the smoothly varying low frequency load current, which may be a substantially sinusoidal load current, for example.

Abstract: Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer.

Abstract: An apparatus includes an integration circuit that integrates values of one of a data center and a data edge of input data, based on clock signals, a sampling circuit that samples another at the data center and a data edge of the input data, based on clock signals, a first determination circuit that determines a data value of an integration value of the integration circuit, a second determination circuit that determines a data value of a sampling value of the sampling circuit, a phase detection circuit that detects phase information of the input data, based on a data value determined by the first determination circuit and the second determination circuit, and a phase adjusting circuit that adjusts a phase of a reference clock so as to track a phase of the input data, in accordance with the phase information, so as to output as the clock signals.

Abstract: A phase excursion/carrier wave frequency excursion compensation device has a signal dividing unit, a preprocessing compensation circuit, post-processing compensation circuits, a signal combination unit, a correction amount calculation unit, and a signal correction unit. The preprocessing compensation circuit and the post-processing compensation circuits calculate a phase compensation amount with respect to the input signal, and output the phase compensation amount, and a compensation circuit output signal such that the input signal can be compensated accordingly. The signal combination unit acquires compensation circuit output signals from the post-processing compensation circuits and, based on order of input to the signal dividing unit, outputs rearranged signals.

Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.

Abstract: There is provided a frequency synthesizer capable of improving phase noise. A sinusoidal signal with a frequency set by a frequency setting part is output as a digital signal from a set signal output part, and the digital signal is D/A-converted. A difference between a sinusoidal signal with a frequency corresponding to an output frequency of a voltage controlled oscillating part and a sinusoidal signal output from a D/A converting part is amplified by a differential amplifier, and an amplified signal is input via an A/D converting part to a means for extracting a phase difference between the aforesaid sinusoidal signals. A voltage corresponding to a signal being the result of integration of the phase difference is input as a control voltage to the voltage controlled oscillating part. Then, a gain of the differential amplifier is set larger than a maximum value of phase noise degradation of the A/D converting part, whereby the phase noise degradation of the A/D converting part is cancelled.

Abstract: A clock phase shift detector circuit may include a phase detector for generating a phase signal based on a phase difference between first and second clock signals. A current mirror having a first, a second, and a third integrator may be coupled to the phase detector, whereby the first integrator integrates the first clock signal and generates a first voltage, the second integrator integrates the first clock signal and generates a second voltage, and the third integrator integrates the phase signal and generates a third voltage. A first comparator receives the first and the third voltage, and generates a first control signal. A second comparator receives the second and the third voltage, and generates a second control signal. The first and second control signals may detect a change between the phase difference of the first and the second clock signal and an optimized phase difference.

Abstract: An interpolation circuit includes: a generation circuit that generates interpolation data from a plurality of pieces of input data, using an interpolation coefficient, among input data inputted in time series including a data point and a transition point; a detection circuit that detects that the input data lacks at the data point; and a coefficient circuit that changes the interpolation coefficient for each given data interval, and skips a position for changing the interpolation coefficient to the transition point when the detection circuit detects the lack of the input data.

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract: A transmitter, a base station device, and a method for aligning a signal output from a transmitter are provided. The transmitter is connected to a first antenna, and the first antenna detects a second test signal transmitted by a second antenna that is connected to another transmitter. The transmitter includes: a signal generating unit, which generates a first test signal; a directional coupler, which receives the first test signal and the second test signal; and a signal processing unit, which measures a timing difference between the first test signal and the second test signal, and uses the measured timing difference to control signal generation, so as to align a signal transmission delay between the two transmitters. Thus, closed-loop detection and an adaptive rectification mechanism for transmission signals of multiple transmitters can be implemented, and accuracy of aligning a signal at each transmitting antenna is improved.

Abstract: A stepper motor driver system includes: a digital signal controller configured to digitally synthesize synthesized analog voltage signals that will induce a desired velocity of a stepper motor when applied to a pair of stepper motor windings; and voltage amplifiers, communicatively coupled to the digital signal controller, configured to amplify the synthesized analog voltage signals to produce amplified analog voltage signals and to output the amplified analog voltage signals; where the digital signal controller is configured to synthesize the analog voltage signals by affecting at least one of a phase or an amplitude of each of the analog voltage signals as a function of the desired velocity of the stepper motor.

Abstract: A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.

Abstract: A phase locked loop that includes a signal generator arranged to output a feedback signal, a first phase detector arranged to detect a phase difference between the feedback signal and a reference signal and to output a first phase detect signal in dependence on that detection, a second phase detector arranged to detect a phase difference between the feedback signal and a delayed version of the reference signal or between the reference signal and a delayed version of the feedback signal and to output a second phase detect signal in dependence on that detection, and an adjustor. The adjustor is arranged to determine which of the first and second phase detect signals commutes first and to alter the frequency of the feedback signal in dependence on the result of the determination.

Abstract: Embodiments of the invention may be directed to a continuous analog phase shifter for radio frequency (RF) signals, which can be integrated on a CMOS process or another compatible process where inherent process-dependent passive components such as inductors and capacitors may have low quality factors. Insertion loss degradation for a given amount of phase shift may be compensated by using an active compensation circuit/device that smartly controls negative resistance generated from the compensation circuit/device to cancel out finite resistance of a network, leading to very small insertion loss variation. According to an example aspect of the invention, improved phase linearity and increased phase shift for a given size may be obtained by incorporating the compensation circuit/device. Thus, example analog phase shifters in accordance with example embodiments of the invention may have one or more of low insertion loss variation, small size, and good phase linearity over more than a 360 degree phase shift.

Abstract: An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector.

Abstract: Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed.

Abstract: A system includes a transmitter circuit and a receiver circuit that are coupled together through transmission lines. The transmitter circuit generates an early timing signal, a nominal timing signal, and a late timing signal. A multiplexer circuit selects between the early and the late timing signals based on a data signal to generate an encoded output signal that encodes the data signal. The nominal timing signal and the encoded output signal are transmitted through the transmission lines to the receiver circuit. The receiver circuit samples the encoded output signal in response to the nominal timing signal to generate even and odd sampled data signals. Complementary timing signals can be transmitted through transmission lines on opposite sides of the encoded output signal to provide crosstalk cancellation.

Abstract: A digital phase detector circuit and corresponding monitor and control logic is presented. The digital phase detector has two storage elements, where the data input of the first storage element receives a first clock signal and the data input of the second storage element receives a second clock signal. A time shifter shifts the second clock signal by a shift period, and transmits the shifted signal to the clock input of the storage elements. The signals applied to the data inputs are transmitted from the storage elements when the clock input receives the shifted second clock signal from the time shifter. A monitor and control module samples the data output from the storage elements after each shifted second clock signal is transmitted by the time shifter. The sampling of the output data provides the data used to determine the time relationship between the first and the second clock signals.

Abstract: Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information. A phase estimation unit (PEU) determines a phase error in the over-sampled data streams; and a phase retrieval unit sets the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.

Abstract: A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

Abstract: A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may include a controller configured to drive the first multiplexer and the second multiplexer respectively with a first select signal and a second select signal, a detection module configured to detect a phase difference between the first output signal and the second output signal and to generate a corresponding digital phase shift signal, the detection module including a phase comparator, and a Time-Digital converter circuit coupled thereto and having logic elements configured to generate the digital phase shift signal, and a logic circuit connected to the detection module and configured to process the digital phase shift signal and to generate a signal indicative of a control executed.

Abstract: An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; loop filters for generating and transmitting respective DC voltage feedback signals; current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.

Abstract: Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer.

Abstract: Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed.

Abstract: A method, system and device for eliminating intra-pair skew are disclosed. The method includes: measuring a phase difference between the received differential signals as a transmission delay difference; and compensating delays of the differential signals using the transmission delay difference, to eliminate intra-pair skew of the differential signals. A phase difference measuring apparatus is used to measure a phase difference between the differential signals as the transmission delay difference, so that the transmission delay difference may be adjusted according to the phase difference. Therefore, the procedure for eliminating intra-pair skew is effectively simplified, and the effect of adjusting the transmission delay difference is improved.

Abstract: A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

Abstract: A phase generator includes a delay element configured to receive an input signal and delay the input signal by a predetermined amount to develop a delayed version of the input signal, a logic element configured to receive the input signal and the delayed version of the input signal, the logic element configured to produce a signal dependent on a phase difference between the input signal and the delayed version of the input signal, a circuit configured to generate a reference signal, and a comparator configured to receive an output of the logic element and the reference signal. The comparator is configured to generate a control signal that is dependent on the difference between the output of the logic element and the reference signal, where the control signal is applied to the delay element to determine the delay applied to the input signal.

Abstract: A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may include a controller configured to drive the first multiplexer and the second multiplexer respectively with a first select signal and a second select signal, a detection module configured to detect a phase difference between the first output signal and the second output signal and to generate a corresponding digital phase shift signal, the detection module including a phase comparator, and a Time-Digital converter circuit coupled thereto and having logic elements configured to generate the digital phase shift signal, and a logic circuit connected to the detection module and configured to process the digital phase shift signal and to generate a signal indicative of a control executed.

Abstract: A phase splitter uses digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

Abstract: A signal processing circuit includes: a first operation circuit for receiving a phase component of an input signal, and generating an adjusted phase component and at least one weighting factor according to the phase component of the input signal; a second operation circuit, coupled to the first operation circuit, for receiving the adjusted phase component and converting the adjusted phase component into a frequency component corresponding to the adjusted phase component; a third operation circuit, coupled to the first operation circuit, for receiving an amplitude component of the input signal, and adjusting the amplitude component according to the at least one weighting factor to generate an adjusted amplitude component; and a fourth operation circuit, coupled to the second operation circuit and the third operation circuit, for generating an output signal according to the frequency component and the adjusted amplitude component.

Abstract: A reference signal is split and input to first and second variable phase shifters 10, 20. The first and second variable phase shifters output to first and second inputs 31, 32 respectively of a phase comparator 30. Initially, the first and second variable phase shifters 10, 20 are preferably set to the same phase. The first and second phase shifters are then aligned, e.g. by adjusting the calibration of one or both of the phase shifters so that the phase comparator 30 indicates that they output the same phase. The phase of the first phase shifter 10 is then adjusted by one step and a phase delay section 60 is placed between the output of the second phase shifter 20 and the second input 32 of the phase comparator 30. The first and second phase shifters 10, 20 are then aligned again.

Abstract: A waveform generating circuit includes a constant current circuit that supplies a constant current through a power source; a current mirror circuit that flows an output current that is n times an input current; and a switching circuit that switches a flowing direction of the current in the constant current circuit between the current mirror circuit and the output terminal according to the logical level of the rectangle input signal. The waveform generating circuit generates a triangle wave having a falling slope waveform that is n times the rising slope. On the other hand, the waveform generating circuit that receives an inverted signal of the signal generates a triangle wave and its voltage is compared with another in the comparator to generate an output signal.

Abstract: Embodiments related to configurable differential lines are disclosed herein.

Abstract: A voltage control circuit is disclosed. A power factor corrector may utilize the control circuit to provide power factor correction for an AC induction motor. An AC induction motor system may combine the power factor correct with an AC induction motor.