Abstract: To provide a voltage control device that includes a power supply circuit that supplies electric power to an input terminal of a controlled circuit, a power supply voltage control circuit that controls the power supply voltage to be supplied from the power supply circuit to the controlled circuit, on the basis of the clock signal to be supplied to the controlled circuit, and a clock generation circuit that receives a power supply that is the internal voltage to be applied to a second internal circuit region at a second wiring distance from the input terminal, and generates the clock signal on the basis of the internal voltage, the second wiring distance being longer than a first wiring distance at which a first internal circuit region is located in the controlled circuit, the first wiring distance and the second wiring distance being wiring distances in the controlled circuit from the input terminal.

Abstract: Methods and apparatus for supplying radio frequency (RF) power to a process chamber. An RF generator is configured with a capability to operate with an RF power output independent of a reference frequency or synchronize the RF output power to the reference frequency. A clock ramp is used to change an RF power output frequency of the RF output power to match the reference frequency when the frequencies are in an unlocked state. When the RF power output frequency reaches the reference frequency, the RF power output can be locked to the reference frequency.

Abstract: Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Abstract: Systems and methods to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a first current mode digital-to-analog converter (DAC) configured to multiply an input signal with a first current having a first amplitude to generate a first signal. The device can further include a second current mode DAC configured to multiply the input signal with a second current having a second amplitude to generate a second signal. The second amplitude can be less than the first amplitude. The device can further include a mixer configured to multiply the second signal with a clock signal to generate a third signal. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.

Abstract: Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Abstract: The present application relates to a method and apparatus for implementing a radar array including a gate bias source for providing a first variable voltage, a back gate well control for providing a second variable voltage, and a field effect transistor having a drain, a source, a gate and a back gate well control, the field effect transistor being further configured to couple an alternating current radar signal between the drain and the source and to adjust a phase of the alternating current radar in response to first variable voltage applied to the gate and the second variable voltage applied to the back gate well control.

Abstract: Various embodiments provide for phase interpolators with phase adjusters to provide step resolution, which can be used with a circuit such as a data serializer/deserializer circuit. In particular, for some embodiments, a phase interpolator is coupled to a phase adjuster, where the combination of the phase interpolator and the phase adjuster is configured to interpolate between phases in phase adjustment steps at a phase adjustment step resolution. For such embodiments, the phase adjustment step resolution of the steps is achieved by controlling the phase interpolator and the phase adjuster.

Abstract: A switch comprising a first switching circuit assembly having a first pair of identical diodes in first anti-series configuration. The first switching circuit assembly constructed and arranged to cancel capacitance change wherein capacitance increases in a first diode of the first pair of identical diodes and, simultaneously, capacitance decreases in a second diode of the first pair of identical diodes with a first selectively applied radio frequency (RF) voltage input. The switch comprises a second switching circuit assembly having a second pair of identical diodes in second anti-series configuration. The second switching circuit assembly constructed and arranged to cancel capacitance change wherein capacitance increases in a first diode of the second pair of identical diodes and, simultaneously, capacitance decreases in a second diode of the second pair of identical diodes with a second selectively applied RF voltage input. A system and method are also provided.

Abstract: Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Abstract: A phase shifter (60) is provided corresponding to an antenna element constituting an array antenna and is configured to change a phase of a radio frequency signal to be transmitted or received by a corresponding antenna element. The phase shifter (60) includes a first distributor (61) configured to distribute the radio frequency signal input thereto into a plurality of first distributed signals having mutually different phases; second distributors (62) provided corresponding to the first distributed signals, the second distributors each being configured to distribute a corresponding one of the first distributed signals into a plurality of second distributed signals having mutually different amplitudes; a controller (63) configured to control on/off of the second distributed signals; and a combiner (64) configured to combine the second distributed signals that are controlled on by the controller (63).

Abstract: Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

Abstract: Apparatuses and methods for quadrature signal generation are provided. An example includes a quadrature signal generator. The quadrature signal generator is configured to generate, based on a received differential signal, a plurality of quadrature clock signals at a same frequency as that of the received differential signal. The quadrature signal generator is also configured to provide the plurality of quadrature clock signals to a memory system.

Abstract: Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Abstract: A ring oscillator includes first to fourth current-controlled delay circuits configured to allow a delay time to be changed depending on a magnitude of sink current, wherein the first to fourth current-controlled delay circuits are arranged symmetrically to each other about a square.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: A ring oscillator includes: (i) one or more current sources each connected to a supply voltage source; and (ii) oscillation elements connected in series in a ring configuration each element including: (a) first and second input terminals; (b) first and second output terminals; (c) first and second inverters receiving input signals from the first and second input terminals, respectively, and providing output signals on the first and second output terminals, respectively; and (d) third and fourth inverters, each having an input terminal and an output terminal, wherein the input terminals of the third and fourth inverters are coupled to the first and second output terminals of the oscillator element, respectively, wherein the output terminals of third and fourth inverters are coupled to the second and first output terminals of the oscillator element, respectively, and wherein each of first, second, third and fourth inverters are coupled to the supply voltage source through the current sources.

Abstract: An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.

Abstract: This application discusses techniques for providing a power-on reset (POR) circuit. The techniques take advantage of the small size of active devices, consume very little current and can use a native NMOS transistor to provide a stable reference over temperature and voltage variations.

Abstract: A phase interpolator includes a current generating circuit, a current controlling circuit and a signal generating circuit, wherein the current generating circuit is arranged to generate a current; and the current controlling circuit is arranged to generate a control signal to the current generating circuit to control a current value of the current. The signal generating circuit includes a capacitor, wherein the signal generating circuit generates a phase interpolation signal by using the capacitor to receive the current, wherein a phase of the phase interpolation signal is varied according to the current.

Abstract: A test bench for turbomachine comprising: an installation zone for turbomachine; an active system for attenuating the noise emissions produced by the turbomachine. The active system includes an attenuation zone with emitters such as loudspeakers; a first microphone placed downstream of the turbomachine; and a second microphone placed downstream of the attenuation zone. The system reduces the turbomachine waves on the basis of the measurements from the first microphone and from the second microphone. The invention also proposes a method for attenuating the noise emissions from the turbomachine tested in the test bench.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: An example phase interpolator includes: a ring oscillator having a plurality of delay stages and a plurality of injection switches, each of the plurality of injection switches responsive to a differential reference clock signal and a first differential control signal; a supply control circuit configured to provide a regulated supply voltage to the ring oscillator in response to a first component of a second differential control signal; and a ground control circuit configured to provide a regulated ground voltage to the ring oscillator in response to a second component of the second differential control signal.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value. The enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction.

Abstract: An absorptive switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common terminal and one or more ports, any of which may be selectively coupled to the common terminal by closing an associated path switch; non-selected, unused ports are isolated from the common terminal by opening an associated path switch. Between each path switch and a port are associated shunt switches for selectively coupling an associated signal path to circuit ground. Between each path switch and a port is an associated absorptive switch module. Each absorptive switch module includes a resistor coupled in parallel with a switch. The combination of the resistor and the switch of the absorptive switch module is placed in series with a corresponding signal path from each port to the common terminal, rather than in a shunt configuration.

Abstract: A circuit for generation of a reference voltage for an electronic system, which circuit comprises at least one digital buffer (U21, U31, U32, U41, U51), a low pass filter (R21, C21; R31, C31; R41, C41; R51, C51) and an operational amplifier (OA21, OA31, OA41, OA51)), which circuit is adapted to revive an input in the form of a bandgap reference voltage into the digital buffer, which digital buffer is adapted to receive a digital input from a Pulse Width Modulated (PWM) signal, which digital buffer is adapted to generate an output signal adapted to be fed to the low pass filter, which output signal after filtration is adapted to be fed to a positive input terminal of the operational amplifier, which operational amplifier comprises a feedback circuit, which feedback circuit comprises at least one capacitor (C22, C32, C44, C54) adapted to be connected from an output terminal of the operational amplifier towards a negative input terminal of the operational amplifier so as to form an integrator, wherein the feedba

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: A multichannel UWB-based radar life detector includes a transmitting antenna and three receiving antennas for forming three radar echo signal channels.

Abstract: A circuit comprises a phase combiner and four output ports. The phase combiner adds an in-phase positive input and a quadrature positive input to obtain an in-phase positive output, adds an in-phase negative input and a quadrature negative input to obtain an in-phase negative output, adds the in-phase negative input and the quadrature positive input to obtain a quadrature positive output, and adds the in-phase positive input and the quadrature negative input to obtain a quadrature negative output. The four output ports, are respectively configured to output the in-phase positive output, the in-phase negative output, the quadrature positive output, and the quadrature negative output.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: Certain aspects of the present disclosure provide apparatus for producing an output signal that may have a phase difference with respect to an input signal. One example phase shifting circuit for producing such an output signal generally includes a transmission line having first and second points, an impedance connected with a node and with a reference voltage level, a first switch connected with the first point of the transmission line and with the node, and a second switch connected with the second point of the transmission line and with the node, wherein a first signal input to the first point of the transmission line has a phase difference with a second signal output from the second point based on one or more properties of the transmission line when the first and second switches are open.

Abstract: A poly-phase filter receives inphase input signals I and ? and quadrature input signals Q and Q, and provides inphase output signals Iout and Iout and quadrature output signals Qout and Qout. The capacitance of each variable capacitor connected to the terminals providing inphase output signals Iout and Iout is and the capacitance of each variable capacitor connected to the terminals providing quadrature output signals Qout and Qout, are different in value, and preferably by twice a predetermined value. This is because adjustment to the capacitance values may be made to each set of variable capacitors by the predetermined value.

Abstract: The problem was that the noise superimposed on a touch electrode via the human body can incur erroneous touch determination by a touch sensor circuit. The invention provides a semiconductor device including a terminal to which a touch electrode may be coupled; a source voltage drop circuit generating a constant voltage; a phase shift circuit generating a phase shifted clock in response to a first clock and a phase control signal; and a switching circuit to which the constant voltage is supplied. The switching circuit generates drive pulses for applying the constant voltage to the terminal in response to the phase shifted clock. The phase shift circuit varies the phase of the drive pulses based on the phase control signal.

Abstract: A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.

Abstract: An integrated circuit for phase shifting a radio frequency signal, wherein the integrated circuit comprises at least one phase shifter comprising: at least one input for receiving a radio frequency signal, a voltage variable element; and a plurality of active devices operably coupled to the voltage variable element and arranged to receive a variable control voltage. The plurality of active devices comprise at least two active devices coupled in a common base arrangement and arranged to receive the radio frequency signal with the voltage variable element coupling the emitter contacts or source contacts of the at least two active devices, such that a variable control voltage applied to the voltage variable element adjusts a phase of the radio frequency signal.

Abstract: A multiple gate semiconductor structure is disclosed having a thin segment of semiconductor with first and second major surfaces that are opposite one another, a first gate on the first major surface of the segment, a second gate on the second major surface of the segment opposite the first gate, a first differential input coupled to the first gate, and a second differential input coupled to the second gate. Preferably the semiconductor structure is symmetrical about a plane that extends through the thin segment between the first and second major surfaces. When a first voltage of a first polarity is applied to the first input and a second voltage of the same magnitude as that of the first voltage but of opposite polarity is applied to the second input, a virtual ground is established in the structure near its center of the segment.

Abstract: A phase interpolator includes an adaptively biased phase mixer, phase control circuitry and an adaptive bias generator. The adaptively biased phase mixer has mixing transistor circuitry configured to provide an output phase signal in response to a plurality of phase control signals, a bias current, and a number of phase input signals offset in phase from one another. The adaptively biased phase mixer further has adjustable bias transistor circuitry configured to adjust the bias current provided to the mixing transistor circuitry in response to an adaptive bias signal.

Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of capacitors, a first input for a clock signal, a second input for a phase shifted clock signal, a reference input for a reference signal, and an output. The phase interpolator is configured to provide at its output an interpolated, modulated phase information signal by switching, dependent on a modulation information, a first number of the capacitors between the first input and the output, a second number of the capacitors between the second input and the output, and a third number of the capacitors to the reference input.

Abstract: Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.

Abstract: An interpolator includes interpolation cells. Each interpolation cell includes a first driving unit and a second driving unit. The first driving unit includes a first pulling-up circuit for selectively coupling an output terminal to a high voltage, a first pulling-down circuit for selectively coupling the output terminal to a low voltage, and a pair of first switches for selectively enabling/disabling the first pulling-up circuit and the first pulling-down circuit. The second driving unit includes a second pulling-up circuit for selectively coupling the output terminal to the high voltage, a second pulling-down circuit for selectively coupling the output terminal to the low voltage, and a pair of second switches for selectively enabling/disabling the second pulling-up circuit and the second pulling-down circuit. Driving capabilities of the first and second pulling-up circuits are not all equal, and/or driving capabilities of the first and second pulling-down circuits are not all equal.

Abstract: The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90°. This feature is useful in clock/data recovery where the 90° “jumps” can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads.

Abstract: A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.

Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.

Abstract: One object is to provide a front-end module with a shared output terminal wherein an input impedance is readily matched and an insertion loss is suppressed. In accordance with one aspect, the front-end module 10 includes an input terminal, output terminals, a first filter circuit that passes signals in a first passband, a second filter circuit that passes signals in a second passband, a switch that is disposed between the input terminal and the first and second filter circuits and selectively connects the input terminal to the first and second filter circuits, and a matching circuit. The second filter circuit includes phase shifters.

Abstract: A phase interpolator includes an adaptively biased phase mixer, phase control circuitry and an adaptive bias generator. The adaptively biased phase mixer has mixing transistor circuitry configured to provide an output phase signal in response to a plurality of phase control signals, a bias current, and a number of phase input signals offset in phase from one another. The adaptively biased phase mixer further has adjustable bias transistor circuitry configured to adjust the bias current provided to the mixing transistor circuitry in response to an adaptive bias signal.

Abstract: A digital-to-analog conversion apparatus and a current-mode interpolation buffer thereof are provided. The current-mode interpolation buffer comprises a current source, a first differential transistor pair, a second differential transistor pair and an output stage. The current source outputs a first current and draws a second current. Wherein, the amperages of the first current and the second current are dependent on a digital code. First differential transistor pair generates a first differential current according a first rough voltage, an analog voltage and the first current. Second differential transistor pair generates a second differential current according a second rough voltage, the analog voltage and the second current. Output stage generates the analog voltage according to the first differential current and the second differential current, where the analog voltage belongs to a rough range from the first rough voltage to the second rough voltage.

Abstract: In one embodiment, a phase interpolator with a phase range of n degrees, where 0<n?360, and having m reference signals, where m?2, and a control signal as input, and producing an output signal with a phase within the phase range using one or more of the m reference signals based on a control code provided by the control signal. The phase interpolator comprises one or more circuits configured to: divide the phase range of n degrees into k sections, wherein k>m; and for each of the k sections, select a relative gain of one or more weights assigned to the one or more reference signals, respectively, with respect to the control code provided by the control signal.

Abstract: A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.

Abstract: A phase interpolator, multi-phase interpolation device, interpolated clock generating method and multi-phase clock generating method is related to a phase interpolator with a differential to single-ended converter, a load circuit, two differential pairs, a current source and at least a switch pair. By using the switch pair to control the current providing for the two differential pairs from the current source, and through regulating the load of the load circuit and/or the reference current of the current source, the intersection of a first signal and a second signal is in the overlap duration between a first input clock and a second input clock, so that uniform multi-phase output clock signal can be interpolated.

Abstract: An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption.