Abstract: This disclosure provides systems and apparatuses for reducing flicker noise in output signals provided by a radio frequency (RF) amplifier. In some implementations, the RF amplifier may include a bias generator to provide one or more bias signals to control operating points of devices and circuits of the RF amplifier. The bias generator may include a feedback circuit to generate a current to attenuate flicker noise within the bias generator. In some implementations, the feedback circuit may receive a bias voltage and may generate the current based on a frequency of the bias voltage.

Abstract: An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched.

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

Abstract: A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.

Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range.

Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

Abstract: A method includes, in at least one aspect, selecting a first phase signal, where the first phase signal concurrently enables a first pair of switching elements; selecting a second phase signal, where the second phase signal concurrently enables a second pair of switching elements; and generating an interpolated phase signal by providing a connection between a switching element of the first pair of switching elements to an output node and providing a connection between a switching element of the second pair of switching elements to the output node.

Abstract: The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before-make (BBM) circuit ensures that the differential I/Q signals (LO—0, LO—90, LO—180, LO—270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-over-lapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (?) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT—0, LT—90, LT—180, LT—270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (?) equal to zero.

Abstract: Disclosed are a phase shifter, a wireless communication apparatus, and a phase control method in which power consumption is reduced. A phase shifter includes a 90° step phase shifter (17) and a 45° phase shifter (18) and adds phase information to two baseband signals to be output to an orthogonal modulator. The 90° step phase shifter (17) contributes to adding any one of phases 0°, 90°, 180°, and 270° to the baseband signals according to a first control signal. The 45° phase shifter (18) contributes to adding one of phases 0° and 45° to the baseband signals according to a second control signal. A phase shifter (8) performs replacement of component signals of one of the baseband signals with component signals of the other of the baseband signals and inversion of polarities of the component signals.

Abstract: A method for providing an interpolated output signal includes, in at least one aspect, receiving a plurality of phase signals applying each phase signal of the plurality of phase signals to switching elements of a first set of switching elements receiving a plurality of select signals, applying an asserted select signal to a first switching element of a second set of switching elements to provide a connection between a first switching element of the first set of switching elements and a first output terminal, and applying the asserted select signal to a second switching element of the second set of switching elements to provide a connection between a second switching element of the first set of switching elements and a second output terminal.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: A phase interpolator is provided that, in one implementation, includes first and second interpolator modules, each having an output in communication with an output node. The first interpolator includes an input to receive a first plurality of input phase signals, and a selector to select one or more of the first plurality of input phase signals for interpolation at the output node of the phase interpolator. The second interpolator module includes an input to receive a second plurality of input phase signals, and a selector to select one or more of the second plurality of input phase signals for interpolation at the output node of the phase interpolator. Each of the selected ones of the first plurality of input signals and each of the selected ones of the second plurality of input signals are included in an interpolated output signal.

Abstract: Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: Embodiments of an interpolator system and method are disclosed. One embodiment of an interpolator system, among others, includes an interpolator having first and second output terminals providing output signals; a comparator coupled to the first and second output terminals and configured to detect a peak voltage level of the output signals and compare the peak voltage level with a reference voltage level; and an impedance element coupled to the comparator and the first and second output terminals, wherein the comparator is configured to provide a control signal to the impedance element to change the impedance of the impedance element to set a voltage variation of the output signals.

Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and a first and second output terminals, a first differential amplifier circuit includes first and second MOS transistors with a common source connected to a first tail current source, first and second load resistors and a first non-doped MOS transistor connected between the first and second resistors and the second power supply terminal. A second differential amplifier circuit includes third and fourth MOS transistors with a common source connected to a second tail current source, third and fourth load resistors and a second non-doped MOS transistor connected between the third and fourth load resistors and the second power supply terminal.

Abstract: Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.

Abstract: Methods and apparatus are provided for maintaining a desired slope of clock edges in a phase interpolator using an adjustable bias. The disclosed phase interpolator comprises at least one delay element to generate at least two interpolation signals each having an associated phase and a variable slope unit associated with each of the at least two interpolation signals, wherein a slope of each of the variable slope units is controlled by a bias signal and is varied based on a data rate of the interpolation signals. The slope is varied to maintain a desired slope of clock edges associated with the interpolation signals. The slope can be maintained, for example, between approximately the value of the delay between consecutive clock edges and twice the value of the delay between consecutive clock edges.

Abstract: A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an output and a second portion of the first modulated input signal to an internal balancing node. The weighting system also is configured to steer a first portion of the second modulated input signal to the output and a second portion of the second modulated input signal to the balancing node. The first portion of the first and second modulated input signals are summed at the output to provide an interpolated output signal having a phase angle that is between the first and second phase angles.

Abstract: A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Abstract: A clock and data recovery system for detecting and resolving meta-stability conditions is provided. The clock and data recovery system includes a phase detector having logic configured to detect a meta-stability condition and to generate an output signal to mitigate the condition. The system can also include a time varying gain adjustment portion. This portion includes a gain control logic configured to determine and adjust system gain during reception of an incoming data stream. The system further includes a phase interpolator having increased linearity. The phase interpolator has a plurality of first branches having a differential transistor pair, a switch, and a current source, coupled between a first output and a first supply voltage and a plurality of second branches having a differential transistor pair, a switch, and a current source, coupled between a second output and the first supply voltage. The phase interpolator can also include an integrator portion.

Abstract: A gain amplifier with quadrature phase compensation circuit is disclosed.

Abstract: An apparatus for producing a clock output signal, having an input for receiving an input signal containing a phase information item; a clock generator for producing a multiplicity of clock signals whose phases are respectively shifted from one another by a predetermined amount; and a weighting and mixing circuit for weighting each of the multiplicity of clock signals based on the phase information item contained in the input signal. The weighting and mixing circuit is also for mixing the weighted clock signals in order to produce a clock output signal whose phase essentially matches the phase represented by the phase information item.

Abstract: In a &pgr;/2 phase shifter, first and second signals and first and second inverted signals are produced based on input signals. The first and second signals have the same amplitude and are out of phase from each other, and the first and second inverted signals respectively correspond to the first and second signals with their respective phases inverted. A first output signal is produced by adding the first signal and the second signal, and a second output signal is produced by adding the first signal and the second inverted signal. Since the first and second signals have the same amplitude, the first output signal and the second output signal respectively correspond to diagonal lines of a rhombus formed by a vector representing the first signal and a vector representing the second signal. Accordingly, the phase difference between the first and second output signals of the &pgr;/2 phase shifter is accurately set to &pgr;/2 even when the phase difference between the first and second signals is not &pgr;/2.

Abstract: The present invention provides a technique for selective cancellation of the 2nd-order or 3rd-order nonlinearity of a transistor. Any nonlinearity is a function of the bias voltage of a transistor. In many cases, this function is such that, at a particular bias voltage, nonlinearity is zero. The invention provides a bias circuit that generates the optimum bias voltage for a transistor at which its selected nonlinearity is zero. Mathematically, the nonlinearity can be represented by a sum of multiple components where some components have negative sign. The components are proportional to the DC currents of the transistor at bias voltages differing by a small amount. The bias circuit includes bias transistors that are scaled versions of the main transistor. Each bias transistor generates a DC current representing one of the components. The currents are combined according to the signs of the respective components to form a DC signal proportional to the selected nonlinearity.

Abstract: An apparatus for producing a clock output signal, having an input for receiving an input signal containing a phase information item; a clock generator for producing a multiplicity of clock signals whose phases are respectively shifted from one another by a predetermined amount; and a weighting and mixing circuit for weighting each of the multiplicity of clock signals based on the phase information item contained in the input signal. The weighting and mixing circuit is also for mixing the weighted clock signals in order to produce a clock output signal whose phase essentially matches the phase represented by the phase information item.

Abstract: Method and system for providing a signal with a controllable zero crossing time value. The system provides first and second two-sided triangular wave signals, identical but shifted by a selected fraction f·T of a period T of either triangular signal, and forms a weighted sum of the signals, weighted by A and 1−A, respectively, with 0≦A≦1. In each of two time regions within a period T, a zero crossing time of the sum varies linearly with choice of the value A.

Abstract: A termination structure is shown whereby multiple transmission lines designed to have the same intrinsic impedance and same delay are driven from a central node. The central node is driven by a driver and calibration resistor connected in series to produce a drive impedance that is equal to the parallel combination of the intrinsic impedances of the multiple transmission lines. At the other end of the multiple transmission lines is a receiver and a feedback circuit. The feedback circuit provides a modest amount of positive feedback from the output of the receiver to the input of the receiver. This positive feedback prevents the output of the receiver from being affected by small reflections and perturbations that result from mismatches among the multiple transmission lines.

Abstract: A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllable capacitive load coupled to either the input or the output of the phase interpolator circuit. The controllable capacitive load is designed to add or subtract capacitance to the adjustable phase interpolator.

Abstract: An electronic phase shifter splits an input signal into two signals whose amplitudes are set by a weighting circuit controlled by a phase shift control signal. Each of the two outputs of the weighting circuit is loaded with an RLC resonator, one tuned to a frequency lower than that of the input signal and one tuned to a frequency higher than that of the input signal. The loaded outputs are recombined in a vector summing network to synthesize the required phase shifted output signal. This technique permits implementation on a monolithic integrated circuit (MIC) with high gain at high frequencies (e.g. 10 GHz). It also allows a large dynamic range of operation and a large (i.e., greater than 90 degrees) controllable phase shift. This is accomplished without the use of variable reactance elements or any other components external to the MIC.

Abstract: A programmable phase comparator comprises a switch circuit operable in response to first and second signals to provide an output signal representative of the phase relationship of the first and second signals. A reference signal is applied to the switch circuit to offset the output signal. A phase adjustment adjusts the phase relationship of the first and second signals so that the offset output signal is representative of a null condition. The switch circuit preferably is a Gilbert multiplier having a current source, an impedance means, and a transistor circuit connected between the current source and the impedance means. The transistor circuit has first and second inputs for receiving the first and second signals. The reference signal is input between the transistor circuit and the impedance means and is connected to an output. The output provides the output signal having a value based on the reference signal and the phase relationship of the first and second signals.

Abstract: An active pixel sensor cell array in which a two-stage amplifier amplifies the output of each cell. The two-stage amplifier design reduces fixed pattern noise in the image data generated by reading the array, by providing increased gain for the output of each cell without impractically increasing the size and complexity of each cell. For each column of cells of the array, one part of the two-stage amplifier for each cell is shared by all cells of the column, and another part of the two-stage amplifier for each cell is included within the cell itself. Preferably, each cell includes only NMOS transistors (no cell includes a PMOS transistor). In preferred embodiments, a differential amplifier within each cell is the primary stage of the cell's output amplifier, PMOS load circuitry including a secondary output amplifier stage is shared by all cells of the column, and the two amplifier stages for each cell together comprise an op amp.