Abstract: A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit (22 and 24) for receiving an input signal and a symmetry circuits (205 and 210) advantageously configured to provide an output signal exhibiting a symmetrical rising and falling edge waveform in response to the received input signal. An integrated power source (Is) provides current to a common node (N1) in which current is advantageously steered to each half circuit (22, 205 and 24, 210) to reduce voltage variation on the common node during voltage transition of the input signal, hence, reducing current fluctuation from the current source.

Abstract: A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors 104,106 and 105, 107 provide loads for the differential transistor 102 and 103. Transistors 111-114 and 121-122 together with an amplifier 130 provide biasing for the delay device. The amplifier 130 has a non-inverting input set to VDD−VCLAMP. As configured, a constant output voltage swing from VDD to VDD−VCLAMP is provided at the outputs VOUT+ and VOUT− of the delay device, independent of a control voltage VCTL used to set the tail current. The NMOS load transistor 104, as opposed to the PMOS transistor 4 in FIG. 1, does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current.

Abstract: A VCO (voltage-controlled oscillator) that can realize stable oscillation operation over a broad frequency range with a low level of jitter. The VCO includes a plurality of basic cells having differential input/output, and a center frequency adjustment circuit. The plurality of basic cells are serially connected in a ring. Each basic cell includes a circuit constituted by two delay circuits and an adder circuit, the delay times of the two delay circuits being each independently determined by the center frequency adjustment circuit. The output amplitude of each of the basic cells is controlled to a fixed value. In the adder circuit, the output of one of the delay circuits is multiplied by an addition proportion coefficient, following which the outputs of both delay circuits are added. In this way, the delay time for each basic cell can be set over a broad range.

Abstract: A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors 104,106 and 105,107 provide loads for the differential transistor 102 and 103. Transistors 111-114 and 121-122 together with an amplifier 130 provide biasing for the delay device. The amplifier 130 has a non-inverting input set to VDD−VCLAMP. As configured, a constant output voltage swing from VDD to VDD−VCLAMP is provided at the outputs VOUT+ and VOUT− of the delay device, independent of a control voltage VCTL used to set the tail current. The NMOS load transistor 104, as opposed to the PMOS transistor 4 in FIG. 1, does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current.

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.

Abstract: A method and apparatus for matching rise time and fall time in two differential signals. The apparatus includes a system that includes an scaled summer, a reference voltage generator, a comparator, and a storage device. The scaled summer receives two input signals and generates an instantaneous scaled sum of the two input signals. The reference voltage generator generating a reference voltage. The comparator compares the scaled summer output signal and the reference voltage and generates a comparison signal. The storage device stores the comparison signal. The stored comparison signal is usable to adjust one of the rise time and the fall time of both of the two input signals to match one of the fall time and the rise time of the two input signals.

Abstract: A delay circuit for a ring oscillator includes a first electric potential line, a pair of output lines, a pair of two first transistors arranged between the first electric potential line and the pair of output lines, respectively, a second electric potential line, and a pair of two second transistors arranged between the second electric potential line and the pair of output lines, respectively. Respective gates of the first transistors are connected to the pair of output lines, respectively, the first transistors, and the second transistors are connected to each other center-symmetrically, and the output lines are connected to a third electric potential line. Such a circuit can easily realize a differential gain of more than or equal to 1 and an in-phase gain of less than or equal to 1.

Abstract: A programmable delay circuit employs a relatively slow conventional silicon emitter-coupled transistor pair and a relatively fast silicon/germanium heterojunction emitter-coupled transistor pair. The bases of both transistor pairs are driven by an input signal to be delayed. The collectors of transistors of both pairs are linked to a voltage source through a pair of load resistors, with an output signal appearing across the collectors of both transistor pairs. A current source draws complementary adjustable load currents through the two transistor pairs. Although the sum of the two load currents is a constant, the relative amount of load current drawn though the two transistor pairs is adjustable.

Abstract: A precision wide-range variable delay system whose delay is independent of process, voltage, and temperature variations. A delay controller supplies a voltage, that is independent of process, voltage, and temperature variations, and that is used in a delay line to set the amount of delay through all individual delay elements cascaded together inside of the delay line. The number of cascaded delay elements determines the maximum delay of the delay system. An output voltage controller regulates the output voltage swing of the output from the delay system for stability of the delay over voltage variations. The desired delay from the system is variable and is determined by the user. The pre-delay timing relationships of multiple signals, that are delayed, is maintained by the delay system.

Abstract: Voltage controlling/oscillating device comprises a terminal for setting the delay rate in the delay unit and the delay interpolator. Clock signal whose phase is inverted by the inverting gate is inputted into a first input terminal of the delay interpolator and into the delay unit. The delay unit delays the signal by d1 and inputs into second input terminal of the delay interpolator. Oscillation frequency control voltage is fed into a terminal of the delay interpolator through an oscillation frequency control terminal of the device. Delay control voltage is fed into a terminal of the device in order to control a propagation delay rate in the delay unit and the delay interpolator. The delay rate in a delay unit and a delay interpolator can be adjusted by a delay control voltage.

Abstract: A delay cell comprises a fast delay stage including a differential amplifier for connection to a differential input. A slow delay stage includes a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount. A current source develops a bias current. A current switch is connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage. An output circuit is connected to the fast and slow delay stages for developing a differential output delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current.

Abstract: The present invention provides a method for controlling a timing of a digital component having an impedance-input terminal. The method includes determining an impedance level present at the impedance-input terminal, and delaying the timing of the digital component based on the impedance level. The present invention also provides a digital component and a system, where the digital component includes an impedance-input terminal and an impedance matching circuit that is capable of determining an impedance level present at the impedance-input terminal. The digital component also includes a delay circuit that is capable of delaying a timing of the digital component based on the impedance level.

Abstract: A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllable capacitive load coupled to either the input or the output of the phase interpolator circuit. The controllable capacitive load is designed to add or subtract capacitance to the adjustable phase interpolator.

Abstract: A delay circuit includes a reference voltage generation circuit for generating a reference voltage which changes to a prescribed voltage level during the operation of a comparison circuit, an RC delay stage for integrating an input signal, a comparison circuit for comparing an output signal from the RC delay stage and the reference voltage of the reference voltage generation circuit, and a logic circuit for buffering the output signal of the comparison circuit. Since the reference voltage is pulled to a prescribed voltage level only during a comparison operation, the reference voltage may accurately be maintained at the prescribed voltage level only when necessary free from the influence of other circuits and noises. A delay circuit with reduced current consumption which is capable of changing an output signal with fixed delay time independently of the influence of fluctuations of the power supply voltage and the input logical threshold value of a logic circuit in a succeeding stage is provided.

Abstract: A delay circuit (7) delays a transfer signal (V1) transferred through a transfer signal line (1) by the first delay time (dt1) to generate the first delayed signal (V9) and delays the first delayed signal (V9) by the second delay time (dt2) to generate the second delayed signal (V10). The second current mirror differential amplifier circuit (11) receives the transfer signal (1) and the second delayed signal (V10), whose ground terminal is connected to the first delayed signal line (9). On the other hand, the first current mirror differential amplifier circuit (14) also receives the transfer signal (V1) and the second delayed signal (V10), whose power-supply terminal is connected to the first delayed signal line (9). In response to a rise of the input signal (V1), the circuit (14) starts its operation to change a level of an output signal (V6) from "L" level to "H" level, remaining thereafter.

Abstract: Signal-controlled oscillator structures are provided that are substantially insensitive to temperature, supply voltages and fabrication processes. They include a plurality of time-delay stages that are serially connected in a closed feedback ring and each of the stages includes an amplifier, at least one capacitor and at least one signal-controlled impedance element that couples the capacitor to the amplifier. Accordingly, the frequency of the oscillator is a function of a control signal applied to the impedance elements of the stages. In an oscillator embodiment, each of the amplifiers is a differential pair of transistors, the capacitor comprises first and second capacitors and the signal-controlled impedance element comprises first and second coupling transistors that each couples a respective one of the capacitors to a different side of the differential output.

Abstract: A low-voltage, low-jitter voltage controlled oscillator according to the invention includes a plurality of delay units electrically connected in series to form a closed loop circuit. Each delay unit has a symmetric differential structure constituted by a plurality of MOS FETs. Furthermore, only two transistors are stacked between the power source and ground. Thus, the low-voltage, low-jitter voltage controlled oscillator can operate at low voltage, and can not be affected by the variation of the power source voltage.

Abstract: A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal to an error control signal derived from an error amplifier or in the alternative to a disable signal. The output of the comparator is latched on until a reset signal is received. The reset signal is produced when the ramp signal is discharged below a predetermined level. The programmable delay circuit is useful in a secondary side post regulator to control a totem pole driver. The totem pole driver in turn controls a switching device coupled to a voltage on a secondary winding.

Abstract: A ring oscillator comprising a cascade connection of two or several delay stages (31 to 33), wherein each delay stage comprises two differential pairs of two transistors (Q1, Q2; Q3, Q4; Q5, Q7). In the ring oscillator, the collector resistors and the emitter resistor of a traditional ring oscillator are replaced by coils (L1 to L6) in all stages.

Abstract: A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal with a disable signal or an error control signal derived from an error amplifier. The comparator latches the output on until a reset signal is received. The reset signal is produced when the ramp signal is discharged below a predetermined level. The programmable delay circuit is useful in a secondary side post regulator to control a grounded totem pole driver. The totem pole driver in turn controls a switching device coupled to a voltage on a secondary winding.

Abstract: A voltage-controlled oscillator (VCO) includes a plurality of differential amplifiers which are ring-connected. Each amplifier includes two FETs, the sources of which are coupled. The coupled sources of each amplifier are connected to series-connected FETs which is part of a current mirror circuit. The series-connected FETs decrease transconductance of (i.e., increase impedance against) fluctuations in a power supply voltage, so that fluctuations in current flowing in the amplifiers are lessened. Thus, power-supply rejection ratio of the VCO increases and fluctuations in the VCO frequency are lessened.

Abstract: An array oscillator circuit is disclosed herein. The array oscillator circuit includes a plurality of ring oscillators, each ring oscillator having a plurality of buffer stages for generating output signals on a like plurality of oscillator output ports. Interconnections are provided between each of the plurality of ring oscillators and at least one other of the plurality of ring oscillators such that the plurality of ring oscillators oscillate at identical frequencies and such that the output signals on the each ring oscillator's plurality of oscillator output ports have a phase offset from the signals generated on corresponding ones of the other ring oscillator's oscillator output ports. A multiplexer provides an electrical connection to a selected one of the plurality of oscillator output ports of the plurality of ring oscillators.

Abstract: A series delay generator for imposing a programmable delay on the timing edges of an incoming waveform is disclosed. The magnitude of the imposed delay is proportional to the value of a binary programming word. The series delay generator is implemented as a series of delay cells, each of which can be programmed into two delay states, a maximum delay and a minimum delay. The magnitude of the maximum and minimum delays can be set and calibrated using an analog tuning voltage. The series of delay cells can be segmentized in order to provide pipelined operation. The series delay generator is therefore capable of processing more than one timing edge at a time, permitting its minimum reprogramming time to span and even exceed the maximum delay span of the generator.A delay cell is also disclosed that uses a differential input and a digitally controlled current balance circuit to advance and retard the zero crossings of the incoming waveform and its inverse.

Abstract: A delay circuit having standby state and active state and designed to output at least one signal obtained by delaying an input signal. The delay circuit comprises a storage circuit and at least one amplifier circuit. In operation, the storage circuit receives an input signal, generates a first voltage when the input signal is inverted, and generates a second voltage from a difference between the first voltage and a first supply voltage. The amplifier circuit amplifies the difference between the first voltage and the second voltage.

Abstract: Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, S1, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit.

Abstract: A voltage-controlled phase shift apparatus having an unlimited range for producing an output signal that varies in phase from an input signal by a predetermined phase difference. The phase shift apparatus includes a first delay circuit coupled to receive the input signal, the first delay circuit for outputting a first intermediate signal that is .alpha. degrees out of phase with the input signal, a second intermediate signal that is .beta. degrees out of phase with the first intermediate signal, a third intermediate signal that is 180 degrees out of phase with the first intermediate signal, and a fourth intermediate signal that is 180 degrees out of phase with the second intermediate signal.

Abstract: A timing generator, which is simple in construction and is capable of high speed operation with excellent linearity and low power consumption, wherein a delayed timing signal is generated by delaying an input timing signal. The generator comprises a switch having one end thereof connected to a first voltage source and which is controlled by the input timing signal, a current source provided between the other end of the switch and a second voltage source; a charge injection circuit generating a voltage signal which is turned ON and OFF in accordance with the input timing signal; a capacitor provided between the output end of the charge injection circuit and the other end of the switch; and a comparator generating a delayed timing signal by comparing the voltage at the other end of the switch with a desired voltage, wherein the delay time of the delayed timing signal is adjusted by controlling either the voltage outputted from the charge injection circuit or the current from the current source.

Abstract: An inverting delay circuit including a differential amplifier (OTA) having a non-inverting input (+) coupled to ground, an inverting input (-) and an output; an input capacitor (Cin) which is coupled between an input of the inverting delay circuit and the inverting input (-) during a first switching phase (.phi.), and which is discharged during a second switching phase (); a feedback capacitor (Cx) which is coupled between the output and the inverting input (-) of the differential amplifier (OTA) during the first switching phase (.phi.), and between the inverting input (-) and ground during the second switching phase (); and an output capacitor (Co) which is coupled between the output and the inverting input (-) during the second switching phase (), the output capacitor (Co) being discharged during the first switching phase (.phi.), a charge on the feedback capacitor (Cx) being transferred to the output capacitor (Co) during the second switching phase ().