Abstract: A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.

Abstract: A method for sensing temperature in memory die, memory die and memory with temperature sensing function are provides. The memory die includes at least one temperature monitoring for outputting a temperature status in the memory die; a temperature sensor, arranged in the memory die for sensing an operation temperature in the memory die; and a control logic unit, coupled to the temperature sensor for receiving the operation temperature and coupled to the temperature monitoring pin. The control logic unit compares the operation temperature and a threshold value received from outside of the memory die to generate a comparison result, and outputs the temperature status through the temperature monitoring according to the comparison result.

Abstract: A skew sensor for detecting skew between two input signals is provided. The skew sensor includes at least two skew detectors. The first skew detector receives either a first clock signal or a second clock signal as a first input signal, and the other one of the first clock signal and the second clock signal delayed by a first delay difference induced by one or more delay elements as a second input signal. The second skew detector receives either the first clock signal or the second clock signal as the first input signal, and the other one of the first clock signal and the second clock signal optionally delayed by a second delay difference induced by one more delay elements, wherein the second delay difference is different from the first delay difference, as the second input signal. Skew is measured between the first clock signal and the second clock signal.

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.

Abstract: A phase-locked loop circuitry (200) having low variation transconductance design comprises a voltage controlled oscillator structure (308) to provide an output signal (Fosc) having an oscillation frequency. The voltage controlled oscillator structure (308) comprises a voltage-to-current converter circuit (312) and a current controlled oscillator circuit (314). The voltage-to-current converter circuit is designed with a low variation transconductance. The voltage-controlled oscillator circuit (200) has a characteristic curve being independent of different PVT (processes, supply voltages and temperature) conditions to ensure that the phase-locked loop circuitry (200) is stable under different PVT condition.

Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.

Abstract: A clock generator that outputs multiphase clocks comprises a ring oscillator that includes a plurality of inverter circuits connected in a circular pattern and outputs, from the inverter circuits, clocks provided with a delay time based on a delay control signal, a first frequency divider that divides an injection clock by a first value and outputs the clock as a reference clock, a second frequency divider that divides one of the multiphase clocks by a second value and outputs the clock as a comparison clock, and a frequency comparator that compares frequencies of the reference clock and the comparison clock and output the delay control signal based on a result of the comparison. The ring oscillator is configured to adjust the delay time based on the delay control signal.

Abstract: Digital control of a crystal oscillator is implemented in a manner that allows frequency accuracy to be traded off dynamically with power consumption. The oscillator transitions between a less accurate/lower power mode and a high accuracy/higher power mode smoothly without requiring any external clock source during the transition. Power consumption is optimized because the crystal oscillator provides the clock source during transitions between the power modes and no other clock source is needed for these transitions. The system can also optimize the startup time and steady state power consumption independently.

Abstract: Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.

Abstract: A method and a system are provided for synchronizing a signal. A keep out window is defined relative to a second clock signal and an edge detection signal is generated that indicates if an edge of a first clock signal is within the keep out window. The edge detection signal may be filtered. An input signal is received in a domain corresponding to the first clock signal and a delayed input signal is generated. Based on the edge detection signal or the filtered edge detection signal, either the input signal or the delayed input signal is selected, to produce an output signal in a domain corresponding to the second clock signal.

Abstract: A driver circuit includes first switch, configured to selectively couple a first driving node to a power supply node, and a second switch, configured to selectively couple a second driving node to a ground node. The first driving node is coupled to each transistor in a first set of PMOS transistor(s) and the second driving node is coupled to each transistor in a second set of NMOS transistor(s). The driver circuit is configured to propagate a first drive signal in a first direction along an electrical path for biasing the first and second sets of transistors when the transistors in the first set, before receiving the first drive signal, are in a first state. The driver circuit is configured to propagate a second drive signal in a second direction along the path when the transistors in the first set, before receiving the second drive signal, are in a second state.

Abstract: A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs.

Abstract: A delay circuit includes a first inverter in which a delay time of rising is larger than a delay time of falling, and a second inverter which is connected in series with the first inverter and in which a delay time of falling is larger than a delay time of rising. Transistors for each of the first and second inverters are connected in series between a power supply terminal and a ground terminal.

Abstract: A delay circuit is coupled to an electromagnetic coil and includes a power input end coupled to a first end of the electromagnetic coil, a first switch module coupled to the power input end, a second switch module coupled to a second end of the electromagnetic coil, a first timing module coupled to the power input end and the first switch module, and a second timing module coupled to the power input end and the second switch module. The second switch module turns on when the power input end supplies power. The first timing module is configured to count time when the power input end supplies power and turns on the first switch module after a first predetermined time. The second timing module is configured to count time after the first switch module turns on and turns on the second switch module after a second predetermined time.

Abstract: A semiconductor integrated circuit includes a rupture instructing pulse generation unit configured to generate a rupture instructing pulse signal in response to a fuse rupture command signal and an address; a first anti-fuse rupture unit configured to perform an operation for rupturing a first anti-fuse during an enable period of the rupture instructing pulse signal, and generate rupture information of the first anti-fuse; a pulse shifting unit configured to delay the rupture instructing pulse signal and generate a delayed rupture instructing pulse signal; and a second anti-fuse rupture unit configured to perform an operation for rupturing a second anti-fuse during an enable period of the delayed rupture instructing pulse signal, and generate rupture information of the second anti-fuse.

Abstract: A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal.

Abstract: Disclosed herein is a feed-forward ring oscillator. The feed-forward ring oscillator includes a plurality of delay cells for receiving a first differential input signal pair and a second differential input signal pair, and outputting a differential output signal pair. The delay cells are connected in a ring shape. Each of the delay cells receives a differential output signal pair of a delay cell of a previous stage as a first differential input signal pair and receives a differential output signal pair of a delay cell of a stage before the previous stage as a second differential input signal pair. Each of the delay cells comprises multiple independent gate field-effect transistors.

Abstract: An integrated circuit may include a delay circuit that receives an input signal at a first logic level and produces a delayed output signal at a second logic level at an output terminal. The integrated circuit may include a preset circuit coupled to the delay circuit. The preset circuit may receive the input signal and pre-drive the delayed output signal to an intermediate logic level that lies between the first and second logic levels.

Abstract: A time difference adjustment circuit includes two flip-flop circuits, a delay circuit, and a reset circuit. The delay circuit includes first and second transistors of a first polarity and third and fourth transistors of a second polarity, wherein drains of the first and third transistors are coupled to each other, drains of the second and fourth transistors are coupled to each other, the drains of the first and third transistors and a gate of the fourth transistor are coupled to each other, an input signal is coupled to a gate of the first transistor, an output signal is supplied from the drains of the second and fourth transistors, and first and second reset signals are respectively coupled to gates of the second and third transistors.

Abstract: A digitally controlled delay device includes at least one delay generating gate device, whose propagation delay is controlled by limiting operating current by means of a tail transistor that is controlled by its gate voltage, a gate control voltage control means for controlling the current limiting transistor gate voltage, and a bank of digitally controlled MOSFET transistors in parallel configuration, and the digital control is adapted to switch the transistors to off and to diode mode connection, current feeding means to feed current through the bank of MOSFET transistors, and the voltage over the bank of parallel transistors is used for gate source control voltage of the tail transistors.

Abstract: The present invention relates to a semiconductor circuit including: a delay unit for delaying an input signal by a predetermined time to output the delayed signal; a voltage adjusting unit for charging and discharging voltage according to a level of the input signal; and a combination unit for controlling the charging and discharging operations of the voltage adjusting unit according to signals generated using the level of the input signal and a level of the signal output from the delay unit, and it is possible to effectively remove low level noise and high level noise which are respectively mixed in a high level signal and a low level signal input to the semiconductor circuit.

Abstract: A control voltage generating circuit according to an aspect of the present invention includes: a reference voltage unit that includes a plurality of first transistors of the same conductivity type connected in series between a first power supply and a second power supply, and generates a drain voltage of one of the plurality of first transistor as a reference voltage; and a voltage conversion unit that includes a plurality of second transistors connected in series between the first power supply and the second power supply and having the same conductivity type as that of the reference voltage, supplies the reference voltage to a gate of one of the plurality of second transistors, and outputs a drain voltage of one of the plurality of second transistors as a control voltage.

Abstract: The embodiments of the present invention disclose a delay circuit. The delay circuit comprises an inverter, a load capacitor, and a first voltage clamping module, wherein the first voltage clamping module generates a voltage drop configured to prolong the propagation delay time of the delay circuit as the power supply voltage decreases. The power supply dependent delay circuit may have a much larger propagation delay time at low power supply voltage than it at high power supply voltage at the rising-edge or falling-edge of an input signal.

Abstract: A delay line with cell by cell power down capability and methods of use are provided. The delay cell includes a first gate transistor coupled to a voltage supply, a second gate transistor coupled to ground, and a reset signal provided to at least one of the first gate transistor and the second gate transistor. The reset signal turns the delay cell on and off.

Abstract: Certain embodiments of the invention may include systems, methods, and apparatus for providing an integrated high-speed signal buffer circuit. According to an example embodiment of the invention, a method is provided for driving a clock signal. The method includes configuring a clock driver circuit with a differential clock buffer output connected to one or more clock lines; matching an operational output resistance of the differential clock buffer output approximately with an input impedance associated with the one or more clock lines; receiving a clock reference signal; applying the clock reference signal to inputs associated with the differential clock driver circuit; and driving the one or more clock lines with the differential clock buffer output.

Abstract: A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.

Abstract: The present invention relates to a semiconductor circuit including: a delay unit for delaying an input signal by a predetermined time to output the delayed signal; a voltage adjusting unit for charging and discharging voltage according to a level of the input signal; and a combination unit for controlling the charging and discharging operations of the voltage adjusting unit according to signals generated using the level of the input signal and a level of the signal output from the delay unit, and it is possible to effectively remove low level noise and high level noise which are respectively mixed in a high level signal and a low level signal input to the semiconductor circuit.

Abstract: A non-overlap circuit includes a first delay circuit configured to receive a first input signal and output a first control signal to a driver circuit, sensing circuitry configured to sense a current generated in response to the first control signal coupled through bulk semiconductor of a semiconductor substrate and produce a feedback signal response, and a second delay circuit. The second delay circuit configured to receive the feedback signal from the sensing circuitry and a second input signal and output a second control signal to the driver circuit based on the sensed feedback signal and the second input signal.

Abstract: Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.

Abstract: A bus switch circuit according to an embodiment includes a signal transmission circuit connected between a first terminal and a second terminal. The bus switch circuit includes a first switch element controlled by a first control signal. The bus switch circuit includes a second switch element controlled by a second control signal. The bus switch circuit includes a delay signal generating circuit that outputs a delay signal based on a first signal varying with a first voltage applied to the first terminal and a second signal varying with a second voltage applied to the second terminal. The bus switch circuit includes a control signal generating circuit that outputs the first control signal and the second control signal based on the first signal, the second signal, and the delay signal.

Abstract: An adaptive delay device that provides a delay to a signal based on circuit conditions such as temperature, supply voltage values and/or fabrication processes. The adaptive delay device may respond to circuit conditions by charging a capacitive device to a threshold voltage. A comparator may incorporate the adaptive delay device to provide adaptive timing for the comparator functions thereby attaining improved noise performance and/or reduce power consumption.

Abstract: A system and method for characterizing process variations are provided. A circuit comprises a plurality of inverters arranged in a sequential loop, and a plurality of transmission gates, with each transmission gate coupled between a pair of serially arranged inverters. Each transmission gate comprises a first field effect transistor (FET) having a first channel, and a second FET having a second channel. The first channel and the second channel are coupled in parallel and a gate terminal of the first FET and a gate terminal of the second FET are coupled to a first control signal and a second control signal, respectively.

Abstract: Here, an apparatus is provided. The apparatus comprises a first supply rail, a second supply rail, a first ambipolar transistor (which is coupled to the first supply rail at its drain and which receives a reference voltage at its gate), a second ambipolar transistor (which is coupled to the first supply rail at its drain and which receives an input signal at its gate), a current source (which is coupled between the sources of the first and second ambipolar transistors and the second supply rail), and an output circuit (which is coupled to drain of the first ambipolar transistor). In operation, the output circuit provides an output signal having a frequency that is about twice the frequency of the input signal.

Abstract: An inverter of a delay circuit in a semiconductor integrated device that has a high resistance to an electrostatic discharge. The delay circuit includes at least one inverter. Each inverter has high and low potential parts. The low potential part includes a pair of FETs. A source terminal of one FET is connected to a drain terminal of the other FET at a first common node. The high potential part includes another pair of FETs, with a source terminal of one FET being connected to a drain terminal of the other FET at a second common node. A power supply potential is applied to the first common node when the inverter output becomes a high potential. A ground potential is applied to the second common node when the inverter output becomes a low potential.

Abstract: A high voltage drive circuit includes an edge detector for generating an edge detection signal by detecting edges of a first high side input signal and a first low side input signal, the edge detector providing a high side delay signal and a low side delay signal by delaying the first high side input signal and the first low side input signal, a dead time generator for generating a dead time signal indicating a preset dead time in response to the edge detection signal, and a driver comprising a drive signal generator for providing a high side output signal and a low side output signal by inserting the preset dead time based on the dead time signal into the high side delay signal and the low side delay signal.

Abstract: A control voltage generating circuit according to an aspect of the present invention includes: a reference voltage unit that includes a plurality of first transistors of the same conductivity type connected in series between a first power supply and a second power supply, and generates a drain voltage of one of the plurality of first transistor as a reference voltage; and a voltage conversion unit that includes a plurality of second transistors connected in series between the first power supply and the second power supply and having the same conductivity type as that of the reference voltage, supplies the reference voltage to a gate of one of the plurality of second transistors, and outputs a drain voltage of one of the plurality of second transistors as a control voltage.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: To cancel a delay time that occurs in a delay circuit due to temperature and voltage changes. The delay circuit includes a plurality of first and second inverters that are each composed of an N-channel first transistor and a P-channel second transistor connected in series, and P-channel third transistors that are connected between a first power supply wiring and the input nodes of the second inverters. According to the present invention, the presence of the third transistors cancels characteristic variations of the second transistors included in the respective plurality of inverters even if there are changes in temperature, voltage, etc. Consequently, when temperature, voltage, or the like changes, variations in the amount of delay of the entire delay circuit can be regarded as resulting from characteristic variations of the first transistors.

Abstract: Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.

Abstract: Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage.

Abstract: A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.

Abstract: A delay circuit includes a MOSFET and bias voltage sources. The bias voltage sources apply a voltage difference between the drain and source of the MOSFET. The bias voltage source supplies a source voltage to a source electrode of the MOSFET. The bias voltage source supplies a drain voltage to a drain electrode of the MOSFET. An input signal to be delayed is propagated through the gate of the MOSFET in the gate width direction (y-axis direction).

Abstract: A delay cell for delaying an input data signal to generate an output data signal includes a logic circuit and a bias current generator. The logic circuit is used for processing the input data signal to generate the output data signal. The bias current generator is coupled to the logic circuit for providing a first bias current to the logic circuit to control a delay time of the delay cell based on a process corner at which the delay cell is manufactured in a wafer. The bias current generator includes a first transistor coupled between a first power supply and the logic circuit for steering the first bias current of the logic circuit, wherein the first transistor is biased by a first bias voltage.

Abstract: A dynamic oscillating ring circuit is described, which has multiple non-inverting domino circuits, each having a signal input, a trigger input, inputs for charge state clock and clocked cutoff and an output inverter. A number of the domino circuits are coupled in series, the output of one feeding the input of the next, to form a chain, which form stages of the ring. A number of the stages are coupled in series, the output of one feeding the input of the next, to form the ring. The first domino circuit of said chain receives a logic signal input and a single trigger input for the chain. Within the ring, the output of each stage feeds the input signal to the next stage and is fed back to clock an earlier stage to allow the ring to oscillate.

Abstract: A delay cell for use in a ring oscillator and associated method is provided. The delay cell includes a differential amplifier, a switched capacitance bank, and a Kvco equalizer. The differential amplifier comprises a differential pair, a first load and a second load. The differential pair includes a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The first load is coupled to the positive output terminal, and the second load is coupled to the negative output terminal. The switched capacitance bank has a plurality of controlled capacitor paths selectively connecting to the positive output terminal or the negative output terminal according to a capacitance controlling signal. The Kvco equalizer has an adjustable current source for providing a current to the Kvco equalizer according to a current controlling signal to compensate currents flowing through the first load and the second load.

Abstract: A time-delay buffer having a CMOS transistor and a capacitor is disclosed. The CMOS transistor of the time-delay buffer has a silicide layer partially disposed on the transistor gate of the CMOS and a non-silicide region lain in between the silicide layers. Therefore, the time-delay buffer of the present invention has a resistance therein, and results in a period of time delayed in the circuit.

Abstract: A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.