Abstract: A current controlled oscillator circuit comprising a "variable-ratio current mirror", for providing a variable output current that varies in response to process. The "variable-ratio current mirror" having a reference MOS transistor and a mirrored MOS transistor, and the reference MOS transistor has a greater predetermined channel length than the channel length of the mirrored MOS transistor. A second current mirror is coupled to the "variable-ratio current mirror" to provide a control current that decreases in response to an increase in the variable output current of the "variable-ratio current mirror." A multi-stage ring oscillator having a plurality of series-connected inverter stages is responsive to the control current of said second current mirror for controlling the frequency of oscillation of said multi-stage ring oscillator.

Abstract: A variable delay circuit that delays an input signal for a desired time and outputs the delayed signal includes N (N is an integer of 2 or more) load transistors and N control transistors for controlling the load transistors respectively connected in pairs in series to form N load transistor pairs. The load transistor pairs are connected in parallel to form a load transistor group. A switching transistor that is turned on or off according to an input signal input to a gate, and the load transistor group are connected in series between first and second power supplies. The input signal is delayed according to control signals that are respectively input to the control transistors, and a delayed signal is output from a connection node of the load transistor group and the switching transistor. Since no selector is required, a delay circuit operation due to differences in delay times between paths in a selector is avoided, thereby obtaining a variable delay circuit having minute resolution and a good yield.

Abstract: A variable delay circuit for arbitrarily change of a signal delay helps easily attain a desired resolution with a high precision, which has been difficult due to device process dependence of a voltage control circuit applying a voltage to a CMOS circuit. A variable voltage controller is provided between a power source and a CMOS circuit propagating a signal such that a delay time of signal propagation is supervised by controlling the voltage at a connecting point in the variable voltage controller. The controller includes two MOS transistors and an npn transistor, which solves the process dependence and hence leads to a low power consumption and a high resolution.

Abstract: The present invention provides a circuit (10) and method for providing a delayed output signal which is less sensitive to supply variation compared to conventional circuits, has high noise immunity, can be operated at high frequency, and occupies a minimum area on the semiconductor. The delay is provided according to the present invention by separately controlling the discharge currents of a capacitor (26) before and after the trip point voltage of an output inverter (16) of the circuit (10) has been reached. The delay interval is determined primarily by the capacitor value, the voltage difference between the supply and the trip point of the output inverter, and the first discharge current, set by a resistor (24) in series with a transistor (34). The second discharge current is set by a switch (36) having a series of transistors (38, 40).

Abstract: A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.

Abstract: The present invention concerns a delay circuit that provides a fixed amount of delay that is generally independent of process variations. An input resistance is provided that may be presented to a threshold device, such as an inverter, that may then be presented as an output. The output of the threshold device may also be presented through a feedback path comprising a capacitive device to the input of the threshold device. The feedback through the capacitive load actively resists the movement of the load. As a result, the delay provided by the circuit is generally resistant to process variations.

Abstract: A cascoded cmos differential delay element is described. The delay element provides a controlled delay useful in forming voltage controlled oscillators or other circuits. The delay element provides high gain enabling it to be useful in multistage delay element circuits. The circuit described includes cascoded complementary differential amplifiers and replicated bias clamps.

Abstract: A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof.

Abstract: A delay circuit comprising at least one capacitor with one electrode thereof is connected to a fixed potential, a signal transmission line, and at least one switch means between the other electrode of the capacitor and the signal transmission line. The switch means makes electrical connection or disconnection between the capacitor and the signal transmission line in accordance with an actual supply voltage value.

Abstract: The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.

Abstract: A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof.

Abstract: A scan circuit includes a plurality of stages of cascaded pulse delay transfer circuits each including a single-phase-clock controlled inverter connected in cascade and configured to receive a given pulse signal from a preceding stage so as to transfer the received pulse signal to a next stage at a delayed timing in synchronism with a clock signal, and a two-input logic gate having a first input connected to an output of the associated single-phase-clock controlled inverter and a second input receiving the same clock signal. The two-input logic gate of an odd-numbered stage includes a NOR gate, which has an output connected to a non-inverting output buffer. The two-input logic gate of an even-numbered stage includes a NAND gate, which has an output connected to an inverting output buffer.

Abstract: An integrated circuit for selectively providing delay to a waveform carried on a signal line. With the present invention, a waveform is carried by a signal line to which a digitally-controlled capacitive load is coupled. A digital enable line is directly coupled to the capacitive load which either activates or deactivates the capacitive load. When the enable line is in the active state, the capacitive load is activated and the load therefore has maximum capacitance. Accordingly, the delay of the waveform carried on the signal line is also maximized. When the enable line is in the inactive state, the capacitive load has minimal capacitance and the delay of the signal being carried on the signal line is therefore minimized.

Abstract: A capacitance measuring device comprises a MOS transistor having a source, drain, and gate; a first capacitor C.sub.1 connected between said gate and said drain so that charge is coupled from said drain onto said gate; and a second capacitor C.sub.2 for connection to a source of gate voltage V.sub.G and connected to said gate. One of the first and second capacitors has a known capacitance and the other has an unknown capacitance. A DC voltage is supplied between the source and drain to cause a saturation current to flow therebetween. The ratio .delta.V.sub.G /.delta.V.sub.d for the saturation current, where V.sub.G is the applied gate voltage, and V.sub.d is the drain voltage is determined and the unknown capacitance is derived from the relationship C.sub.1 /C.sub.2 =-.delta.V.sub.G /.delta.V.sub.d.

Abstract: A delay circuit comprises cascade-connected first through third inverters. The second inverter comprises a first resistor one terminal of which is connected to an output of the first inverter; a P-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, and a source of which receives a power supply voltage; an N-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, a source of which receives a ground voltage, and a drain of which is connected to a drain of the P-channel MOS transistor; and a capacitor one terminal of which is connected to the other terminal of the first resistor, and the other terminal of which is connected to the other terminal of a current path of the P-channel MOS transistor.

Abstract: A delay stage for a ring oscillator supplies a first output signal and a second output signal. Each of the first and second output signals has a peak-to-peak voltage swing. The first and second output signals are complementary to each other. The delay stage includes a differential amplifier for generating the first output signal and the second output signal and a voltage clamping circuit for limiting the peak-to-peak voltage swing of the first and second output signals. The voltage clamping circuit is coupled between the first output signal and the second output signal. The differential amplifier includes a first NMOS transistor and a second NMOS transistor for generating the first and second output signals. The differential amplifier also includes a first PMOS transistor and a second PMOS transistor coupled to (1) the first and second NMOS transistors and (2) the voltage clamping circuit for providing bias currents to the first and second NMOS transistors.

Abstract: A true type single-phase shift circuit including a pair of PMOS transistors, a pair of NMOS transistors, a pair of first-type MOS transistors and one second-type transistor. The source terminals of the two PMOS transistors are both coupled to a first electric potential, the gate terminal of one PMOS transistor is coupled to a data signal, and the gate terminal of the second PMOS transistor is connected between the two first-type MOS transistors. The source terminals of the two NMOS transistors are both coupled to a second electric potential; the gate terminal of one NMOS transitors is coupled to the data signal and the gate of the second NMOS transistor is connected between the two first-type MOS transistors. The two first type MOS transistors are serially connected between the drain terminals of one of the two PMOS transistors and the drain terminal of one of the two NMOS transistors. Each gate terminal of the two first type MOS transistors is coupled to a clock pulse signal.

Abstract: The subject of the invention is an integrated delay circuit (10), including two amplifiers (11a, 11b), furnishing different delays, and having a common input, and a control block (12) connected to two terminals of the two amplifiers, respectively, in order to vary the phase offset between the two amplifiers. This circuit is integrated into a III-V semiconductor, such as gallium arsenide.

Abstract: A bus driver circuit includes a plurality of first MOS transistors connected in series between a data input terminal and a data output terminal, and a plurality of second controlling MOS transistors. Sources of said plurality of first MOS transistors are connected to drains of said plurality of second controlling MOS transistors. Also, gates of said plurality of second controlling MOS transistors to control signal source means for selectively turning ON and OFF said plurality of second controlling MOS transistors. The bus driver circuit thus constructed permits selection of optimal rise-up and fall-down transition period for achieving high speed and efficient data transmission.

Abstract: Performance degradation resulting from hot carrier stress is determined using a special test circuit. The test circuit is formed using a string of inverters on an integrated circuit. The string of inverters is connected in series. Every other inverter in the string of inverters uses cascaded transistors so that performance of the inverters with cascaded are not degraded by introduced hot carrier stress. For example, odd numbered inverters are each constructed using cascaded PMOSFETs and cascaded NMOSFETs and even numbered inverters are each constructed using a single PMOSFET and a single NMOSFET. On an input of the string of inverters, a first signal is placed which transitions from logic 0 to logic 1. Propagation delay of the first signal through the string of inverters is measured. Also, a second signal which transitions from logic 1 to logic 0 is placed on the input of the string of inverters. Propagation delay of the second signal through the string of inverters is measured.

Abstract: In a ring oscillator, a delay unit includes an input stage having a first and a second input port and a first and a second differential output port. At least two delay units are coupled together so as to form the ring oscillator. The delay unit further includes a first capacitor coupled to the first differential output port of each one of the delay units and a second capacitor is coupled to the second differential output port of the delay unit. A switching accelerator is coupled to the first and second capacitors so as to reduce the time it takes to switch between charged and discharged states for the capacitors.

Abstract: An output device and method of operating it are disclosed. The output device includes a output control unit and an output buffer unit. The output control unit produces a data release (INR) signal after producing an output release (OR) signal, for example, by delaying the OR signal. The INR signal causes release of an output signal from a sense amplifier, resulting in a data signal. The output buffer includes n- and p-channel switching transistors and control units controlling their gates. In response to activation of the OR signal, the control units bring the voltage of the gates of the switching transistors to respectively slightly above and slightly below the threshold levels of their gates. In response to the data signal, the control units fully activate one of the switching transistors and deactivate the other of the switching transistors depending on the voltage level of the data signal. The speed with which the control units respond to the data signal is controlled.

Abstract: A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof.

Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.

Abstract: A signal delaying outputting circuit is disclosed which can prevent an excessive increase in dead time at a high temperature without requiring a large chip area. The signal delaying outputting circuit comprises a first invertor circuit driven by an input signal, and a second invertor circuit driven by an output signal of the first invertor circuit. A first auxiliary MOS FET of the same channel type as that of one of two first p- and n-channel MOS FETs of the first invertor circuit is provided in the first converter circuit in an integral continuous relationship with the one MOS FET such that they have separate gates from each other but have a common source or drain.

Abstract: An analog switch includes first and second thin film field effect transistors having their gate connected in common to a control terminal. Current paths of the first and second thin film field effect transistors are connected in series between an input terminal and a capacitive load. A voltage adjusting capacitive element is connected to a common connection between the current paths of the first and second thin film field effect transistors.

Abstract: A digitally adjustable time delay circuit which is able to precisely and selectively provide fine delay steps increments, which increments can be one nth of the delay time of one CMOS inverter, including means to adjust the total range of the delay and size of each delay step.

Abstract: In a signal transmitting device in a semiconductor apparatus, a second signal 29 and a third signal 40 are activated by the activation of a first signal 2 which is entered. More specifically, the third signal 40 is firstly activated, and the second signal 29 is then activated while the third signal 40 is being activated, and then the third signal 40 is inactivated. Further, a fourth signal 42 is activated by the activation of the second signal 29 or by the activation of the third signal 40. Accordingly, even though a noise removing circuit 80 or the like is disposed in a first signal transmitting circuit 70 for activating the second signal 29, the period of time required by the time the fourth signal 42 is activated, can be shortened. Thus, there can be obtained a semiconductor apparatus which is fast in access (speed at which a signal is transmitted to a subsequent stage) and which is resistant to noise.

Abstract: A CMOS pulse delay circuit is arranged to accurately delay an input pulse signal by a predetermined period. The CMOS pulse delay circuit provides two inverters for causing delays. The inverters each have switching transistors. The switching transistors of the first inverter are associated with voltage-controllable variable resistance elements located in series to each other for varying the on-resistance of the transistors. The varying of the on-resistance results in keeping the output delay phases accurate.

Abstract: An off-chip driver with regulated supplies compensates for power supply fluctuations. The circuit reduces di/dt noise by providing complementary voltage regulators to regulate the high and low supplies to the driver stages such that they see a constant operating voltage regardless of changes in supply voltage, V.sub.CC. The circuit uses two push-pull stages which charge and discharge the output load capacitance, C.sub.0. This regulated voltage to the driver stages reduces di/dt noise and provides a constant overdrive voltage, constant gate slew rate, and constant staging delay over a specified external supply voltage range.

Abstract: Disclosed is a digital phase-locked loop circuit which provides a control signal (332, 334) for a delay circuit (304, 306, 308, 310) within the feedback path of the phase-locked loop. The circuit has a first series of delay circuits (304, 306, 308, 310), which have an incremental control signal input (332, 334), to delay an input clock signal (302) to provide the D input (311) to a D flip flop (312). The input clock signal (302) is also connected to a second series of delay circuits (314, 316, 318, 320, 322). The output of this second series (314, 316, 318, 320, 322) is connected to the clock input (323) of the D flip flop (312). The voltage controlled delay signal input for the second series of delay circuits (314, 316, 318, 320, 322) is supplied by a reference control signal (124, 126). The output of the D flip flop (312) is passed through a resistor-capacitor filtering circuit (324, 325) and fed back to the first series of delay circuits (304, 306, 308, 310) as the incremental control signal.

Abstract: A compensation circuit equalizes processing (speed) differences between driver chips used to drive an active matrix LCD display by inserting a delay in opposite proportion to the speed of the driver IC so that a faster IC will receive a longer delay and a slower IC will receive a shorter delay.