Abstract: A power control circuit (10) contains a voltage controlled attenuator (16) in combination with a logarithmic converter (24) to produce linear amplification of an input signal (12) over as wide a frequency output range. A logarithmic converter for use in such a power control circuit is provided, including an amplifying circuitry (60) with a non-inverting (66) and inverting (70) input and an output (64), and two feedback circuits (62, 68). The feedback circuits are separably connected between the output and an input of the amplifying circuitry, so that the first feedback circuitry (62) produces a feedback signal which results in the amplifying circuitry (60) exhibiting a non-linear characteristic and the second feedback circuitry (68) contains at least one reactive element (108) to limit the feedback signal from the first feedback circuitry (62) above certain signal levels.

Abstract: Temperature and technology-independent self-calibrating monolithic logarithmic amplifier systems that use integrated cascades of current-summing or voltage-summing differential-limiter gain stages are disclosed. Each stage is trimmed and stabilized by a respective bias replicator cell and a current mirror cell. The bias replicator provides a bias current control signal in response to a change in a given difference between bias currents in a differential pair of amplifiers controlled by a predetermined differential calibration voltage. The differential pair is identical to a differential pair in the limiter amplifier. The differential calibration voltage E.sub.lin is well-within the linear portion of the amplifier's transfer curve during operation, so that the proportional relation between E.sub.k and E.sub.lin, which is the same as that between the given difference between currents and the correct bias current value I.sub.B, remains constant throughout.

Abstract: A logarithmic conversion circuit includes a narrow band generating unit consisting of a local oscillator (104) and a mixer (103) for receiving an output of the local oscillator and the input signal and a first band-pass filter (105) connected to the mixer for generating a narrow band signal from a broad band input signal; a selection member (106-7) directly connected to the first band-pass filter for selecting either the input signal or the narrow band signal; first and second LOG amps (108, 111) connected in series to the selection member; and a noise suppression unit connected in parallel between the first and second LOG amps and including a second band-pass filter (109) for transmitting only the broad band input signal and a low-pass filter (110) for transmitting only the narrow band signal.

Abstract: An amplifier which outputs a nonlinear function in response to a linear input. The nonlinear response is a piece-wise linear approximation. The circuit includes an op amp which outputs a ramping voltage and a series of stages which change the scope of the ramping voltage. As the output of the op amp reaches a particular breakpoint, an additional stage of the circuit is activated so as to change the slope of the output. The new line segment has a new slope such that the combination of all these stages approximates a nonlinear response.

Abstract: Low power, high linearity log-linear control method and apparatus wherein a master log-linear cell generates a control voltage that is buffered and applied to a slave log-linear cell. By breaking this function up into two pieces, the control loop characteristics are isolated from the signal path. Low impedance buffers can be used to drive the slave log-linear cell control ports, independent of the control loop, providing improved gain control range and linearity. This log-linear control is of particular value in applications that require low harmonic distortion and high gain control range in power or pin-constrained applications. Details of the method are disclosed.

Abstract: An electrical circuit for generating a polynomial function in response to a linear input signal is disclosed. The circuit in one embodiment comprises a primary and a secondary current mirror, with the collector or source of the secondary current mirror connected in common with the input signal of the primary current mirror. The output signal of the electrical circuit is taken at the mirrored current source terminal of the first current mirror. The primary and secondary current mirrors are biased to at least initially respond exponentially to the linear input signal. Each then transitions into the more linear, resistor-dominated range. The primary current mirror is enabled at a predetermined cut-in level, such that an upward curving exponential response function is generated in response thereto.

Abstract: Compensation is provided for temperature-effects intrinsic to a logging transistor in a logarithmic amplifier by applying a temperature-dependent term to a voltage reference of an analog-to-digital converter.

Abstract: A temperature compensated logarithmic detector biased with a proportional to absolute temperature (PTAT) voltage produced in accordance with an area ratio of biasing transistors is disclosed. According to one implementation of the invention, the temperature compensated logarithmic detector includes biasing circuitry and a logarithmic detector cell. The biasing circuitry receives an input signal and produces a PTAT bias voltage from the input signal. The PTAT characteristic of the PTAT bias voltage is produced by an area ratio. The logarithmic detector cell converts the input signal to a logarithmic output signal in accordance with a logarithmic transfer function over a narrow range.

Abstract: A gain cell circuit includes a logarithmic transformation circuit. The logarithmic transformation circuit includes a pair of first and second transistors, each of which has first and second current carrying electrodes and a control electrode. The control electrodes of the first and second transistors are coupled to input terminals of the logarithmic transformation circuit. The logarithmic transformation circuit further includes third and fourth transistors coupled to the first and second transistors. The third and fourth transistors have control electrodes serving as output terminals of the logarithmic transformation circuit, first current carrying electrodes connected at first and second circuit nodes to the second current carrying electrodes of the first and second transistors, and second current carrying electrodes coupled to a power supply voltage.

Abstract: An explicit RMS detector sequentially performs the square, mean and square-root operations in the log domain. An input signal is first applied to a log converter, and then to a times two multiplier which squares the input signal. A log filter averages the log square input signal for a predetermined period to approximate the "mean" operation, after which a times one-half multiplier operates on the log mean-square input signal to compute the square root. An exponentiator exponentiates the resulting log root-mean-square input signal to produce an output signal that approximates the RMS value of the input signal for the predetermined period.

Abstract: A logarithmic amplifier for preventing an abnormal output from occurring when receiving an excessive input. The logarithmic amplifier is provided with an operational amplifier for logarithmic conversion purposes and a feedback circuit for feeding back an output from the operational amplifier via a resistor connected to an output terminal of the operational amplifier. An element (for example, an element consisting of a Zener diode and a diode connected in series with each other) having an effective resistance which becomes smaller when a voltage above a predetermined value is applied to the element is connected in parallel with a resistor connected to an output terminal of an operational amplifier for logarithmic conversion purposes.

Abstract: An electronic filter for passing predetermined frequencies includes resistive and capacitive components that need not be rated to handle the input voltage. An input signal is converted to a second signal that is proportional to the logarithm of the input signal (and therefore of much smaller magnitude than the input signal), and then low, high, bandpass filtered with an RC filter. The filtered signal is reconverted to an output signal that is proportional to the inverse logarithm of the filtered signal. The filter may be embedded in a current mirror that may be used in telephone system subscriber line interface circuit.

Abstract: A differential comparator with a hysteresis proportional to the peak value of the input signal. The comparator operates independently of the magnitude of the supply voltage and of the ambient temperature while handling both differential and single-ended inputs and without introducing a delay between the input and the output.

Abstract: A logarithmic amplifier gain stage for supplying, in response to an instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal. The gain stage includes a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal. A full-wave detector having an input coupled to the intermediate output of the transistor amplifier receives the intermediate output signal and supplies the output signal wherein the detector includes a rectifier comprising transistors having different effective emitter areas.

Abstract: A logarithmic amplification circuit is provided which is composed of a differential amplifier, a plurality of full-wave rectifiers including two half-wave rectifiers connected so as to have their input signals inverse in phase to each other and respectively receiving an output signal of the differential amplifier, and an adder for adding the output signals of the full-wave rectifier. Each of the half-wave rectifiers includes a differential transistor pair only one of which has an emitter resistor.

Abstract: An anti-logarithmic type converter circuit, with temperature compensation, includes a diode connected between a unity gain, non-inverting interface circuit and a low-impedance reference voltage circuit. A thermal compensation circuit is connected between the converter input and the interface circuit. The thermal compensation circuit includes current mirror circuits having a gain higher than one and their output currents linearly dependent on temperature.

Abstract: A logarithmic amplifier includes an operational amplifier, an element for logarithmic conversion purposes connected to a feedback circuit of the operational amplifier, an oscillation prevention circuit having a capacitor connected in parallel with the logarithmic conversion element, and a control circuit for controlling the oscillation prevention circuit in such a way that the amount of feedback by way of the oscillation prevention circuit is reduced as an input current to the operational amplifier becomes smaller. To improve the high-speed response characteristics of the logarithmic operational amplifier, the operational amplifier is made up of a composite amplifier consisting of an FET input type operational amplifier and a bipolar input type operational amplifier.

Abstract: A color corrector receiving a video signal as an input signal and producing an output signal representing a function of power of the input signal includes a logarithmic converter for achieving a logarithmic conversion of the input signal and outputting a resultant signal, a variable gain amplifier for altering amplitude of the signal from the logarithmic converter and outputting an obtained signal, and an antilogarithmic converter connected to the amplifier for outputting a signal representing an exponential function of the signal from the amplifier.

Abstract: A log conversion circuit comprising first and second input terminals to which voltage signals are input, first and second resistors, first ends of which are respectively connected to the first and second input terminals, first and second PN junction element sections connected in series and in opposite polarities, between a second end of the first resistor and a second end of the second resistor, a biasing circuit connected between a first source terminal and a node between the first and second PN junction element sections, first and second current sources for determining potentials at both ends of the first resistor, the first current source means connected between the first end of the first resistor and the first and second source terminals, and the second current source means being connected between the second end of the first resistor and the first and second source terminals, third and fourth current sources for determining potentials at both ends of the second resistor, the third current source means con

Abstract: To provide a resistor array circuit device and variable gain device which make possible precise setting of attenuation factors and the like as well as prevention of generation of gridge noise, a resistor array circuit device has resistors R1.sub.1 to R1.sub.n-1, each with a resistance value R, resistors R2.sub.1 to R2.sub.n, each with a resistance value aR, resistor R3 having a resistance value (l+b)R, switches SW.sub.1 to SW.sub.n for switching connection of resistors R2.sub.1 to R2.sub.n to a terminal T3 or a terminal T4, and a control circuit for controlling switches SW.sub.1 to SW.sub.n so that resistors R2.sub.1 to R2.sub.m-1 on a terminal T1 side of an arbitrary resistor R2.sub.m are connected to terminal T4 and resistors R2.sub.m to R2.sub.n on a terminal T2 side of resistor R2.sub.m are connected to terminal T3, the values of the a and b being determined based on b={-1+(1+4a).sup.1/2 }/2 and 1/2<a/(1+a+b).

Abstract: A multiplier circuit including a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage; and a control section having a first terminal through which an input current flows, a second terminal through which a current equal to or a constant multiple of the input current at the first terminal flows, the first voltage being supplied to the second terminal, a third terminal through which an output current flows, and a fourth terminal through which a current equal to or a constant multiple of the output current at the third terminal. The second voltage is applied to the fourth terminal. The control section controls the output current so that a logarithm of a ratio of an absolute value of the output current to an absolute value of the input current is in proportion to a difference between the first voltage and the second voltage.

Abstract: In a phase detector, an input signal (Si) is multiplied in a multiplier by two reference signals intersecting at right angles with each other. Signals obtained by multiplication are passed through filters and subjected to quadrature demodulation. An I signal and a Q signal obtained by quadrature demodulation are input to non-linear compression circuits and compressed by logarithmic conversion. Based on the compressed I and Q signals, a phase detection circuit detects the phase of the input signal (Si).

Abstract: A detector cell for a logarithmic includes a differential pair of inputs across which a input signal V.sub.0 is applied across. The detector cell also includes a pair of differential outputs. The detector cell is comprised of three transistors Q4, Q5 and Q6. Resistors are coupled between the bases of adjacent transistors. The resistors form a voltage divided across which the input signal V.sub.0 is divided. The emitters of the three transistors are coupled to a current source, which sends a predetermined amount of current Ihd D. The collectors of the first and third transistors are coupled together to form a first differential input of the differential input pair. The collector of the second transistor alone forms the second differential input of the pair. The emitter area of the second transistor is ratioed with respect to the first and third so that a current I.sub.1 flowing through the first differential output is equal to a current I.sub.

Abstract: A PTAT current source has first and second current mirror circuits, each comprising a cascode transistor, an output transistor in series with the cascode transistor, and a base current compensating transistor having a control element connected to the cascode transistor on a side away from the output transistor, and a current flow path element connected to a current control element of the output transistor, the cascode transistors of the first and second current mirror circuits having differently sized emitter areas. A resistor is connected between the cascode transistors of the first and second current mirror circuits across which a differential current is developed. An output circuit develops a current in the output transistor of the second current mirror circuit. In one embodiment, a third mirror circuit is provided, to cancel a portion of an emitter current flowing in the output transistor of the second current mirror circuit.

Abstract: A logarithmic convertor based on a nonlinear successive detection principle has a temperature-compensated biassing arrangement and a large operating range due to a d.c. feedback network for offset reduction and an attenuating input stage permitting large input voltages. The log convertor exploits the exponential relationship between the collector current and base-emitter voltage of a bipolar transistor to render the convertor insensitive to temperature and process parameter variations. The converter is a cascade of sections, each having a constant-gain differential amplifier having a particularized current source. The constant-gain amplifier may include a Darlington differential pair, and the current sources have outputs that are either temperature-independent, or proportional to temperature.

Abstract: A method and apparatus for convening a measured signal which, at least in a first approximation, is related to a quantity of interest by the equation (a): ##EQU1## where y is the quantity of interest, x is the measured signal, and k, k.sub.N, k.sub.Z are constants, into a signal that is a function of the quantity of interest. The method implements the function (b):ln y=prop. ([ln (x-k.sub.N)-ln (k.sub.Z -x)])wherein prop. means proportional, and where the function is implemented in an approximated manner by at least two bipolar transistors that have base emitter voltages that are dependent on collector currents of the bipolar transistors for receiving an output signal according to the equation (c): y'=ln y, with y' being the output signal.

Abstract: A logarithmic amplifier has first and second mirror circuits, each having active transistors interconnected by a resistor. The current input is applied within one of the mirror circuits so that a logarithmic function thereof is generated for output by an output current mirror circuit. The mirror circuits are similarly constructed with an active transistor, a cascode transistor, and a base current compensating transistor. The cascode and active transistors are connected in series between an input node and a reference potential, or ground, with the base current compensating transistor connected between a supply voltage source and a base of the active transistor. The base of the base current compensating transistor is connected to the reference current input node. Through modification of the basic circuit by injection of an input current to the active transistor with respect to the reference potential, an exponential converter is presented.

Abstract: A cascaded amplifier is comprised of a number of amplifying stages connected in cascade such as the dual emitter-coupled amplifier shown. A first pair of transistors (14,20) provides limiting amplification and a second pair of transistors (16,18) with degeneration (22,24) provide linear amplification. Each pair of transistors is driven by a current source (28,26) which supplies a current (IT, IT2) proportional to absolute temperature (PTAT). The small signal amplification is then substantially independent of temperature and the value of the limited output is proportional to absolute temperature. This latter effect is countered by including a translinear variable current gain amplifier (54,56,58,60) in the last dual-gain stage of the cascaded amplifier to modify the output voltage in a manner inversely proportional to absolute temperature. A transfer function may thus be provided which is substantially independent of temperature.

Abstract: A logarithmic detector having a first input line linked to the base of the first transistor, a second line linked to the base of the second transistor, a third input line linked to the bases of third and fourth transistors, a fourth input line linked to the bases of fifth and sixth transistors, a first output line linked to the collectors of the third and sixth transistors a second output line linked to the collectors of the fourth and fifth transistors and emitters of the third and fifth transistors being linked through the first and second impedances respectively to connect to the first transistor, the emitters of the fourth and sixth transistors being linked through third and fourth impedances to the collector of the second transistor and the emitters of the first and second transistors being linked through 5th and 6th impedances respectively to a current source connected to earth.

Abstract: A gain cell circuit includes a logarithmic transformation circuit. The logarithmic transformation circuit includes a pair of first and second transistors, each of which has first and second current carrying electrodes and a control electrode. The control electrodes of the first and second transistors are coupled to input terminals of the logarithmic transformation circuit. The logarithmic transformation circuit further includes third and fourth transistors coupled to the first and second transistors. The third and fourth transistors have control electrodes serving as output terminals of the logarithmic transformation circuit, first current carrying electrodes connected at first and second circuit nodes to the second current carrying electrodes of the first and second transistors, and second current carrying electrodes coupled to a power supply voltage.

Abstract: A phase detector for symbol clock recovery in a digital communications system determines the phase error of a local symbol clock from the symbol rate of a transmitted signal by sampling the transmitted signal to obtain a first sample at a fraction of a symbol period after the symbol clock and to obtain a second sample at an equal fraction of a symbol period before the symbol clock, and determining a phase error equal to the difference between a function of the magnitude of the first sample and a function of the magnitude of the second sample. The function is preferably the square of the magnitude or the logarithm of the magnitude of the samples.

Abstract: A wideband amplifier which employs a plurality of cascaded logarithmic amplifier stages under the control of a digital signal processor which nulls offset voltages. In one aspect of the invention, the digital signal processor controls switches, one switch associated with each amplifier stage for determining an appropriate offset voltage and producing a counterbalancing signal. In another aspect of the invention the amplifier includes two potentiometers or variable signal devices which can set the overall input signal level and set the ratio of maximum to minimum of the input signal level, respectively, to desired levels. In a third aspect of the invention, a lookup table is associated with the digital signal processor for storing correction factors to be applied to digitized values in order to produce a final result which is corrected for variations in the amplifier characteristic from true logarithmic.

Abstract: Gamma correction is performed by dividing the total gamma transfer function input value range into a plurality of segments. The source RGB data is then mapped into an associated x-position in a "standard" segment, and gamma correction is performed on the mapped value as if it was initially in that standard segment. The resulting corrected value is then de-mapped back into the original input value segment. Only the portion of the gamma correction curve which is within the "standard" segment is processable by the circuitry. The segments into which the input value range is divided may occupy ratiometrically increasing portions of the input value range, with the high-order half of the range designated as the standard segment. The lowest-order portion may be approximated linearly. Mapping into the standard segment then involves shifting the input value to the left until the highest order logic 1 is in the highest order bit position.

Abstract: A toner depositing amount measuring apparatus for measuring the amount of toner deposited on a photosensitive drum includes a light source for irradiating the surface of the photosensitive drum with light and a photoelectric converting section for receiving the reflected light and converting the received reflected light into an electric signal. A logarithmic calculation is applied to the output signal of the photoelectric converting section in a logarithm-compressing section. The temperature characteristics of the logarithm-compressing section are compensated for in a temperature compensating section. The amount of the toner deposition is calculated in a toner depositing amount calculating section based on a difference between the data during non-deposition of the toner and the data during deposition of the toner, the data being obtained from the logarithm-compressing section.

Abstract: In an image sensing device, a photodiode is connected to a drain of a MOS transistor. The drain is connected to a gate of the MOS transistor via a resistor. The MOS transistor operates in a subthreshold region to output a signal being logarithmically proportional to the intensity of incident light to the photodiode.