Abstract: A switching point detection circuit for detecting a switching point according to a fabrication condition of MOS transistor, includes a reference voltage generation unit for generating a reference voltage, a first CMOS inverter, in which an NMOS transistor is dominant for the reference voltage, receiving the reference voltage and a second CMOS inverter, in which a PMOS transistor is dominant for the reference voltage, receiving the reference voltage.

Abstract: In a switching circuit, a first electrical element (22) is disabled before a second electrical element (30) is enabled. The switching operation is called break before make and ensures that disabling operation of a first electrical element occurs before enabling operation of a second electrical element. The assurance is in the form of a disable signal being detected from a first electrical element at an input of a first detection circuit (28). Correspondingly, the detected disable signal of the first electrical element enables operation of the second electrical element. Alternatively, a detected disable from the second electrical element at the input of the second detection circuit (20) enables operation of the first electrical element.

Abstract: A controllable pulse-clock-delay apparatus for use with an integrated circuit, the controllable pulse-clock-delay apparatus including an input pulse clock terminal that is adapted to receive an input pulse clock, an output pulse clock terminal, a controllable delay arrangement that is coupled to the input pulse clock terminal, and that is adapted to output an output pulse clock at the output pulse clock terminal, and a feedback arrangement coupling the output pulse clock to the controllable delay arrangement so that another output pulse clock is based on the input pulse clock and the output pulse clock.

Abstract: A circuit is designed with a delay circuit (300) coupled to receive a clock input signal (CLK) and a control signal (DFT). The control signal has a first logic state and a second logic state. The delay circuit produces a clock control signal (*CLK) at a first time in response to the first logic state and at a second time in response to the second logic state. A clock circuit (200) is coupled to receive the clock input signal and is enabled by the clock control signal. The clock circuit produces a first clock pulse signal having a predetermined width in response to a first transition of the clock input signal and produces a second clock pulse signal having the predetermined width in response to a second transition of the clock input signal.

Abstract: A cable driver is disclosed which provides a substantially linear output signal corresponding to an input signal received by the cable driver on a transmission line. The cable driver includes a number of switches coupled by delay elements with cause the switches to operate in a sequential order in response to an input signal. Each of the switches couples an associated current source to an output port, producing a substantially linear output signal on a transmission line connected to the output port. The substantially linearity of the output signal increases the rate at which data may be transmitted over the transmission line, while permitting the rise and fall time of a specified portion of the output signal to be controlled to ensure that electro-magnetic interference is not produced.

Abstract: A delay circuit is constituted by connecting a plurality of delay elements in series, each delay element is constituted by a pMOS transistor P1 and a nMOS transistor N1 having a larger driving capability than P1 and by a nMOS transistor N2 and a pMOS transistor P2 having a larger driving capability than N2, an input signal is applied to the gate of the transistor P1, a precharge signal is applied to the gate of the transistor N1, an inverted signal of the precharge signal is applied to the gate of the transistor P2, the gate of the transistor N2 is connected to an intermediate node A, an input signal S.sub.IN is input to each delay element as the precharge signal, and when the input signal S.sub.IN is at a high level, the node A is in the state of a low level and the output terminal OUT is in the state of a high level, the falling edge of the input signal S.sub.IN is sequentially propagated by delay elements, and thus a delay signal is obtained.

Abstract: A power applying circuit for an internal logic circuit includes a plurality of basic power applying units coupled to the internal logic circuit in parallel, each of the basic power applying units including a logic gate unit outputting a pulse in response to two input signals having a time interval with respect to each other, and a transmission gate coupled to the logic gate unit and receiving the pulse.

Abstract: A multiplexer selectively connects one of first and second nodes to a third node. The multiplexer includes a first switch coupled between the first and third nodes, a second switch coupled between the second and third nodes, and a control input for receiving a signal to either open the first switch and close the second switch or open the second switch and close the first switch. Additionally, a delay circuit, coupled to the control input and the second switch, delays closure of the second switch until the first switch is open. In a preferred embodiment, the delay circuit includes two field-effect transistors having substantially different width-to-length ratios.

Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are filed by a current generator through current mirrors and are therefore very stable.

Abstract: In a driving circuit for generating driving signals for controlling and switching on and off a first output element employed in an output circuit for generating a high-level output signal and a second output element employed in the output circuit for generating a low-level output signal in a mutually complementary manner, the conductance of the driving circuit is controlled so that it increases gradually with the lapse of time. By sequentially controlling the conductance of the driving circuit for generating the driving signals, the rates of change of the driving signals can be controlled in a smooth and stable manner and output currents can thus be changed smoothly to result in high-speed operation of an output signal with a reduced amount of noise.

Abstract: A switching circuit for outputting input and output signals from a single terminal includes an I/O signal interface circuit for forming a current path in parallel with a switch when a voltage at both terminals of the switch changes from high state to low state and for opening the current path when receiving a delay signal. An I/O signal separator provides the delay signal of predetermined time width when forming the current path to the I/O signal interface circuit and for blocking the current path during the delay period. Repeated and consecutive striking of a singular switch is ignored since only the first strike is effective. In addition, a display connected to a previously pressed switch remains continuously lighted when an interval between two consecutive struck different switches is shorter than the delay period.

Abstract: A BIMOS driver circuit and method in which a push-pull pair of PNP-NPN bipolar transistors replaces the middle CMOS inverter stages in a circuit for driving a capacitive load. The rise and fall times of the circuit are made symmetrical by feeding back driver circuit output to operate a feedback transistor which removes the base charge stored in a PNP transistor of the bipolar push-pull pair, and maintains low propagation delay.

Abstract: A switch circuit for activating and deactivating a motor vehicle cruise control includes a 555 model timer integrated circuit which has a trigger terminal, a reset terminal, a threshold terminal, a control voltage terminal and an output terminal. A substantially constant voltage is applied to the threshold terminal. A first normally-open switch connected between the vehicle ground and the trigger terminal, and a second normally-open switch connected between vehicle ground and the reset terminal. Separate pull-up resistors connect the trigger and reset terminals of the timer to a positive voltage source and a capacitor couples the control voltage terminal to vehicle ground. A relay has a coil connected between the output terminal and vehicle ground, and has a switch that is connected between the common terminal and the ON control terminal of the cruise control. The 555 timer is configured as a latching circuit having an output which toggles in response to operation of the two normally-open switches.

Abstract: A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

Abstract: A power conserving integrated circuit is disclosed. The integrated circuit is coupled to its external power supply only in response to an external event. An initial power connection is made in response to the external event. An element on the integrated circuit detects the initial power connection. After detecting the initial power connection, a switch internal to the integrated circuit is closed so as to couple the power supply to the integrated circuit for a predetermined period of time sufficient for a function to be executed by the integrated circuit. Afterwards, the connection is terminated and is not re-initiated until another external event. Therefore, power is consumed only when necessary, thereby preserving the power source.

Abstract: An integrated circuit for generating a reset signal includes a circuit part having two first transistors being connected in series between terminals for a first and a second supply potential and each having a respective one of first and second mutually complementary channel types. A serial network acting as a voltage divider circuit is connected between the terminals for the first and the second supply potentials. The serial network includes at least two second transistors each having a respective one of the mutually complementary channel types and at least one element having a voltage drop during operation. The sources of the transistors of the first channel type are connected to the terminal for the first supply potential. The sources of the transistors of the second channel type are connected to the terminal for the second supply potential. The drains of the two first transistors form a first circuit node at which a reset signal is created in operation.

Abstract: A pulse shaping circuit of the clock stretcher/chopper type which is sufficiently simplified to be included on an integrated circuit chip with other circuits without significantly reducing the chip area on which such other circuits may be formed achieves a fast recovery time by developing differential delays in response to each of two different characteristics of a signal input to a delay line. Pulse stretching is accomplished by a latch circuit and pulse chopping is accomplished by a delay arrangement which controls the latching action and the output signal. The delay arrangement may also be made programmable. By controlling the latching and the output signal in response to the delay line, a wide range of duty cycles of input and output signals may be accommodated, even at extremely high frequencies.

Abstract: A noise-suppression logic system suppresses a noise signal having a time duration which is less than a predetermined time. A delay circuit has a delay which is equal to the predetermined time. A logic combining circuit is coupled to the system input terminal and to the output terminal of the delay circuit. A R-S latch circuit, having a RESET input terminal, a SET input terminal, and an OUTPUT terminal provides a delayed output signal corresponding to an input signal which has a time duration greater than the predetermined time. A set circuit has a first input terminal coupled to the system input terminal, a second input terminal coupled to the output terminal of the delay circuit, and an output terminal coupled to the SET input terminal of the R-S flip-flop circuit.

Abstract: An analog calculating circuit capable of storing data.A calculating circuit according to the present invention converts an analog voltage level to a time value by using a charging voltage of an RC circuit and stores the time value as a number of clock cycles in a digital counter. The circuit then converts another voltage level to a second time value and either adds the second time value to or subtracts it from the first time value. This yields a time value corresponding to a multiplication or division, respectively, of the analog voltage levels.

Abstract: A clock control apparatus having a basic period clock and a plurality of clocks with different phases from the basic period clock by t/N period, is used with an information processing unit.

Abstract: A semiconductor integrated circuit according to this invention is characterized by comprising a flip-flop having input terminal means and output terminal means, at least one input gate means having output terminal means connected to the input terminal means, which supplies data to this input terminal means under the control of clock, and at least one output buffer means having input terminal means connected to the output terminal means, to which the output signal of the flip-flop is supplied and which is connected to the output terminal means of the input gate means to receive the data from this input gate means to provide an advance read function.

Abstract: A single chip microcomputer includes two kinds of timer circuits which receive a common clock signal. One of the timer circuits generates a first timer signal, and the other generates a second timer signal. When the first timer signal is being reset, the second timer signal is inactive.