Abstract: A constant gate drive metal-oxide semiconductor ("MOS") analog switch. In one embodiment, the analog switch includes first, second, and third devices, and a level shifter. The first device includes a source coupled to an input terminal, a drain coupled to an output terminal, and a gate. The second device includes a source coupled to the input terminal, a drain, and a gate. The third device includes a source coupled to the drain of the second device, a drain coupled to the output terminal, and a gate. The level shifter includes an input coupled to the drain of the second device and an output coupled to the gates of the first, second, and third devices. The level shifter provides a constant gate drive to the first device, regardless of a signal on the input terminal, resulting in a constant on-resistance of the analog switch. In addition, a constant linearity of on-resistance is achieved by keeping the gate voltage constant with respect to the mid-point of the source and drain voltages.

Abstract: A plurality of output transistors for an output buffer of a semiconductor device are provided in parallel. Potentials to be applied to gates of output transistors are set to different levels upon conduction of the output transistors. By sequentially rendering the transistors conductive in the order of increasing voltage during conduction, rapid flow of a large amount of current is prevented, thereby reducing ringing. More preferably, the transistors are increased in size according to the order of conduction of the output transistors.

Abstract: A dual mode apparatus for alternately supplying a low power reference voltage and a high power reference voltage, both at the same voltage level. The apparatus includes a driver, an output buffer and a switch. The driver generates the low power reference voltage, which is directly supplied during a standby mode of a receiving unit. The output buffer receives the low power reference voltage during an active mode of the receiving unit, and generates the high power reference voltage therefrom. The switch is connected between an output of the driver and the output buffer, and provides the high power reference voltage during the active mode, and the low power reference voltage during the stand-by mode.

Abstract: A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.

Abstract: A balanced switching circuit comprises a plurality of transfer gates, each transfer gate having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each transfer gate, which may be comprised of pass transistors such as n- and p-channel metal oxide semiconductor (MOS) transistors, is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of transfer gates are arranged in N rows and N columns with the input and output terminals of the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each transfer gate has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Each clock terminal is coupled to the control terminal of only one transfer gate in each row and only one transfer gate in each column.

Abstract: An output buffer is provided which receives an input signal and drives an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage level corresponding to a logic value of the input signal. The second driver has a greater (current) driving capacity than the first driver. The output buffer also has control circuitry which detects a transition in the logic value of the input signal. In response, the control circuitry generates a particular pulse aligned with the input signal logic value transition having a particular constant voltage level for a predetermined time period. Furthermore, the control circuitry delays the second circuit from driving the output terminal to a complementary voltage level corresponding to the logic value to which the input signal transitions during the predetermined time period.

Abstract: An output circuit according to the present invention is provided with a delay circuit for delaying an enable control signal by a predetermined period td and an output means capable of controlling the output state in either an enable or a disable state, wherein the output state of the first output means so controlled as to be switched from the disable to the enable in accordance with the enable control signal and to be switched from the enable to the disable state gradually in accordance with the signal supplied from the first delay circuit.

Abstract: A switching circuit operable under a low voltage power source includes first and second level shift circuits. The level shift circuits receive a switching control signal and generate an internal switching signal and an inverted internal switching signal. The level shift circuits supply the internal switching signals to switching elements. A switched capacitor filter includes an amplifier and the described switching circuit. The amplifier has amplification inverters connected in series in three stages.

Abstract: A bus switch has control of the timing of turning on and off the main p-channel and n-channel transistors that connect two network nodes. A pair of cross-coupled NAND gates form a set-reset S-R latch that controls the gates of the main p-channel and n-channel transistors. The S-R latch controls the timing so that the main p-channel and n-channel transistors switch at about the same time, canceling much of each other's injected charge. Since the main p-channel is larger due to the lower hole mobility, an excess of injected charge from the p-channel transistor remains. This excess charge is cancelled by opposite charge injected by compensating transistors. The compensating transistors are also p-channel devices, but are driven with a logical inverse of the gate of the main p-channel transistor. This produces a charge with opposite polarity to the excess charge from the main p-channel transistor.

Abstract: An apparatus and method for delaying a signal using a variable delay line circuit. A variable delay line circuit includes first and second delay lines, each including a plurality of delay elements. A multiplexer is coupled to respective outputs of the first and second delay lines and selectively couples the output of one of the first or second delay lines to an output of the multiplexer. A control circuit is coupled to the multiplexer and the first and second delay lines, and controls the multiplexer so as to produce a delayed signal at the multiplexer output using one of the first or second delay lines, and changes a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines.

Abstract: An electronic vernier realizes programmable gain steps with first and second impedance ladders, a plurality of activatable coupling networks and a switch network. The ladders receive and progressively process the differential input signal into a plurality of progressive differential signals. In an embodiment, the coupling networks each generate a respective one of a plurality of progressive differential output signals in response to a respective one of the progressive differential signals and the switch network activates any selected one of the coupling networks. Thus, any selected vernier step is obtained by activating the respective coupling network. The verniers can be integrated into various systems, e.g., programmable amplifiers.

Abstract: A drive circuit for driving scanning lines or data lines in an EL or plasma display panel has a pair of power recovery lines each connected to a corresponding one of two thyristors. The first thyristor recovers electric power from the scanning line and the second thyristor supplies the electric power to another scanning line. The lower ON-resistance and lower parasitic capacitance of the thyristors provides an efficient recovery of the electric power while suppressing a latch-up failure of CMOSFETs.

Abstract: Circuit techniques for allowing the sharing of the same output terminals between transmission line drivers that comply with differing protocols. By inserting isolation transistors at the outputs of line driver circuits, and in a preferred embodiment along the current loop of a current-output line driver circuit, the invention allows the sharing of output pins while meeting all the power on and power off requirements of different protocols.

Abstract: A voltage converter circuit (10) includes a primary P-type FET (20) having its source-drain conduction path connected between an input (22) and a first output node (23). An N-type FET (21) is connected in parallel with the primary P-type device (20) between the input (22) and first output node (23). The gate electrode of the primary P-type device (20) is connected to the first output node (23) while the gate electrode of the N-type device (21) is connected to a second voltage supply at the voltage level of a desired second voltage signal. A first digital signal at a first voltage level is applied to the input (22). The voltage produced at the first output node (23) equals the desired second voltage level and comprises the input signal voltage reduced by the threshold voltage of the primary P-type device (20). One or more additional P-type devices (40) may be connected in series with the primary P-type device (20) to reduce the output voltage level further.

Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.

Abstract: A loading device for use in a tester for testing a semiconductor integrated circuit device (DUT) includes a programmable voltage source for providing a selected voltage at an output terminal thereof and multiple resistive elements each having at least a first state, in which the resistive element is conductive, and a second state, in which the resistive element is substantially non-conductive. The resistive elements are connected as a two-terminal network between the output terminal of the programmable voltage source and a tester pin for connection to a pin of the DUT. A selection device selects the state of each resistive element, whereby the resistance between the output terminal of the programmable voltage source and the tester pin can be selectively varied.

Abstract: The present invention provides a switch circuit having a switch and a first body grabbing circuit. The switch includes a first transistor and a second transistor. The first transistor has a body and is coupled to the second transistor in parallel to form a common source and a common drain. The common source defines an input node and the common drain defines an output node. The first body grabbing circuit is coupled to the body of the first transistor. The first body grabbing circuit is arranged to couple the body of the first transistor to the input node when the first and second transistors receive a turn-on voltage signal such that a body effect is eliminated in the first transistor.

Abstract: A multiplexer has first, second, third and fourth inputs receiving respective first, second, third and fourth input signals, having first and second control inputs receiving respective first and second select input signals and an output. Each of the four input signals is supplied to the input of a CMOS transmission gate. The first and second transmission gates are clocked via the first select signal and its inverse in a first phase. The third and fourth transmission gates are clocked via the first select signal and its inverse in a second phase, opposite to the first phase. A first embodiment includes a first intermediate inverter having an input connected jointly to the outputs of the first and second transmission gates and a second intermediate inverter having an input connected jointly to the outputs of the third and fourth transmission gates.

Abstract: An on-chip resistance to an input current of an input signal includes a parallel transistor resistor and a control circuit for biasing the transistors of the parallel transistor resistor. The parallel transistor resistor includes first and second transistors of first and second types. Each transistor includes first and second current handling terminals and a control terminal. The control terminals are coupled to receive control signals from the control circuit. The first current handling terminals are coupled to provide an input node for receiving an input signal, and the second current handling terminals are coupled to provide an output signal. The control circuit is coupled to provide the first and second control signals for biasing the respective first and second transistors so that a first derivative of a resistance of the parallel transistor resistor in relation to an input-to-output voltage is zero at a selectable operation point.

Abstract: An apparatus and method is provided with hysteresis for switching a load according to an input signal. There is a transfer gate for transferring a first signal to a second signal. A controller receives the first signal and the second signal and provides a control signal for the transfer gate. The control signal enables the transfer gate if the first signal reaches a first magnitude and disables the transfer gate if the first signal reaches a second magnitude. The control signal is obtained from a voltage divider across the first signal. A portion of the voltage divider is shorted out by a switch activated by a second signal. Thus, the control signal depends on the second signal. The apparatus is entirely powered by the second signal.

Abstract: A high power MOS transistor consists of a large number of sub-transistors (T1 to T6) connected in parallel. The gate electrodes of the sub-transistors (T1 to T6) can be driven individually via controllable switching elements (SW1 to SW6; SQ1 to SQ5).

Abstract: A first FET is connected between first and third nodes, a second FET is connected between second and fourth nodes, a third FET is connected between third and fifth nodes and a fourth FET is connected between fourth and fifth nodes. A fifth FET is connected between first and sixth nodes and a sixth FET is connected between second and sixth nodes. The gates of the first, fourth and sixth FETs are connected to a first control terminal and the gates of the second, third and fifth FETs are connected to a second control terminal. A power-supply terminal is connected to the fifth and sixth nodes. The first and second nodes are connected to a common terminal through first and second capacitors, respectively. The fifth and sixth FETs form a pull-up switching circuit. The pull-up switching circuit pulls up the source of an FET in an OFF state to the power-supply voltage and isolates the source of an FET in an ON state from the power-supply voltage.

Abstract: A soft clipper circuit in CMOS technology not only allows the knee to be programmed, but also the slope of the curve after the knee to be programmed. This is accomplished by putting a second transconductance in parallel with the first transconductance, and using a switching circuit to connect the output of the second transconductance to that of the first transconductance when the knee level is reached. This is determined by a comparator which has an input coupled to the second transconductance and controls a control node of the switching circuit.

Abstract: Switches are provided on the input and output side of an amplification stage in a signal switching circuit provided in a signal transmission line, and another signal is provided so that a signal can be transmitted directly. Further, a switching circuit is formed from FET elements, which are controlled to be switched on/off by control signals to assure a high isolation.

Abstract: Circuits and method for isolating internal nodes of an integrated circuit from external signals applied to I/O terminals of the IC even under no-power conditions are disclosed. The invention senses the most positive voltage level (in case of a p-channel implementation) or the most negative voltage level (in case of an n-channel implementation) at two input or input/output (I/O) pads and uses that voltage to isolate the internal nodes of the integrated circuit from the pad, without requiring the circuit power supply for its operation.

Abstract: A signal transmission cable driver apparatus for transmitting an input signal through a transmission cable performs frequency compensation without using a peaking coil. The signal transmission cable driver apparatus includes a transmission driver for receiving the input signal and driving the transmission cable to transmit the input signal therethrough, and transition signal drive means having a capacitor circuit for detecting transition of the input signal by charge/discharge in the capacitor circuit and amplifying currents in said charge/discharge of the capacitor circuit, wherein the currents amplified by the transition signal drive means are superimposed on the input signal driven by the transmission driver at an input of the transmission cable.

Abstract: A clock circuit for generating alternate clock phases (P.sub.1, P.sub.2) whose trailing edges define sampling points of an analog-to-digital converter (106). Complementary signals (CLOCK0, CLOCK1) are generated from a system clock (F.sub.SYS) and switched through transmission gates (340-341, 342-343) when an enable signal (V.sub.EN) is applied. The system clock (F.sub.SYS) is delayed by a delay circuit (316) to produce the enable signal (V.sub.EN) after the complementary signals (CLOCK0, CLOCK1) are stable, thereby synchronizing the complementary signals (CLOCK0, CLOCK1) with the enable signal (V.sub.EN).

Abstract: Data are transmitted from a control device through an interface cable to a set of driver devices in synchronization with an external clock signal, or a complementary pair of external clock signals. The signal line or lines carrying the external clock signal or signals are terminated at both ends by resistors with resistance values matching the characteristic impedance of the interface cable. Each driver device has a comparator that compares the external clock signal with a regulated reference voltage, or compares the two complementary external clock signals with each other, and thereby generates an internal clock signal. The driver devices receive the data in synchronization with these internal clock signals.

Abstract: A bi-directional high-voltage RESURF EDMOS (REduced SURface Extended Drain MOS) transistor which can endure a high voltage at its source by providing drift regions at both sides, i.e., the source and drain of the conventional RESURF LDMOS (Lateral DMOS) transistor, and exchanging the drain and the source when an analog signal of high voltage is inputted. Further, the bi-directional high-voltage RESURF EDMOS transistor provides a high-voltage analog multiplexer circuit employing a RESURF EDMOS transistor which is capable of reducing the number of necessary high-voltage elements and performing a stable operation, by constructing a high-voltage analog multiplexer having at least three inputs and a multistage high-voltage multiplexer circuit of push-pull type, pass transistor type, and combined form of push-pull type and pass transistor type by using the bi-directional high-voltage RESURF EDMOS transistor.

Abstract: An output buffer is provided which receives an input signal for output onto an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage corresponding to a logic value of the input signal. The second driver has a higher driving capacity than the first driver. The output buffer also has control circuitry receiving a transition in logic value of the input signal and at least one mode signal. The control circuitry responds to the transition in logic value by delaying the second driver from driving the output terminal to a complementary voltage until after the first driver begins to drive the output terminal to the complementary voltage. In so doing, the control circuitry delays the second driver by a first delay, when the mode signal(s) indicates a full speed mode. On the other hand, the control circuitry delays the second driver by a second delay, that is longer than the first delay, when the mode signal(s) indicates a low speed mode.

Abstract: Six sets of parallel-connected MOSFETs are gated to provide a 3-phase output. At least one of the MOSFETs in each of three sets of the six sets has a separately metallized current-sensing pad. The output from this pad represents the phase current. When phase current reaches a maximum permissible level, this signal controls the MOSFET gates to limit current.

Abstract: A method and apparatus for low power transmission of digital data. A low power data transmission circuit includes a pass gate having parallel-connected n and p-channel CMOS transistors that transmit input data. To reduce power in a first embodiment, a circuit disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle. In a second embodiment, the circuit disables the parallel-connected n-channel pass gate transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle.

Abstract: A voltage level shift circuit has a first input receiving a first voltage signal and a second input receiving a second voltage signal. The voltage level shift circuit is structured to generate an output voltage at an output terminal which is equal to a sum of the first and second voltage signals. The first voltage signal may be varied to vary a shift of the second voltage signal.

Abstract: Circuitry for controlling load current, in accordance with the present invention, utilizes a load drive transistor configuration operable to provide a first load current path having a first fraction of load current flowing therethrough and a second load current path having a second smaller fraction of load current flowing therethrough. The circuit includes a sense resistor associated with the load drive transistor to detect various load current threshold values. In order to reduce debiasing effects of the sense resistor upon the second load current path of the load drive transistor, a compensation resistor is provided between drive inputs associated with each of the two current paths. The compensation resistor has a compensation voltage established thereacross which is operable to negate the debiasing effect of the sense resistor on the load driving device.

Abstract: A MOSFET switched, redundant power supply has a back-to-back MOSFET switch connecting respectively each power supply to a single load. Each power supply has a positive and negative gate voltage source. In a specific N-channel MOSFET embodiment, the positive (i.e. on) bias is coupled to each switch via a radiation hardened, redundant analogue switch capable of being driven by, for example, a TTL or CMOS microprocessor signal. The negative (i.e. off) bias is coupled to each via a redundant diode pair. In addition, the gates of the back-to-back MOSFET switch for one power source are also connected to the negative bias of the other power source. In this way the MOSFET switch for a failed power supply will be maintained in an off state by the negative bias provided by the redundant supply.

Abstract: A current source providing a voltage-controlled variable-current reference is described which employs a conventional current mirror to supply a current to a diode-connected transistor, and to a plurality of controllable current paths, wherein the controllable current paths are controlled by voltages from a voltage sensing circuit so that predetermined amounts of current are drawn away from the diode-connected transistor as function of a controlled voltage, so that the diode-connected transistor generates a voltage as a function of the current flowing through it which voltage is used to control an output transistor and a current flowing through the output transistor.

Abstract: A switching circuit is made by serially connecting two field effect transistors in series in a small-signal transmission path, each of the transistors being applied with a substantially equal voltage, so as to lower a voltage applied to each of the FETs in the OFF state by voltage division, with the result that a high withstand voltage of the transmission path can be attained and a linear output can be obtained even when a large electric power is transmitted.

Abstract: An improved CMOS current source circuit capable of constantly generating a certain reference voltage irrespective of an analog supplying voltage, a substrate temperature, and a temperature variation, which includes a start unit for driving the CMOS current source circuit in accordance with a start signal; a bias current generating unit driven by the start unit for generating a bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation; a current input unit for inputting a bias current; and a current compensation unit for receiving a bias current through the current input unit and for compensating the bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation and for generating a reference current.

Abstract: Switching regulator circuits and methods are provided in which the output circuit is adaptable to maintain high efficiency over various load current levels. The regulator circuits generate one or more control signals in response to the load current and selectively route a switch driver control signal to one or more switches in the output circuit. The switches differ in their size, such that the most efficient switch can be used at a particular load current level. At low load current levels, the driver control signal is routed to output circuitry with smaller switch devices, which incur smaller driver current losses for a given frequency of operation, thereby increasing the regulator efficiency. At high load current levels, the driver control signal is routed to large switch devices, which incur greater driver current losses for a given frequency of operation, but which have a lower impedance.

Abstract: A semiconductor chip incorporating a current generating circuit that will both power-down selected circuitry during inactive or standby periods and yet maintain a bias current to other parts of the chip. More specifically, the current generating circuit has output lines for providing output currents that mirror the current source during chip power-on operation periods. During chip power-down operation periods, the current generating circuit uses a current bias generator to supply current only to circuits needing to be operational during a partial chip operational mode.

Abstract: A bidirectional current blocking switch is disclosed. The switch includes a four-terminal MOSFET in which there is no source-body short. The voltages applied to the source and drain terminals are both higher than the voltage applied to the body terminal (for an N-channel) device so that the source-body and drain-body junction of the MOSFET never become forward-biased. The switch of this invention is particularly useful for switching a cascaded set of batteries in a portable computer. Also included is a disclosure of circuitry to protect the switch against a reverse connected battery charger.

Abstract: A current mirror circuit for mirroring current in CMOS integrated circuit technology includes a current mirror arrangement formed of first and second P-channel MOS transistors (MP32,MP33), a variable input current source (I.sub.CS), a first source follower transistor (MN34), a second source follower transistor (MP35), a current-sinking transistor (MN31), and a load circuit 212. The load circuit is formed of a load transistor (MN36) and a load resistor (R1). In an alternate embodiment, the load circuit is formed of a single load resistor. As a result, the amount of current injected into the first P-channel MOS transistor (MP32) is more precisely mirrored into the second P-channel MOS transistor (MP33).

Abstract: An electronic driver circuit for low-impedance loads, being of a type which comprises an input terminal (IN) to which a voltage signal (Vin) is applied for alternate transfer to an output, and a plurality of output terminals (OUTi), each connected to a corresponding electric load (2), further comprises, between the input terminal and the output terminals, a single operational amplifier (3) having multiple output stages (7), one for each output terminal (OUTi). The operational amplifier (3) is of the single-ended or fully differential multistage type and allows each load to be driven alternately by activation of the corresponding output stage (7i).

Abstract: A flip-flop with scan capability includes a four switches, a master stage, a slave stage and a scan-out logic gate. The flip-flop can operate in a functional mode, and a scan mode and receives a clock signal, a data signal, a scan clock signal and a scan-in signal. The flip-flop enters the functional mode when the clock signal runs free and the scan clock signal is held constant. The first switch receives the data signal and provides the data signal to the master stage for storage during a first part of a clock cycle. During a second part of the clock cycle, the third switch, connected between the master stage and the slave stage, closes, providing the data stored in the master stage to the slave stage and outputted as a q output signal. The flip-flop enters the scan mode when the clock signal is held constant and the scan clock signal runs free. The first switch is controlled to stay open by the constant clock signal.

Abstract: Fault protection using parallel output CMOS devices for integrated circuit analog switches prevents damage to circuits incorporating the same by not coupling analog input voltages beyond the power supply voltages to the analog output, and by preventing the forward biasing of any P/N junction to provide a low impedance path between such fault analog input voltage and either power supply terminal. Circuitry is provided for having the analog output electrically floating whenever the switch is commanded off, regardless of whether the analog input is within the power supply voltage range or not, to provide the analog input as the analog output whenever the switch is commanded on and the analog input is within the power supply voltage range, and to clamp the analog output at the closest power supply voltage whenever the switch is commanded on and the analog input is beyond the power supply voltage range. Alternate embodiments are disclosed.

Abstract: A logic circuit for implementing a flip-flop circuit that operates stably and at high speed at a low supply voltage of about 1 V. The logic circuit includes transistors 25,26,31 for forming a first current mirror circuit 2; transistors 27,28 for converting clock signals to current signals; transistors 19,22,23 for forming a second current mirror circuit 3; and transistors 20,21,24 forming a third current mirror circuit 4. These current mirror circuits supply a current nearly equal to the current from transistors 27,28 to the circuits connected respectively to those current mirror circuits. Transistors 29,30, current source 47, voltage source 50 and voltage comparison circuit 51 form a voltage maintenance circuit. Transistors 11,12 and resistors 41,42 form an input stage of a master D flip-flop D-FF, and transistors 13,14 form the signal-holding row of the master D flip-flop D-FF.

Abstract: The present invention relates to a system for neutralizing charge injection problems in a switched current system. The system is comprised of a PMOS transistor coupled in parallel with an NMOS switch transistor. If the channel area of the PMOS transistor and the NMOS transistor are equal, then the clock signal to the PMOS transistor must be adjusted to neutralize the negative channel charges of the NMOS transistor. However, if the clock signal to both the PMOS transistor and the NMOS transistor are equal, then the dimension of the PMOS transistor must be smaller than the NMOS transistor in order to neutralize the negative channel charges of the NMOS transistor.

Abstract: An integrated circuit (IC) with metal-oxide semiconductor field effect transistor (MOSFET) circuitry and on-chip protection against oxide damage caused by plasma-induced electrical charges includes a MOSFET circuit for receiving and processing an input signal and a complementary MOSFET pass gate coupled to the input thereof for receiving and passing the input signal thereto. The complementary MOSFET pass gate includes complementary MOSFETs with control terminals, input terminals and output terminals, with the control terminals being connected for receiving the IC power supply voltage and ground potentials, the input terminals connected together for receiving the input signal and the output terminals connected together and to the input of the MOSFET circuit for passing the input signal thereto in response to the receiving of the IC power supply voltage and ground potentials.

Abstract: An input cell circuit for an integrated circuit for use in a mixed signal mode where an input pin may receive either digital or analog signals. The circuit solves the problem where several such pins are used in a mixed signal mode and share a common internal bus. Such input signals will cause erratic values on the common analog bus, if any given input pin is used as a digital input signal and the voltage on that input pin exceeds the supply voltage by the base-emitter voltage of the parasitic transistor in the P-channel transistor in a pass gate in the associated input cell. This problem is solved by adding a second P-channel transistor to the pass gate and also adding an N-channel transistor connected to a node between the two P-channel transistors, as well as adding an input resistor.

Abstract: Arrangement for providing improved current source signals in a DAC current source circuit including a current source transistor, an output transistor, and a switching transistor for selectively grounding the source current or directing it through the output transistor. The DAC current source circuit includes a high gain double cascode device for electrically isolating the current source and output transistors from the switching transistor. The isolation device may include one, two or more transistors in series. The arrangement further includes a matching circuit at the input of the DAC current source circuit.