Abstract: An electronic switch having a reduced body effect includes first and second switch terminals. A first transistor of a first type has a control terminal, a first substrate coupled to a first voltage level, and first and second drive terminals respectively coupled to the first and second switch terminals. A second transistor of a second type has a control terminal, a second substrate, a first drive terminal coupled to the second substrate and to the first switch terminal, and a second drive terminal. A third transistor of the second type has a control terminal, a third substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the third substrate and to the second switch terminal. A fourth transistor of a first type has a control terminal, a fourth substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the fourth substrate and a first voltage level.

Abstract: A waveshaping circuit for a sense amplifier pulldown device receives a standard digital signal at its input and independently creates a signal with two distinct rising slopes at its output. This unique output signal activates the sense amplifier pulldown device slowly at first with the first rising slope then quickly saturates it with the second rising slope allowing the sense amplifier to accurately sense and amplify the voltage difference between two digit lines.

Abstract: A driver circuit (8) is arranged to switch a transistor (10) of a switched capacitor circuit, or transistors (62 and 64) of a differential switched capacitor circuit, between a first state, in which the transistor switch is closed whereby an input signal (VINP) is transferred to an output, and a second state, in which the transistor switch is open. The driver circuit includes a maximum and a minimum selection (12, 14) between the input signal and a reference voltage (VAG) , a voltage shift element (26), and switches (16, 18, 20, 22, 24), coupled to receive the input signal (VINP) and to the gate electrode of the transistor switch (10), which ensures that the gate-to-source voltage of the transistor switch (10), in the first and second states, is independent of the input signal (VINP).

Abstract: A circuit configuration for noise signal suppression includes an input signal terminal and two inputs being controlled by the input signal terminal. Transfer gates are each connected in series with a respective one of the inputs and have a terminal being connected to the input signal terminal. A transistor is connected as a capacitor in parallel with each of the inputs.

Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fiber communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit utilizes a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.

Abstract: A bus driver circuit includes a plurality of first MOS transistors connected in series between a data input terminal and a data output terminal, and a plurality of second controlling MOS transistors. Sources of said plurality of first MOS transistors are connected to drains of said plurality of second controlling MOS transistors. Also, gates of said plurality of second controlling MOS transistors to control signal source means for selectively turning ON and OFF said plurality of second controlling MOS transistors. The bus driver circuit thus constructed permits selection of optimal rise-up and fall-down transition period for achieving high speed and efficient data transmission.

Abstract: The present invention provides non-cut fuses and/or conductive transmission gates to control signal flow, and cut fuses and non-conductive transmission gate paths to prevent cross-talk from occurring.

Abstract: A power switch includes two power FETs connected back-to-back in series at a common source node and a common gate node and a resistor connected between the common source node and the common gate node. The switch further includes a current source and a single-control switch connected to the current source and to the gate node for switching the current source to the gates of the two power FETs.

Abstract: A signal line switching circuit includes a switching and driving circuit connected in parallel to a pair of complementary signal lines to be switch-controlled and having a current supply capability sufficiently larger than that of an amplifier having its pair of complementary outputs connected to the pair of complementary signal lines. The switching and driving circuit can supply onto at least one of the pair of complementary signal lines a signal which is independent of a level of the outputs of the amplifier and which corresponds to a test discrimination result signal.

Abstract: A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.

Abstract: An electronic switch for sampling a signal. A small switch is placed in parallel with a large switch. The large switch is opened first. Any residual charge from the large switch is compensated by a low impedance path through the small switch. Speed is maximized by providing high current capacity through the large switch. Noise is minimized by leaving only residual charge from the small switch. Example embodiments are provided for sampling both voltage and current signals.

Abstract: Circuits embodying the invention include means for sensing certain characteristics (e.g. speed of response and conductivity) of the transistors formed on an integrated circuit (IC) and for using the sensed results to control the operation and structure of a circuit formed on the IC. An output driver circuit embodying the invention includes numerous pull-up transistors connected in parallel between a high power supply line and an output terminal and numerous pull-down transistors connected in parallel between the output terminal and the low power supply line. The number of transistors which are turned-on at any one time is selectively controlled as a function of the characteristics (e.g. conductivity and speed of response) of the transistors of the circuit. The higher the speed of response or the conductivity of the transistors, the fewer the number of pull-up or pull-down transistors which are turned-on.

Abstract: A switching circuit that includes two parallel connected switching transistors. A primary winding of a transformer is connected across the drain electrodes of each of the switching transistors and a secondary winding of the transition transformer is connected to the gate electrodes of the transistor. A capacitor is connected in series with the primary winding to isolate the primary winding from the switching circuit when in a steady state operation. The secondary winding shorts the commonly connected gate electrodes in the steady state condition. The differential in voltage between the drain electrodes is used to activate the primary winding of the transformer which induces a correction voltage in the secondary winding to cause the transistors to operate at the same rate.

Abstract: An apparatus for enabling an IC pin to function in a dual mode, which apparatus includes a first switch for coupling the IC pin to an input terminal when the IC pin operates in an input mode, and a charging circuit for sourcing current to the IC pin during a charging cycle of a timer mode. The inventive apparatus further includes a discharging circuit for sinking current from the IC pin during a discharging cycle of the timer mode. In one embodiment, the inventive apparatus further includes a comparator for generating an activation signal, the activation signal being activated when a potential at the IC pin equals or exceeds a predefined voltage in the timer mode. In another embodiment, the comparator is disabled during the input mode.

Abstract: A CMOS pass gate receiver improves chip-to-chip communication speed for high speed chips. The high speed CMOS pass gate receiver is immune to overshoot or undershoot and can operate in a frequency greater than or equal to 400 Mhz.

Abstract: A semiconductor integrated circuit comprises an input signal terminal to which an input signal is supplied from an outer unit, a plurality of input voltage sensing circuits each having a different circuit threshold value and connected to the input signal terminal, for sensing whether a voltage of the input signal is higher or lower than a predetermined normal level, a power supply voltage sensing circuit for sensing whether a power supply voltage applied from another outer unit is a normal power supply voltage or a voltage different from the normal power supply voltage, a selection circuit for selecting a corresponding one from a plurality of the input voltage sensing circuits in accordance with an output of the power supply sensing circuit, and an internal circuit to which an output of a selected one of the input voltage sensing circuits is connected.

Abstract: An output buffer circuit for a high density programmable logic device. The output buffer includes inverters having n-channel pull up and pull down transistors for driving pull up and pull down transistors providing the buffer output. By utilizing inverters with n-channel replacing p-channel transistors, crowbar resulting from a different number of inverters required to drive the pull up and pull down transistors which provide the buffer output is prevented. By utilizing n-channel rather than p-channel transistors, mobility is increased and Miller capacitance is reduced, reducing loading of the buffer input. To provide the rail-to-rail voltage of p-channel transistors which can further increase switching speed, p-channel pull up transistors are provided with circuitry to turn the p-channel transistors on after the n-channel transistors have turned on and turn the p-channel transistors off after the buffer output switches.

Abstract: An FET switch used for switching between a first transmission path includes a plurality of FETs for the transmission of a low power signal received at an antenna and a second transmission path including a plurality of FETs for the transmission of a higher power signal to the antenna, wherein the first transmission path and the second transmission path have FET circuits of configurations different from each other and/or employ FETs of different characteristics.

Abstract: A current divider for linearly dividing a first signal current (Ii10) into a second and a third signal current (Io11, Io12) includes a first terminal (I10) for the passage of the first signal current (Ii10), a second terminal (O11) for the passage of the second signal current (Io11) and for receiving a first potential, a third terminal (O12) for the passage of the third signal current (Io12) and for receiving a second potential, a first MOS transistor (M1) having a control electrode and a main current path, and a second MOS transistor (M2) having a control electrode and a main current path, the control electrodes of the first and the second MOS transistor (M1, M2) being coupled to a first reference terminal (R10) for receiving a first reference voltage (Rv10) to realize a conductive state of the first and the second MOS transistor (M1, M2) during a first active state of the current divider, the main current path of the first MOS transistor (M1 ) being coupled between the first terminal (I10) and the second te

Abstract: An integrated circuit may have a mode to be switched over if a predetermined signal voltage is input through a mode switching terminal when the predetermined voltage is applied to one or more signal input terminals. The integrated circuit is provided with a voltage setting circuit disposed between the signal input terminal and the logic circuit, for setting the signal input terminal to receive any voltage in the range of a ground voltage to a power source voltage in response to a signal voltage input through the mode switching terminal.

Abstract: A main P-channel field effect transistor 1 exhibiting a larger current driving capacity and an auxiliary P-channel field effect transistor 8 exhibiting a smaller current driving capacity are coupled in parallel across the input terminal 2 and the output terminal 3. When a voltage is applied on the input terminal 2, the output of the comparator 7 falls to the low level L, and the auxiliary P-channel field effect transistor 8 is first turned on. Since the current driving capacity of the auxiliary P-channel field effect transistor 8 is small, the voltage at the output terminal 3 rises gradually at a limited rate. When the voltage at the output terminal 3 exceeds a predetermined level, the output of a second comparator 9 falls to the low level L, and thereby turns on the main P-channel field effect transistor 1.

Abstract: A transmission gate circuit 20 includes a pull-up control circuit 15, a pull-down control circuit 17, and an electrical switch 19. Pull-up control circuit 15 and electrical switch 19 provide fast, complete transition from low-to-high at the output of circuit 20 thus improving circuit 20 speed as well as improving the switching speed of subsequent gates. Pull-down control circuit 17 and electrical switch 19 provide complete transition from high-to-low at the output of circuit 20. Transmission gate circuit 17 also provides increased drive such that circuit 20 may provide a gate fanout increase of 3X.

Abstract: A programmable analog N.times.M switching network that includes a charge-coupled-device (CCD) multiplexer switch means having a plurality of N input leads. The input leads contain signals from typical devices such as video cassette recorders, televisions, video cameras, cable TV telephones or the like. The CCD multiplexer switch means also includes a plurality of M output leads that provide signals to other typical devices which also may be video cassette recorders, televisions, telephones, etc. A programmable read-only memory (PROM) clock generator provides signals to CCD gates in the CCD multiplexer switch means to enable the multiplexer switch means 10 to selectively connect the input signals and leads to the output leads. The programmable PROM is controlled by means of programming request means which may be a computer or an operator console.

Abstract: An active circuit comprising a component coupled between an input terminal and an output terminal, the component requiring power to operate, and a bypass path which causes a signal to propagate from the input terminal to the output terminal via the component when the component is operating under power and which causes the signal to bypass the component, when the circuit loses power, and propagate from the input terminal to the output terminal via a section of transmission line, the bypass path comprising a bypass circuit having at least two FETs, the two FETs providing high and low impedances, the high impedance being provided when the component is operating, thereby causing the signal to propagate from the input terminal to the output terminal via the component and the low impedance being provided when the circuit loses power, thereby causing the signal to propagate from the input terminal via the section of transmission line to the output terminal.