Abstract: The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase.

Abstract: The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.

Abstract: A waveform generating circuit includes a constant current circuit that supplies a constant current through a power source; a current mirror circuit that flows an output current that is n times an input current; and a switching circuit that switches a flowing direction of the current in the constant current circuit between the current mirror circuit and the output terminal according to the logical level of the rectangle input signal. The waveform generating circuit generates a triangle wave having a falling slope waveform that is n times the rising slope. On the other hand, the waveform generating circuit that receives an inverted signal of the signal generates a triangle wave and its voltage is compared with another in the comparator to generate an output signal.

Abstract: An exemplary aspect of an embodiment of the present invention is a voltage-current converter converting an input voltage input to an input terminal to a current to output the current, the voltage-current converter including a first current generating circuit including an input transistor having a gate connected to the input terminal and generating an output current according to a current flowing in the input transistor, and a second current generating circuit including a transistor having a gate having a potential different from potential of a source and a drain, the second current generating circuit generating a superimposed current according to the current flowing in the transistor to supply the superimposed current to the input transistor.

Abstract: A differential signal receiving circuit includes: a first differential circuit of a plurality of depletion type transistors of a first conductive type and having a first output node and a second output node; and a second differential circuit of a plurality of enhancement type transistors of a second conductive type opposite to the first conductive type, and having output nodes respectively connected with the first and second output nodes. An inverter circuit is connected between the first output node and the second output node.

Abstract: Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor circuit.

Abstract: A DC stabilization circuit for an organic electroluminescent display device and a power supply using the same are provided. The DC stabilization circuit includes a self-bias part connected between a first power supply voltage and a reference power supply. The self-bias part generates a bias voltage depending on the first power supply voltage. The circuit also includes a differential part connected to the self-bias part that amplifies a variation in the bias voltage. A negative feedback part is connected to the differential part, adjusts a level of a second power supply voltage using a variable resistor, and compensates for the amplified variation of the bias voltage through a negative feedback operation.

Abstract: A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input terminal and the first output terminal are directly connected. Additionally, the system includes a switch coupled to the first output terminal and a first node. The switch is controlled by at least a first control signal. Moreover, the system includes a comparator including a third input terminal, a fourth input terminal, and at least a second output terminal. The comparator is configured to receive a first input signal at the third input terminal and a second input signal at the fourth input terminal. The first input signal and the second input signal are associated with the first node and the predetermined voltage.

Abstract: A dual reference input receiver, and a method of receiving, wherein the input receiver includes a first input buffer which is synchronized with and enabled by a clock signal, senses a difference between the input data signal and a first reference voltage, and amplifies the sensing result; a second input buffer which is synchronized with and enabled by the clock signal, senses a difference between a second reference voltage and the input data signal, and amplifies the sensing result; and a phase detector which detects a difference between a phase of output signals of the first and second input buffers, and outputs a signal corresponding to the detection result. The first and second reference voltages may respectively be higher and lower than a median voltage of the input data signal. Thus, a single input data signal is advantageously used and a wide input data eye is provided.

Abstract: An amplifying circuit of a semiconductor integrated circuit includes a data amplifier that outputs an up-signal and a down-signal amplified according to a comparison result between an up-data signal and a down-data signal in response to a control signal. The data amplifier repeats an operation of amplifying the up-signal and the down-signal according to the comparison result between the up-signal and the down-signal to be fed back to the data amplifier.

Abstract: Disclosed are an input buffer, and more particularly, a technique that is capable of improving the operation speed of the input buffer by improving response speed with respect to an input signal. The input buffer includes a buffer unit that operates when an activation control signal is activated, compares the voltage of an input signal to a preset reference voltage, and outputs the result of the comparison to an output node, a driving unit that performs driving control on an output of the buffer unit, and outputs an output signal, and a pull-down control unit that outputs a pull-down control signal that has a high pulse for a predetermined time when transition of a potential of the input signal occurs.

Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.

Abstract: A digital output sensor (110) includes a sensing structure (105) including at least one sensing element. The sensing structure (105) outputs a differential sensing signal (106, 107). An integrated circuit (100) includes a substrate (101) including signal conditioning circuitry for conditioning the sensing signal (106, 107). The signal conditioning circuitry includes a differential amplifier (115) coupled to receive the sensing signal and provide first and second differential outputs (116, 117), and a comparator (120) having input transistors (Q27, Q28) coupled to receive outputs from the differential amplifier. The comparator (120) also includes first and second current-mirror loads (Q19/Q21 and Q22/Q20) coupled to the input transistors (Q27, Q28) in a cross coupled configuration to provide hysteresis, wherein the first and second current-mirror loads provide differential drive currents (121,122). An output driver (125) is coupled to receive the differential drive currents (121, 122).

Abstract: A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion.

Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

Abstract: A method, apparatus and system of constant output common mode voltage of a pre-amplifier circuit are disclosed. In one embodiment, a system includes a first circuit, a comparator circuit coupled with an output of the first circuit, a pre-amplifier circuit of the comparator circuit, a tracking circuit coupled with a common output location of the pre-amplifier circuit to provide (e.g., source/sink) an additional current to the common output location of the pre-amplifier circuit using an alternate current path in the tracking circuit when an input common mode of the pre-amplifier circuit is beyond a saturation range, and a second circuit of the comparator circuit coupled with the pre-amplifier circuit. A scaled version of a pair of input transistors of a pre-amplifier circuit of the tracking circuit may be created using a scaling factor (‘N’).

Abstract: A detecting circuit is disclosed. In the detecting circuit, when an input detection voltage Vsns which is obtained by dividing an input voltage Vin by resistors is equal to a reference voltage Vref or more and a temperature detection voltage Tsns is equal to the reference voltage Vref or more due to a low temperature, a detection signal SNS from a comparator becomes a high level. In addition, when the input detection voltage Vsns is less than the reference voltage Vref and/or the temperature detection voltage Tsns is less than the reference voltage Vref due to a high temperature, the detection signal SNS from the comparator becomes a low level.

Abstract: Embodiments of the invention relate to a signal receiver inserted between a first and a second voltage reference and having a first and a second input terminal effective to receive differential signals and an output terminal effective to provide a converted signal. Advantageously, the signal receiver according to embodiments of the invention comprises a conversion stage inserted between the first and second voltage references and connected between the first and second input terminals of the signal receiver and an input terminal of an hysteresis comparator, connected in turn to the output terminal of the signal receiver. In particular, the conversion stage performs a conversion from any input signal received on respective input terminals to an intermediate signal provided on an output terminal and suitable for reception by the hysteresis comparator.

Abstract: Systems and methods provide multi-use input/output (I/O) pads for an integrated circuit. For example in accordance with an embodiment, the multi-use pads may be shared to support different integrated circuit functions via the pads, such as selectively for high-speed signaling or general I/O.

Abstract: A high-speed receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The high-speed receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the high-speed receiver assembly.

Abstract: The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory.

Abstract: A high-voltage switch circuit includes an enable control circuit, a feedback circuit, a boosting circuit, and a high voltage switch. The enable control circuit precharges an output node to a set voltage in response to an enable signal. The feedback circuit supplies a feedback voltage to an input node in response to a switch control voltage generated from the output node when the output node is precharged. The boosting circuit boosts the feedback voltage and outputs a boosting voltage to the output node, in response to clock signals, thereby increasing the switch control voltage. The high voltage switch is turned on or off in response to the switch control voltage, and is turned on to receive a high voltage and output the received high voltage. The boosting circuit includes an amplification circuit of a cross-coupled type.

Abstract: A current sensing circuit and a boost converter including the current sensing circuit are disclosed. The current sensing circuit includes a switching device, a sensing transistor, and a current sensing amplifier, and senses the current flowing through the switching device. The current sensing amplifier maintains a potential of an output terminal of the switching transistor substantially equal to a potential of an output terminal of the sensing transistor based on a difference between an output current of the switching device and an output current of the sensing transistor. Accordingly, the current sensing circuit accurately senses the current flowing through the switching device.

Abstract: A voltage comparator circuit is composed of a differential amplifier circuit receiving a pair of input signals to develop an output signal on an output terminal, and a waveform shaping circuit connected to the output terminal.

Abstract: A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion.

Abstract: A display panel driving circuit includes an input part for amplifying an input on-off signal so as to generate a first on-off voltage signal, a voltage signal generation part for generating a second on-off voltage signal which is varied in response to variations of the first on-off voltage signal, and an output part generating a push-pull output voltage as a driving voltage so as to drive a display panel in response to the first and second on-off voltages. The display panel driving circuit further includes a controlling part for controlling the voltage signal generation part so that a difference between on and off voltages of the second on-off voltage signal is not smaller than a predetermined voltage. Therefore, the push-pull output voltage whose response speed is well balanced when the push-pull output voltage increases and decreases can be generated without increasing electric power consumption and a circuit area.

Abstract: A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. Integration continues until a desired voltage or time is reached, resulting in a sufficiently reliable output. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion.

Abstract: Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.

Abstract: A regulated mirror current source circuit has an output transistor, a regulator for controlling the output circuit, and a current mirror having two or more current paths. The first path of the mirror is coupled in series with a current path of the output circuit, and the second path is coupled to the regulator, to provide feedback. The feedback can provide better precision, or reduced component area. The circuit can include cascode transistors, and the regulator can have integral control. The output transistor gate-source voltage is overdriven to reduce “on” resistance of the output transistor. When the output transistor is a high voltage transistor, its area can be reduced without sacrificing compliance.

Abstract: A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area.

Abstract: A self sensing reference system and method are described. The self sensing reference systems and methods facilitate efficient accurate access to information. In one embodiment, a self sensing reference system includes a main cascode component, a self referencing component, and a comparison verification component. The main cascode component receives input on a first current value and a second current value. The self referencing component establishes a plurality of data indications wherein a first data indication is established based upon a comparison of the first current value to the second current value. A comparison verification component verifies a second data indication.

Abstract: An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.

Abstract: A stable high-precision current detection circuit capable of continuously detecting load current through a load with extremely reduced power loss. The current detection circuit has a power transistor and a current detection transistor that are fed with a common power supply voltage and a common switching signal. A buffer circuit is provided for supplying an idling current to the output node of the current detection transistor while realizing the same virtual potential at the output terminals of these transistors. Thus, the buffer circuit always functions as a class-A amplifier.

Abstract: A comparator circuit includes a differential amplifier circuit, a latch circuit, and a control signal generating circuit. The latch circuit includes a pair of cross-coupled inverting amplifiers that pull the output signals of the differential amplifier to the high and low logic levels, a control transistor that activates the latch circuit in synchronization with a clock signal, and an equalizing transistor that equalizes the output signals when the latch circuit is inactive. The equalizing transistor is switched on and off by a control signal generated from the clock signal by the control signal generating circuit. The high-level potential of the control signal is lower than the high-level potential of the clock signal. Switching noise at the control electrode of the equalizing transistor is therefore reduced, permitting high-speed operation.

Abstract: An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the finite input resistance. The third circuit may be configured to cancel the current by (i) generating the current in response to presenting the voltage across a replica resistor having a resistance similar to the finite input resistance and (ii) passing the current away from the apparatus.

Abstract: Embodiments of a variable gain amplifier circuit are described. In one embodiment, multiple resistor devices are coupled in series to form a string of resistor devices and to receive an input current. A multiple input operational amplifier device has an amplifier output coupled to a feedback resistor in the string of resistor devices and multiple amplifier input pairs, each amplifier input being coupled into the string of resistor devices as a tap between two respective adjacent resistors, each amplifier input pair being controlled by a corresponding bias current transmitted from a respective bias current source.

Abstract: In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifiers are alternately activated by first and second differential clock signals, and when activated convert data received on differential input lines into logical values for storage in respective storage circuits. The storage circuits may be flip-flops, latches, keeper circuits, or other circuits for storing data.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: A logic device with low electromagnetic interference. The logic device includes a digital logic gate, a voltage-limited circuit and a current-limited circuit. The digital logic gate provides a corresponding digital logic function. The voltage-limited circuit is connected to the digital logic gate in order to provide a fixed voltage to the digital logic gate to thus reduce an output voltage swing of the digital logic gate. The current-limited circuit is connected to the digital logic gate in order to provide a fixed current to the digital logic gate to thus reduce a transient current of the digital logic gate. Accordingly, an electromagnetic interface (EMI) caused by switching of the digital logic gate is reduced with the reduced output voltage swing and transient current.

Abstract: An over-driver control signal generating apparatus includes a pulse generating unit for generating a pulse signal having a pulse width corresponding to a desired over-driving interval in response to an over-driving signal; a supply voltage level detecting unit for detecting a voltage level of a supply voltage to generate a detecting signal; and a selecting unit for outputting the pulse signal as a bit line over-driver control signal in response to the detecting signal.

Abstract: For dormant periods in which in data is not transmitted to a differential signal reception circuit, an amount of a constant current provided to output buffers of a differential signal transmission circuit is reduced. Consequently, power consumption in the differential signal transmission circuit and the differential signal reception circuit is reduced.

Abstract: A signal-processing circuit has a first and a second input, which receive a first and a second differential signal, a third input, which receives a common-mode signal, the first and second differential signals having an equal and substantially opposite trend with respect to the common-mode signal, and a first output supplying a first processed signal, equivalent to the first differential signal rectified with respect to the common-mode signal, and satisfying throughout its course a first relation of comparison with the common-mode signal. The processing circuit is provided with first formation means for formation of the first processed signal, which operate on the basis of the first differential signal, and second formation means for formation of the first processed signal, which operate on the basis of the second differential signal; the first and second formation means co-operate in the formation of the first processed signal.

Abstract: A current sensing circuit for sensing the current through a main switch, such as the PMOS or NMOS switches of a switching regulator, is disclosed. The circuit includes a mirror switch, said mirror switch being substantially similar to said main switch but with a smaller aspect ratio, a difference amplifier for ensuring that the voltage across said first leg and across said second leg are substantially equal and thereby to derive from said mirror switch a sensing current nominally equal to a current flowing in said main switch divided by a sensing ratio, a current source for producing a quiescent current in said difference amplifier and a compensatory device for compensating for said quiescent current such that said current sensing circuit can sense currents in the main switch which are smaller than the quiescent current multiplied by the sensing ratio. The compensatory device may be one or two switches essentially similar to the mirror switch.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: An apparatus for receiving an inputted signal in order to transmit the inputted signal from an external circuit to an internal circuit includes a comparing block, enabled by an enable signal, for outputting a logic value to the internal circuit in response to a voltage difference between the inputted signal and a reference voltage; a biasing block for biasing the comparing block in order to sink a current from the comparing block to a ground; and a bias control block for receiving a fixed control signal and outputting the fixed control signal in response to the enable signal.

Abstract: A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.

Abstract: A transconductance stage is provided. The transconductance stage includes a tail current source, a differential pair, and two current mirrors. The input to each of the current mirrors is connected to the drain of a separate one of the transistors in the differential pair. The two current mirrors each have two outputs so that one of the outputs can be used to determine whether the output current exceeds a threshold (e.g. nine-tenths of the tail current). If the source current exceeds the threshold, extra source current is switched in to the output so that output source current is increased. Similarly, if the sink current exceeds the threshold, extra sink current is switched in to the output so that the output sink current is increased. This way, the transconductance stage can supply large output currents in response to a large signal input but maintains low quiescent current for small input signals.

Abstract: A voltage-controlled amplifier for a signal processing system includes an input voltage reception end, a first voltage-to-current converter, a reference current generator, a gain adjustment circuit, a first current mirror, and an output circuit. The voltage-controlled amplifier adjusts a gain according to a variable control voltage, so as to transfer an input voltage to an output voltage according to the adjusted gain. When adjusting the gain, the present invention changes only an alternating current part of the input voltage, and can decrease noise, the production cost, and increase integration degree.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.