Abstract: The input amplifier with unilateral current shutoff for input signals with steep edges has a MOS transistor, the source or drain of which is connected to a node connected to an output stage. An N-channel MOS transistor, which is connected between the two P-channel MOS transistors of the input amplifier, prevents a shutoff of the P-channel MOS transistor by the steep edge input signals. The node is pulled upward to the operating voltage when the input signal is present.

Abstract: A current switching type switch circuit is constructed with a constant current source, a switch group consisted of a pair of P-type MOS transistors and a current mirror circuit consisted of first, second, third and fourth npn bipolar transistors. The sources of the P-type MOS transistors are connected in common and to a first power source via the constant current source. Complementary clock signals are input to the gates of the P-type MOS transistors. Collectors and bases of first and second npn bipolar transistors are respectively connected to drains of the P-type MOS transistors, and to bases of third and fourth npn bipolar transistors. Collectors of the third and fourth npn bipolar transistors are respectively connected to first and second load circuits. Also, emitters of all of npn bipolar transistors are connected to a second power source.

Abstract: A cell-sensing unit is applied to a memory device having a cell associated operably with a complementary pair of bit lines and a word line. The cell-sensing unit includes a current sense amplifier having a first input side adapted to be connected to the bit lines, and a first output side, and a voltage amplifier having a second input side connected to the first output side of the current sense amplifier, and a second output side. The current sense amplifier is capable of magnifying a difference between currents flowing through the bit lines during a read cycle of the cell, and generates a corresponding voltage difference at the first output side. The voltage difference is received by the voltage amplifier at the second input side, and has a magnitude sufficient to enable the voltage amplifier to generate an output signal at the second output side corresponding to data stored in the cell.

Abstract: A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complimentary data signals at their differential inputs.

Abstract: The circuit arrangement compares a quantity supplied by a first neuron MOS field effect transistor (M1) to a reference quantity that is made available by a reference source (R). A current mirror (SP) is provided therefor, this enabling a comparison of a second current (I.sub.2) supplied by a reference transistor (R) to a first current (I.sub.1) supplied by the first neuron MOS field effect transistor (M1). The evaluator circuit is activated or, respectively, decoupled by a first switch unit (S1) and a second switch unit (S2). What is thereby achieved is that no current flows in the evaluator circuit in the quiescent condition. The comparison result is applied to an inverter unit (IS). Since the inverter unit (IS) is decoupled from the evaluator circuit by the first switch unit (S1), an undefined level is never adjacent at the output (AIS) of the inverter unit (IS). This can be advantageously utilized in the further data processing in following stages.

Abstract: A low voltage CTAT current source includes a bipolar transistor connected across two series-connected resistors. A voltage developed across the resistors turns on the transistor, making the current through the resistors CTAT. A second transistor supplies the resistor current; its base (if bipolar) is connected to the node between the resistors, which are selected to limit the transistor's base-collector forward bias and collector-emitter voltage to a preselected fraction of the first transistor's V.sub.be, allowing the CTAT current source to operate with supply voltages of less than two junction voltage drops. A PTAT current can be combined with the CTAT current to create a temperature-compensated current. A low voltage current mirror has the respective bases of a pair of cascoded transistors connected across a resistor which is also connected between the bottom transistor's collector and a programming current.

Abstract: A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complimentary data signals at their differential inputs.

Abstract: A current-mode sense amplifier includes a current mirror circuit having an input branch controlled by a current input signal to be sensed and an output branch connected to a capacitor. The output branch and gates of current mirror transistors are connected to transistors for precharge operation. The sense amplifier needs no reference current, provides a low component count and is noise resistant.

Abstract: A sense amplifier and method are provided using current/voltage converters that are suitable for a multibit (2 bit/cell) memory device. The sense amplifier includes first and second current/voltage converters and a voltage comparator. The current/voltage converters each include a current mirror amplification unit to amplify an input current and a current mirror conversion unit to convert the amplified current into a voltage. A current to be sensed is applied to the first current/voltage converter and a reference current is applied to the second current/voltage converter. The voltage comparator determines a voltage difference by comparing the voltage output by the first and second current/voltage converters. The sense amplifier and method increases the speed and ease of sensing the input current. Further, the sense amplifier and method applied to a multibit memory can reduce an area for memory elements by 40%.

Abstract: A plurality of n-channel FETs in predetermined combinations are grouped two by two into pairs, and their respective gates and sources are connected to each other in a crossing manner, thus forming a first current mirror circuit connected to a higher-potential side power supply. A second current mirror circuit constituted by another plurality of n-channel FETs, diodes, and a variable resistor, which is connected to a lower-potential side power supply, is connected to the first current mirror circuit connected to the higher-potential side power supply, thereby forming a reference voltage generating circuit which generates a constant voltage. Further, three other pieces of n-channel FETs biased by this constant voltage, a diode, and the like constitute a light emitting element driving circuit for driving a light emitting element.

Abstract: A semiconductor memory device capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption even when the quick chip enable access is made possible. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths are set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

Abstract: A sense amplifier increases the differential voltage between a reference signal and a sense signal by using a current mirror to control the generation of the reference signal and the sense signal responsive to a common control signal. The sense amplifier includes a reference signal generator for generating the reference signal at a reference node responsive to a reference cell, a sense signal generator for generating the sense signal at a sense node responsive to the state of a memory cell, and a differential amplifier for amplifying the voltage difference between the reference signal and the sense signal. The reference node is coupled to the reference cell which discharges current from the reference node, and the sense node is coupled to the memory cell which discharges current from the sense node. The reference signal generator includes a first current source transistor that is coupled between a power supply terminal and the reference node.

Abstract: A balanced current amplifier mirrors either a fully differential or single ended input signal into common output circuits in a manner to generate a fully differential output signal without any d.c. bias. Input signal nodes are maintained at a desired voltage by circuit elements other than those of the current mirror circuits, thus freeing the current mirroring elements from having to be sized for this purpose. The sizes of the output transistors are adjustable in order to set the gain of the circuit. In addition to amplifier circuits, a full-wave rectifier, a comparator, and a filter, all operating with current signals, are described. A single circuit module may include all of these circuits with a user provided the capability to program the module to perform any one or more of these functions.

Abstract: A differential amplifier circuit whose noise is reduced when used in a CMOS operational amplifier without increasing its cost includes a differential input stage circuit in which gate lengths of load transistors and gate lengths of differential input transistors are set to an optimal ratio to minimize internal transistor noise components.

Abstract: A method and device for maintaining junction isolation between a second region that is normally clamped at a reference potential, contained within a first region of an opposite type of conductivity whose potential is subject to large inertial swings. The junction is ensured even when the potential of the first region moves toward and beyond the reference potential to which the second region is clamped, by connecting the second region to the reference potential by a switch, and causing the switch to open which places the second region in a floating state, leaving it free to track the potential excursion of the first region. The switch is closed after the potential of the first region has returned to a normal value. A comparator senses a shift of the potential of the second region from the reference potential to which it is clamped. The shift is dynamically induced by the capacitive coupling of the two regions, and triggers off the clamping switch.

Abstract: A circuit for interfacing between the output voltage terminals of a focal plane array (FPA) detector and subsequent digital processing circuitry and employing a differential circuit including respective resistors to create first and second input currents and a control circuit to adjust the first and second input currents to eliminate the common mode current component. The control circuit includes a current source and a current mirror amplifier on each side of the differential circuit with each current mirror amplifier supplying a current sample signal to a current sense amplifier which, in turn, supplies a control signal to each of the current sources. The interface circuit accommodates input voltages of different polarities and magnitudes, while operating from reduced supply voltage levels and providing output currents limited within a defined range.

Abstract: In an interface for an input signal with a small amplitude and a high bit rate, the output voltage of a receiver can become more indeterminate when the input signal voltage at the receiving end of a signal transmission line becomes equal to a reference voltage V.sub.ref. In the input buffer circuit of the CMOS current mirror type, a transistor Q.sub.2 is connected in parallel with another transistor Q.sub.1, where the conductivity types of both the transistors are the same and a reference voltage V.sub.ref is applied to the gate electrode of the transistor Q.sub.1. The transistor Q.sub.2 endows the input buffer circuit with a hysteresis characteristic, and the output power N1 of the input buffer circuit is supplied to the gate electrode of the transistor Q.sub.2.

Abstract: A recording apparatus including a magnetic write head and a write amplifier with capacitive current compensation. The write amplifier is made up of four current mirrors which are turned on two at a time by two switchable floating current sources connected between the input terminals of the current mirrors in order to produce a write current of alternating polarity through the write head. The parasitic capacitances across the write head and/or the parasitic capacitances of the write amplifier at the write terminals are neutralized by means of neutralizing capacitors. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit.

Abstract: The present invention provides a sense amplifier with high speed and stable sensing capabilities under a low supplying voltage. In accordance with the present invention, there is disclosed a sense amplifier comprising: a voltage level shifter for shifting a voltage level of data from a memory cell in response to a sense amplifier enable signal; a current mirror type sense amplifying stage for amplifying the level-shifted data from the voltage level shifter to full range in response to the sense amplifier enable signal; and a driver means for driving the amplified data from the current mirror type sense amplifying stage.

Abstract: Improved small current detector circuit and locator device each comprise a first and a second element in both of which a small current output occurs, a first and a second constant current generator circuit each generating a specified constant current, a first current mirror circuit which is supplied at the input with said output current occurring in said first element and said specified constant current generated from said first constant current generator circuit, and a second current mirror circuit which is supplied at the input with said output current occurring in said second element and said specified constant current generated from said second constant current generator circuit, and wherein either one of said first and second elements is disposed in a detecting portion and a current equal to the current from the output of either one of said first and second current mirror circuits is flowed to the output of the other current mirror circuit such that a detection output corresponding to the difference betw

Abstract: There is disclosed a differential amplifier circuit wherein resistors (89, 91) and capacitors (90, 92) are connected respectively between sources of a differential pair of NMOS transistors (85, 87) and a power supply (2). The resistors (89, 91) raise the source potential of the NMOS transistors to reduce current flows during the time no transition of signal level outputted from the differential amplifier circuit occurs, reducing power consumption in the differential amplifier circuit. The capacitor (90, 92) alleviate the effects of voltage drop by the resistors (89, 91) during the signal level transition to prevent reduction in operating speed of the differential amplifier circuit.

Abstract: Reference circuitry RC includes a current-sensing translator M5-M7, MX connected to a current reference source RS. The outputs O1, O2, etc. of the current-sensing translator M5-M7, MX are mirrored into one or more sense amplifiers SA1,SA2 of sensing circuitry SC. The current-sensing translator M5-M7, MX permits the current from the current reference source RS to be mirrored to multiple sense amplifiers SA1,SA2 at a predetermined ratio.

Abstract: The comparator circuit comprises a first comparator circuit having a differential input stage composed of P-channel FETs; a second comparator circuit having a differential input stage composed of N-channel FETs; pull-up and pull-down resistances connected to the output terminals of the two comparator circuits, respectively; at least one skew adjusting circuit having a delay circuit and a selector; and a logical gate for obtaining the two output signals of the two comparator circuits. Since the two differential input signals can be received by the two comparator circuits and according to the potentials of the two differential input signals, even if the supply potential is low, the comparator circuit can compare the two differential input signals in a wide potential range from the ground potential and the supply potential, so that it is possible to provide a high speed interface circuit which can satisfy the LVDS standard at a low supply potential.

Abstract: An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit.

Abstract: A multiple match detection circuit including an array of N and P-channel pull-up and pull-down devices receiving a corresponding array of hit line signals for developing complementary bit line signals, which are provided to the respective inputs of a differential comparator. Respective buffers drive the bit line signals to a maximum voltage differential in normal mode. For each hit line asserted, the pull-up and pull-down devices modify the voltage of the corresponding bit line voltage between the bit lines by an incremental amount, thereby decreasing the differential. Any single hit line does not cause enough of a voltage change to reverse the polarity of the differential voltage between the bit lines.

Abstract: At the input sides of matched first and second differential amplifiers 11 and 12, first and second input buffers 21 and 22, and third and fourth input buffers 23 and 24 are respectively connected. In input transistors Q5 and Q8 in the first and second input buffers 21 and 22, emitter currents corresponding to the collector currents of differential transistors Q3 and Q4 of the second differential amplifier 12 flow by using current mirror circuits. Changes of base-emitter voltage of the PNP transistors Q5 and Q8, and changes of base-emitter voltage of NPN transistors Q1 and Q2 cancel each other, and an output voltage improved in linearity is obtained between a negative phase output terminal 33 and a positive phase output terminal 34.

Abstract: An apparatus for recording on a magnetic record carrier includes a write amplifier comprising four current mirrors which are turned on two at a time by two switchable floating current sources connected between the input terminals of the current mirrors in order to produce a write current of alternating polarity through a write head. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit. The symmetrical structure further enables the parasitic capacitances at the write terminals to be neutralized by means of neutralizing capacitors.

Abstract: A circuit and method for stabilizing a common mode voltage in a differential circuit provides a desired common mode voltage V.sub.cm to control terminals of two transistors which provide the variable resistance for setting the common mode voltage. V.sub.cm is sampled between load resistors R.sub.L connecting operating terminals of the two transistors and applied directly to their control terminals. A known common mode current I.sub.cm is accepted by each transistor, leaving a differential current I.sub.d to flow through load resistors R.sub.L. The circuit and method find application in a variety of uses, including transconductance and transresistance amplifiers and automatic gain control circuits.

Abstract: An improved current sensing differential amplifier which includes a separate p-channel bias stage to reduce the minimum operating voltage VCC of the circuit. The separate p-channel bias stage is also used to pre-bias a driver stage to more quickly generate differential output currents. Finally, the improved current sensing differential amplifier also includes negative feedback transistors to improve the recovery time of the circuit.

Abstract: A logic circuit for implementing a flip-flop circuit that operates stably and at high speed at a low supply voltage of about 1 V. The logic circuit includes transistors 25,26,31 for forming a first current mirror circuit 2; transistors 27,28 for converting clock signals to current signals; transistors 19,22,23 for forming a second current mirror circuit 3; and transistors 20,21,24 forming a third current mirror circuit 4. These current mirror circuits supply a current nearly equal to the current from transistors 27,28 to the circuits connected respectively to those current mirror circuits. Transistors 29,30, current source 47, voltage source 50 and voltage comparison circuit 51 form a voltage maintenance circuit. Transistors 11,12 and resistors 41,42 form an input stage of a master D flip-flop D-FF, and transistors 13,14 form the signal-holding row of the master D flip-flop D-FF.

Abstract: A high side current sense amplifier (21) comprises a first resistor, a second resistor, an amplifier (22), and a darlington transistor pair. The first resistor has a first input and a second input coupled to a non-inverting input of the amplifier (22). The darlington transistor pair has a collector coupled to the non-inverting input of the amplifier (22), a base coupled to an output of amplifier (22), an emitter. The second resistor is coupled between the emitter of the darlington transistor pair and ground. A differential voltage is applied across the first input of the first resistor and an inverting input of the amplifier (22). The darlington transistor pair converts an output voltage of the amplifier (22) to a feedback current for generating a voltage across the first resistor. Under stable conditions the voltage across the first resistor is equal to the differential voltage. The voltage gain is the ratio of the second resistor to the first resistor.

Abstract: A current mirroring circuit including first and second field effect transistor devices connected in a current mirroring arrangement, a circuit for summing a first plurality of identical currents to provide current for the first field effect transistor device, a circuit for dividing the current from the second field effect transistor device into a second plurality of identical currents, and an output circuit connected to mirror any one of the second plurality of identical currents.

Abstract: A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver inverter having an input and an output. The inverter inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.

Abstract: In reading circuits for memories in integrated circuit form, notably non-volatile memories, to obtain a better compromise between reading speed and the reliability of the information read, there is proposed a reading circuit. A differential amplifier for reading a memory cell is connected to a precharged bit line and reference line. A follower amplifier balances the input potentials of the differential amplifier before the reading phase. The follower amplifier has one input connected to the output of the differential amplifier and is connected during the balancing phase in such a way that it injects a load current to the- bit line in a direction tending to cancel the output voltage of the differential amplifier. A cascode transistor can be used to accelerate the reading.

Abstract: An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit.

Abstract: A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines to a single ended output signal indicative of the state of the data stored in a selected memory cell connected to the complementary bit lines. The circuit is constructed to operate with low voltage swings, thereby increasing the switching speed and thus the sense speed. The sense amplifier includes power down capabilities and the ability to tristate its output terminal while in a standby mode of operation during which it is capable of reading the logic level of an input signal. In one embodiment, the output signal is latched using a simple register when the output stage goes tristated, to continue to provide a valid output signal while a subsequent sense operation is performed.

Abstract: An integrated circuit is disclosed that includes a sense amplifier having first and second transistors, each of which have a conduction path and a gate electrode. The conduction path of the first and second transistors are electrically coupled in series between a power supply node and an input. The integrated circuit also includes third and fourth transistors each having a conduction path and a gate electrode. The conduction path of the third and fourth transistors are electrically coupled in series between the power supply node and a first reference potential. The gate electrodes of the first and third transistors are electrically coupled to an output node. A fifth transistor has a conduction path electrically coupled between a second reference potential and the output node. The gate electrode is maintained at a voltage that is about two threshold voltage drops below the voltage level of the power supply node.

Abstract: In the present invention, there are disposed (i) a P-channel MOSFET for detecting variations of the voltage level of a data line to supply an electric current, and (ii) a current mirror circuit to which an electric current from the P-channel MOSFET is entered as a reference current and of which output current terminal is connected to the data line. When the data line is lowered in voltage level so that an electric current flows from the P-channel MOSFET to the current mirror circuit, an output current of the current mirror circuit flows to the drain of an N-channel MOSFET, so that the data line is electrically discharged. Thus, there is achieved a sensing circuit unit which is suitably used for a dynamic circuit and which can detect, at a high speed, variations of the voltage level of the data line as precharged.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: An interchip high speed I/O circuit having a low voltage swing and on-chip transmission line terminations. The present invention provides a high speed I/O circuit that uses a small voltage swing to keep power dissipation in the overall system to a minimum and particularly in the transmission line termination loads. A differential receiver circuit compares a data signal input to a reference signal, both sent from a driver chip, to determine the appropriate output response. Both the data signal and the reference signal are current controlled which reduces the di/dt noise generated by parasitic inductances.

Abstract: An electronic circuit comprising a comparator which is operated by a first power source voltage and having first and second input terminals, where the first input terminal is supplied with a reference voltage which is dependent on the first power source voltage, a detecting circuit for detecting a deviation of a second power source voltage and for outputting a control signal dependent on the deviation, where the first and second power source voltages undergo mutually independent deviations, and a voltage converting circuit supplied with an input signal for converting a voltage of the input signal depending on the control signal received from the detecting circuit. The voltage converting circuit supplies the input signal to the second input terminal of the comparator which outputs an error signal indicative of an error between the input signal voltage and the reference voltage.

Abstract: In reading circuits for memories in integrated circuit form, notably non-volatile memories, to obtain a better compromise between reading speed and the reliability of the information read, there is proposed a reading circuit constituted as follows: a differential amplifier, means for the precharging of the bit line before a reading phase and means for the balancing of the input potentials of the differential amplifier before the reading phase. The balancing means comprise a follower amplifier that has one input connected to the output of the differential amplifier and is connected during the balancing phase in such a way that it injects a load current of the bit line in a direction tending to cancel the output voltage to the differential amplifier. A cascode transistor can be used to accelerate the reading.

Abstract: The coupled switching transistors of the digital current switch are connected to a controlled current source. Load resistors of the current switch are formed as controlled resistors. The L-level produced by a reference current branch is compared with a predetermined level by means of a regulating device which includes the reference current branch and a compensator, and the controlled resistor or the controlled current source are adjusted such that the L-level is equal to the predetermined level.

Abstract: An off-line controller circuit having a line voltage detector and a switched current bootstrap circuit. The controller receives current from the line and provides a drive signal for controlling the switch(es) of an off-line converter. The line voltage detector establishes a voltage proportional to the line voltage in response to a portion of the received line current. The proportional voltage is compared to a reference voltage to provide a control signal for inhibiting the drive signal when the proportional voltage is less than the reference voltage, indicating that the line voltage is less than a predetermined level. The switched current bootstrap circuit limits a bootstrap current provided to the controller supply voltage from the converter output in accordance with current shunted to ground by a supply voltage clamp.

Abstract: Sense amplifier circuitry (SC) includes a differential amplifier (A) having a reference input and a memory input. The output of a first sense amplifier (SA1) is coupled to the reference input of the differential amplifier (A) and to the input of a second sense amplifier (SA2). The output of the second sense amplifier (SA2) is coupled to the memory input of the differential amplifier (A) and to the input of the first sense amplifier (SA1). The first sense amplifier (SAR) and the second sense amplifier (SA2) include identical mirror transistor circuits (M1, M2, M3, M4).

Abstract: A semiconductor memory device includes a plurality of sense amplifiers for amplifying current changes which occur in corresponding bit line pairs in accordance with binary signals stored in activated memory cells. Each of the sense amplifiers includes first and second current mirror circuits for generating currents of the magnitudes respectively corresponding to currents flowing through a corresponding bit line pair, a storing circuit, responsive to a signal selecting a memory cell, for storing the currents generated by the first and second current mirror circuits before activation of the memory cell, or a difference between these currents, and a current supplying circuit, responsive to activation of the memory cell and based on the amount stored in the storing circuit, for supplying, to the first and second current mirror circuits, currents having a predetermined relationship with the currents having been generated by the first and second current mirror circuits before activation of the memory cell.

Abstract: A sense amplifier for detecting the difference in voltage between two bitlines of a memory circuit. The sense amplifier is comprised of a differential amplifier which is coupled to the two bitlines and generates an output signal based on voltage levels sensed in the bitlines. The differential amplifier is coupled to V.sub.CC and ground through an active load and a current source respectively. To address the problem of increased common mode voltage levels found in the bitlines, a pair of transistors are connected in parallel across the active load to V.sub.CC and the differential amplifier. The gate of one of the transistors is coupled to one of the bitlines and the gate of the other one of the transistors is coupled to the other one of the bitlines. With these two transistors coupled in parallel across the load as described, the differential amplifier has increased immunity to elevated common mode levels found in the bitlines.

Abstract: A data input/output line sensing circuit includes a latch sense circuit having the double functions of performing a latch operation and a sensing operation for data read from a memory cell. The latch sense circuit includes a first inverter having an input end connected to one of the data input/output lines, and an output end connected to the other of the data input/output lines; a first switching transistor provides the first inverter with a power supply voltage and a ground voltage only during a sensing operation in response to a sensing control signal; a second inverter having an input end connected to the output of the first inverter, and an output end connected to the input of the first inverter; and a second switching transistor provides the second inverter with the power supply voltage and the ground voltage only during the sensing operation in response to the sensing control signal.

Abstract: A tristateable sense amplifier, for driving a bus directly with minimal size devices, includes a control transistor coupled to a reference voltage terminal and having a control electrode receiving a first control signal. A first series circuit includes a first transistor of a first channel type and a second transistor of opposite channel type coupled between the control transistor and a supply voltage terminal. A control electrode of the second transistor receives a first input signal and the second transistor generates a first output signal. A second series circuit includes a third transistor of the first channel type and a found transistor of the opposite channel type coupled between the control transistor and the supply terminal. A second input signal is coupled to the control electrode of the fourth transistor.

Abstract: A nonvolatile memory device includes a matrix array of transistors. A read potential generation circuit provides a potential to a selected transistor and generates a read potential in accordance with the flow of current which indicates the data storage state of the transistor. A reference potential generation circuit provides a potential to a selected dummy transistor and generates a reference potential based on the current which flows through the dummy transistor. The memory device incorporates one or more strategies to prevent the relative magnitudes of the read potential and reference potential from being erroneously inverted immediately after the nonvolatile memory is switched from standby to an operational mode. A reference potential decreasing circuit incorporated within the reference potential generation circuit is activated for a predetermined time period after chip enable.