Abstract: A Pseudo Bipolar Junction Transistor(Pseudo-BJT) based retinal focal-plane sensing system is an instant image sensing and front-end processing system with the advantages of high dynamic range and instant image processing. In addition, the system proposes a Pseudo-BJT based retinal focal-plane sensor with adaptive current Schmitt trigger and smoothing network for applying a new Pseudo-BJT circuit structure to mimic parts of functions of the cells in the outer plexiform layer of the real retina. It is suitable to resolve the existing technical drawbacks performing major functions in optical image detecting circuits, such as image recognition, image tracing, robot vision, bar-code/character readers, etc.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: The circuit arrangement for measuring current flowing through a high-resistance consumer (R1) contains a current mirror circuit (1), in the first branch (T1) of which the high-resistance consumer is connected in series and in the second branch of which an evaluation circuit (3, 4, 5) is connected. The high-resistance consumer is, in particular, a lambda probe (R1) of the catalytic converter of an internal combustion engine, whose resistance value is on the order of several M? and which is operated at high operating temperatures of around 400° C. Accordingly, very small currents on the order of several nA to several ?A must be measured. Thanks to the current mirror circuit, a current (ID2) is generated in the second branch that is equal in magnitude to the current (ID1) flowing through the first branch and the consumer (R1). Thus, the current flowing through the second branch does not load the first branch. All components can be integrated in an integrated circuit, such as an ASIC.

Abstract: An amplification apparatus is provided that includes a plurality of gain stages including a first gain stage having first and second transistors and a second gain stage having third and fourth transistors. A plurality of replica stages may also be provided that includes a first replica stage and a second replica stage. Each replica stage may correspond/match one of the plurality of gain stages. An amplifying device may be provided to adjust a body potential of at least the first transistor of the first gain based on an output of the first replica stage and an output of the second replica stage.

Abstract: A differential amplifier is configured to receive an input signal whose magnitude is referenced between a reference voltage and a first power supply magnitude. A differential current conducted by the differential amplifier induces current to be conducted by a first current mirror, which in turn induces current to be conducted by a second current mirror. The current conducted by the second current mirror produces an output signal that is referenced between the reference voltage and a second power supply magnitude.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input terminal and the first output terminal are directly connected. Additionally, the system includes a switch coupled to the first output terminal and a first node. The switch is controlled by at least a first control signal. Moreover, the system includes a comparator including a third input terminal, a fourth input terminal, and at least a second output terminal. The comparator is configured to receive a first input signal at the third input terminal and a second input signal at the fourth input terminal. The first input signal and the second input signal are associated with the first node and the predetermined voltage.

Abstract: A clock enable buffer for entry of a self-refresh mode. The clock enable buffer includes a current mirror load connected between a voltage source and first and second nodes, wherein the current mirror load has first and second transistors; a third transistor connected between the first node and a third node, wherein the third transistor is turned on according to a reference voltage; a fourth transistor connected between the second node and the third node, for controlling the current mirror load in response to a clock enable signal; a fifth transistor connected between the third node and a ground, wherein the fifth transistor is turned on according to a self-refresh signal; and a sixth transistor that is turned on according to an inverted self-refresh signal to make the potential of the first node a Low level.

Abstract: The present invention provides a current mirror circuit of which consistency (ratio) of the input current and output current is more improved. This current mirror circuit comprises input side and output side bi-polar transistors of which bases are commonly connected, an input side MOS transistor of which source is connected to a collector of the input side bi-polar transistor and of which drain and gate are connected to the input terminal, output side MOS transistors of which source is connected to the collectors of the output side bi-polar transistors, of which drain is connected to the output terminals, and of which gate is connected to the gate of the input side MOS transistor, and an MOS transistor for supplying base current of which source is connected to the bases of the input side and output side bi-polar transistors, and of which gate is connected to the gate of the input side MOS transistor.

Abstract: To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop's voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.

Abstract: An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node.

Abstract: A light emitting element driving circuit for supplying driving current I2 to a light emitting element 10 connected to one line 2 of a current mirror circuit 12 is equipped with a pulse generating circuit 20 connected to the other line 1 so that pulse current flows therethrough, and superposing means 30 for superposing a first auxiliary pulse current on the pulse current in synchronization with the rise-up time of the pulse current. The rise-up time is shortened by the superposition. In the driving circuit, a source follower circuit is connected to the current mirror circuit, and current flowing through the source follower circuit is set to be substantially proportional to current flowing through the other line of the current mirror circuit.

Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.

Abstract: An output stage circuit for a current mode device provides open loop reduction or cancellation of DC offset in differential output signals. Differential input signals are received and sourcing current mirrors provide mirrors of the differential input signals to output nodes. Sinking current mirrors also provide mirrors of opposite polarity of the differential input signals to the output nodes corresponding to the opposing sourcing current mirrors. The summing of the mirror currents at the output nodes substantially reduces or eliminates the DC offset components present in the input signals.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors.

Abstract: A semiconductor integrated circuit device is comprised of an amplifier circuit having first and second PMOS and NMOS transistors. The first PMOS transistor has a gate electrode and a drain electrode connected together. The second PMOS transistor has a gate electrode connected to the gate electrode of the first PMOS transistor and a course electrode connected to a course electrode of the first PMOS transistor. The first NMOS transistor has a drain electrode connected to the drain electrode of the first PMOS transistor and a gate electrode sat as a first input terminal. The second NMOS transistor has a drain electrode connected to a drain electrode of the second PMOS transistor, a source electrode connected to a sourse electrode of the first NMOS transistor, and a gate electrode sat as a second input terminal. At least one of the first NMOS transistor and the second NMOS transistor is comprised of a buried channel transistor.

Abstract: A comparator with an offset canceling function and a D/A conversion apparatus capable of canceling an input/output offset with high accuracy using this comparator. To eliminate unbalance between right and left currents of the differential circuit making up the comparator, the phase of a single end output signal of the differential circuit is inverted and the inverted signal is fed back to one substrate of the differential pair MOS transistors as a substrate bias. Threshold voltages of the MOS transistors are changed and the current capacities of the transistors are adjusted in this way.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: A system is provided for use with an on-chip fuse. If the fuse (40) is to be blown, the system blows the fuse, then performs a test read by comparing it with a larger-than-normal reference resistance (41, 42). If, even using the larger-than-normal reference resistance, the fuse reads as blown, then it is possible to be much more confident that the fuse will read correctly when compared against the normal reference resistance (42), even with aging and with variations of temperature and supply. For future reads during normal operation, the system compares it with the normal reference resistance (42). If, on the other hand, the fuse does not read as blown during the test read then the device can be rejected as a failed device.

Abstract: An input stage circuit for an LVDS circuit. The input stage has a folded cascode that receives input signals. The folded cascode has a first input circuit and a second input circuit. The first input circuit receives a first input signal from a connected circuit and the second input circuit receives a second signal from the connected circuit. A first current mirror receives signals from the first input circuit of said folded cascode. A second current mirror receives signals from the second input circuit. The first current mirror and the second current mirror are connected to a common output to merge signals from the first and second input circuits. A diode adjusts a voltage level of the signals to an output voltage.

Abstract: An apparatus for comparing an input voltage with a threshold voltage includes: (a) a first current mirror device that includes a first bipolar transistor with a first base and a first collector; the first base and the first collector establish a diode-connected first collector; the input voltage is received at the first current mirror device; (b) a second current mirror device that includes a second bipolar transistor with a second base and a second collector; the second base and the second collector establish a diode-connected second collector; (c) a first impedance coupled in series with the diode-connected first collector and the diode-connected second collector; and (d) a second impedance coupled between ground and the second current mirror device. The first and second current mirror devices are coupled with an output locus at which output signals appear to indicate relative voltage levels of the input and the threshold voltages.

Abstract: A circuit includes a first pre-amp circuit that provides a first pre-amp current and a second pre-amp circuit that provides a second pre-amp current. A first threshold circuit is configured to generate a first output signal responsive to a difference between a variable current and the first pre-amp current. A second threshold circuit is configured to generate a second output signal responsive to a difference between the variable current and the second pre-amp current. One of the branches of a differential interpolation circuit includes a first transistor that is connected in a current mirror configuration with the first pre-amp circuit. The first transistor has a width/length ratio equal to the product nk, where n<1. A second transistor is connected in a current mirror configuration with the second pre-amp circuit. The second transistor has a width/length ratio equal to the product mk, where m<1 and n+m is about 1.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: A sense amplifier structure for multi-level non-volatile memories reads the contents of the memory cells. In particular, a current drawn by a memory cell to be read is compared to a current drawn by a reference cell through a sense amplifier that has one input terminal connected to a circuit node to which said currents are led. Advantageously, the currents are compared at both inputs of the sense amplifier by connecting a second input of said amplifier to a circuit node to which said currents are led, with opposite signs. The method enhances the read precision of the sense amplifier for a given data acquisition time by doubling the differential input voltage.

Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.

Abstract: A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.

Abstract: A method and system is arranged to convert a differential low-voltage input signal (e.g. LVDS or RSDS) into a single-ended output signal. An operational trans-conductance amplifier (OTA) is configured to convert the input signal into a current. A trans-impedance stage is configured to convert the current into the single-ended output signal. The voltage associated with the output of the OTA corresponds to approximately VDD/2. The trans-impedance stage comprises an inverter circuit, a p-type transistor, and an n-type transistor. The transistors are arranged in a negative feedback configuration with the inverter. The single-ended output signal has a voltage swing that approximately corresponds to the sum of the VGS of the n-type transistor and the VGS of the p-type transistor. The output signal may be buffered by additional circuits such as an inverter, a Schmitt, as well as others.

Abstract: A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.

Abstract: A high-speed sense current amplifier with a low power consumption for a memory cell, the sense current amplifier having: a first current mirror circuit, which amplifies a memory signal current received from the memory cell via a memory signal line and outputs it at a signal output of the sense current amplifier; a second current mirror circuit, which generates a setting current in a manner dependent on the received memory signal current; and an adjustable reference current source, which outputs a reference current to the signal output of the sense current amplifier, the magnitude of the output reference current being set, via a setting line, in a manner dependent on the setting current generated by the second current mirror circuit.

Abstract: A current sense amplifier circuit for detecting a first current includes an input gain stage incorporating a feedback loop, a current mirror, a charge integration stage and a comparator. The first current is coupled to an input node of the input gain stage where the input gain stage operates to maintain the voltage at the input node at a substantially constant level. The current mirror is coupled to mirror the first current into a second current. The charge integration stage is coupled to integrate charge associated with the second current to develop a first voltage. The comparator is coupled to compare the first voltage to a reference level and providing an output signal. The comparator generates an output signal having a first value when the first current exceeds a predetermined threshold level and a second value when the first current is less than the predetermined threshold level.

Abstract: The present invention discloses a current sensing circuit and method of a high-speed driving stage, which comprises an input stage, a level converting unit, a feedback unit, a current mirror unit and a current shunting unit. The current sensing circuit is capable of linearly detecting the output current of the driving stage transistors, and directly condensing the detected current to an appropriate value using the geometric ratio of the transistors, so as to facilitate the subsequent signal processing circuit to use it for control purposes.

Abstract: Presence or absence of a differential clock is detected. The voltage of each differential clock line is compared to the common-mode voltage and integrated over time by a capacitor. The capacitor is discharged during the portions of the clock cycle that the differential line is over the common-mode voltage. If the clock stops pulsing the capacitor is charged by a current source to activate a clock-loss signal. The clock-loss detector is ideal for high-frequency operation since each differential clock line is applied to only one transistor gate. The common-mode voltage generates a bias voltage for a differential amplifier that receives the true and complement differential clock lines. Diodes prevent capacitor charging by reverse current flow from the differential amplifier when the clock is inactive. The averaged peak voltage or envelope of the differential input signals is detected.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract: An optimized read data amplifier for the output data path of integrated circuit memory arrays comprises a fast, low power and small on-chip area consuming circuit which is advantageously effectuated through the combined application of “current sensing” and “voltage sensing” techniques. In a particular embodiment disclosed herein, an amplifier enable signal is timed with the column read address so that the amplifier is turned “off” when not in use and both data read lines (“DR” and “DRB”) are precharged “high”. No clocking of the read data amplifier is required in order to obviate undesired clock latencies and pipelining and a simple mechanism is implemented such that control of power-up and power-down results in further power savings.

Abstract: An indirect current sensing circuit and method for replicating an output current is disclosed. The present invention is capable of preventing device damage and circuit disruption by maintaining output voltage signal integrity and consuming negligible power as well as optimizing output impedance. Furthermore, the indirect current sensing circuit and method is independent of semiconductor process variations and thus is more reliable over prior art current sensing techniques. The indirect current sensing circuit and its method of current limiting and output impedance optimization, according to the present invention, can reliably drive transmission lines in networking system and communication applications.

Abstract: A current sense amplifier (10) for measuring current flowing through a sense resistor (12) coupled between first (11) and second (13) terminals, respectively, of the current sense amplifier, the current sense amplifier includes a first amplifier (18) having a first input (17) coupled by a first resistor (16) to the first terminal (11) and a second input (20) coupled by a second resistor (19) to the second terminal (13) and a bias circuit (30,24) coupled to the first input (17) of the first amplifier for causing the bias current to flow through the first resistor (16. A feedback transistor (26) is coupled to the output (22) of the first amplifier and the second input (20) of the first amplifier to cause a feedback current to equalize the voltages on the first (17) and second (20) inputs of the first amplifier and supply the feedback current to an output terminal (36) of the current sense amplifier (10).

Abstract: A single-ended sense amplifier having a precharge circuit for maintaining a stable voltage on a bitline, a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline, a direct current amplification circuit electrically coupled to the sensing circuit for amplifying the current sensed on the bitline, a current-to-voltage conversion circuit for converting the sensed current to a voltage and a voltage amplification circuit for amplifying the voltage at the sense amp output. The sense amplifier can be implemented using standard CMOS components and provides improved access time at low power supply voltage, high robustness to process variations, and the ability to sense very low currents.

Abstract: The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.

Abstract: A load independent single ended sense amplifier is provided. The sense amplifier includes a first current mirror having a first load transistor and a first reflected current transistor, and a second current mirror having a second load transistor and a second reflected current transistor. The first load transistor is capable of communicating a load current to the second load transistor. In addition, a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current.

Abstract: A comparator circuit for comparing two electric voltages, the comparator circuit comprising a differential amplifier with a current mirror as a load, characterized in that two current branches comprise two differential transistor amplifiers (2, 3) with two current mirrors (4, 5) as a load, in which the bases of the differential amplifiers (2, 3) represent the comparator input, and in that both current mirrors (4, 5) are each constituted by a diode (6, 9) and an associated transistor (7, 8), in which the comparator output value is either one of the currents through the diodes (6, 9) or one of the voltages across the diodes (6, 9) or the difference between the two diode voltages (6, 9).

Abstract: In an embodiment consistent with the present invention, a semiconductor device having a oscillating circuit comprises: a first transistor having a control electrode and having one end and the other end of a current path thereof; a second transistor having a control electrode and having one end and the other end of a current path thereof, the control electrode is coupled to one end of the current path of the first transistor and one end of the current path thereof is coupled to the control electrode of the first transistor; a current mirror circuit that supplies a current to one end of the current path of the first transistor and one end of the current path of the second transistor; an inductor coupled to one end of the current path of the first transistor and one end of the current path of the second transistor; a first capacitor coupled to one end of the current path of the first transistor and one end of the current path of the second transistor; and a second capacitor and a switch element coupled with, are

Abstract: A system and method for current sensing which is substantially consistent over device, temperature, and process variations is provided. A current sensing system includes a first switch coupled to one or more variable resistive elements. The resistive elements being configured to scale down the voltage across the first switch which is provided to an input of an amplifier. The amplifier is coupled to the resistive elements and the second switch and is configured to sense the voltage across the first switch, and force the voltage across the second switch to be equal to the first switch scaled down voltage. Thus, a current of known proportion can be provided at the output of the amplifier. A driver and timing circuit may be provided to prevent the amplifier from providing an excessive slewing of current during the off period.

Abstract: The present invention provides a method and apparatus for current steering for an LVDS input buffer. A current steering circuit is configured to steer current to a first node and/or a second node in response to a comparison between the input common-mode signal and a reference signal. During high input common-mode, more current is steered to the P-channel differential pair node of the input buffer as compared to the N-channel differential pair node. During low input common-mode, more current is steered to the N-channel differential pair node of the input buffer as compared to the P-channel differential pair node. The current steering reduces jitter and achieves stable output of the input buffer over process, voltage and temperature. The method and apparatus provided ensures a stabilized summation of the currents ID1+ID3 and ID2+ID4 by steering current into the P-channel node or N-channel node.

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract: Reference level generating circuit in a memory device includes a first amplifier and a second amplifier each for comparing and amplifying a reference bitline level and a fedback preliminary reference level. A reference level adjuster receives signals from the first and second amplifiers, adjusts the signals to desired reference levels, and feeds the signals back to the first and second amplifiers. A reference level stabilizer stabilizes a reference level from the reference level adjuster, and a pull-down circuit drops an output from the reference level stabilizer by a required level in bitline precharging. An operational controller controls operation of the first and second amplifiers, the reference level adjuster, the reference level stabilizer, and the pull-down circuit. The reference level generating circuit and devices using such circuit improves data sensing rate and device reliability.

Abstract: A current sense amplifier including a transconductance amplifier to measure a current passing through a sense resistor and generate a reference current indicative of the measured current. A current mirror circuit is connected to the transconductance amplifier and receives the reference current for amplification to generate an amplified output current. A cascode circuit is connected serially to the current mirror circuit to boost an output impedance for the amplifier at the output of the generated amplified output current. The current mirror circuit and cascode circuit of the current sense amplifier are each formed from a pair of transistors sharing a common control node, with the transistors realized using with bipolar or MOS technology.

Abstract: A current mirror circuit is described which includes a current input terminal (14A), a current output terminal (14B) and a common terminal (14C). A first controllable semiconductor element (T1) is arranged between the current input terminal (14A) and the common terminal (14C). A second controllable semiconductor element (T2) is arranged between the current output terminal (14B) and the common terminal (14C). The controllable semiconductor elements (T1, T2) havie interconnected control electrodes (T1A, T2A) which are also coupled to a bias voltage source (VBIAS), for biasing said control electrodes at a reference voltage. The circuit further includes a transconductance stage (12) with an input (12A) coupled to the current input terminal (14A) and an output (12B) coupled to the common terminal (14C). The control electrodes (T1A, T2A) are coupled to the common terminal (14C) via a third controllable semiconductor element (T3).