Abstract: The present disclosure discloses a zero-crossing detection circuit, including: a zero-crossing judgment module, having a first end and a second end, wherein the first end is connected to a power supply and the second end is grounded; a photoelectric coupler, connected to the zero-crossing judgment module; an optocoupler driving module, connected to the photoelectric coupler; and an energy storage capacitor, wherein the energy storage capacitor is configured to provide excitation power for the photoelectric coupler and the optocoupler driving module.

Abstract: The present disclosure discloses a zero-crossing detection circuit, including: a zero-crossing judgment circuit, configured to detect a zero-crossing signal; and an energy storage capacitor, connected to the zero-crossing judgment circuit in parallel, wherein the energy storage capacitor is configured to provide excitation current for the zero-crossing judgment circuit.

Abstract: A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof.

Abstract: A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof.

Abstract: A detection apparatus has an alternating-current voltage input unit and a generation circuit. The generation circuit generates a superimposition signal in which information indicating a timing of a zero cross in an alternating-current voltage inputted into the input unit and information indicating a voltage level of the alternating-current voltage are superimposed.

Abstract: An electrical circuit with large creepage isolation distances is provided. In some embodiments, the electrical circuit is capable of increasing creepage isolation distances by many multiples over traditional electrical circuits. In one embodiment, an electrical circuit comprises a ground circuit optically coupled to a floating circuit, and an isolated circuit optically coupled to the floating circuit. The circuits can be optically coupled with opto-isolators, for example. The isolated circuit can have a creepage isolation distance at least twice as large as a traditional circuit. In some embodiments, “n” number of floating circuits can be optically coupled between the ground circuit and the isolated circuit to increase the total creepage isolation distance by a factor of “n”. Methods of use are also described.

Abstract: In one embodiment, a zero-crossing detection circuit for a synchronous step-down converter, can include: (i) a state determination circuit configured to compare a drain voltage of a synchronous transistor of the synchronous step-down converter against a reference voltage, and to generate a state digital signal indicative of whether a body diode of the synchronous transistor is turned on; (ii) a logic circuit configured to convert the state digital signal into a counting instruction signal; (iii) a plus-minus counter configured to generate a numerical signal in response to the counting instruction signal; (iv) a DAC configured to generate a correction analog signal based on the numerical signal; and (v) a zero-crossing comparator configured to receive the correction analog signal and the drain voltage of the synchronous transistor, and to provide a zero-crossing comparison signal to a driving circuit of the synchronous step-down converter.

Abstract: A head lamp system may include a head lamp that may be provided with a headlight and a spotlight unit including a plurality of optical modules having different irradiation regions in front of a vehicle, wherein an optical module of the plurality of optical modules, which has a irradiation region that corresponds to a position of an obstacle in front of the vehicle, blinks, and a blink period of the optical module may be changed according to a vehicle speed.

Abstract: A system for detecting a Zero Crossing point is provided. The system includes: a coupling unit connected between a high voltage side and a low voltage side of the system; and a zero crossing detector connected to the high voltage side and configured to divide a filtered mains voltage signal and to generate an output signal that indicates a zero crossing point of the filtered mains voltage signal.

Abstract: A zero-crossing detection circuit includes a comparator and circuitry. The comparator produces an output signal that is indicative of zero-crossing events in an input Alternating Current (AC) waveform. The circuitry may be configured to feed the comparator with first and second rails voltages, and to progressively increase the rails voltages during time intervals derived from the input AC waveform, so as to feed the comparator with target values of the rails voltages in time-proximity to the zero-crossing events. The circuitry may be configured to compensate for an error in detecting the zero crossing events caused by differences in amplitude of the input AC waveform, by correcting the input AC waveform provided to the comparator. The circuitry may be configured to activate the comparator during time intervals preceding respective anticipated times of the zero-crossing events, and to deactivate the comparator at least once during time periods other than the time intervals.

Abstract: Various embodiments of the present invention provide for an adaptive and accurate zero cross circuit that can operate without directly sensing an inductor current. Certain embodiments allow adjustment of a zero crossing condition while eliminating the need for a blanking time. In certain embodiments this is accomplished by detecting the effects of turning off a switch on a switching node voltage of a buck converter. Some embodiments use a counter to lengthen or shorten the delay time between an inductor crossing a zero value and the effect of the switching event. In one embodiment, the effect of the switching event includes a change in the direction of the switching node voltage from which the direction of a current flowing in the buck converter inductor.

Abstract: A voltage regulator for generating a housekeeping voltage in a high voltage power supply circuit includes a charging switch coupled to a high voltage node and to a storage device at an output node, and a control voltage regulation circuit coupled to the charging switch and configured to cause the charging switch to generate a current pulse for charging the storage device.

Abstract: An apparatus includes a signal converter configured to convert a voltage signal into a current signal and an analog digital converter (ADC) configured to convert the current signal to a digital signal. The apparatus also includes a digital processor configured to process the digital signal and generate an output signal that indicates a zero crossing point of the mains voltage signal.

Abstract: Systems and methods of actively compensating for the input offset voltage of a comparator are provided. A compensation circuit may include a compensation comparator for comparing the comparison signal generated using the output signal of a comparator, to a reference voltage. A first voltage accumulator is coupled to the compensation comparator and produces a first voltage that is related to a first amount of time that the comparison signal spends above the reference voltage. A second voltage accumulator is coupled to the compensation comparator, and produces a second voltage that is related to the second amount of time that the comparison signal spends below the reference voltage. The first voltage and/or the second voltage may be used to provide one or more compensation signals to one or more of the two input terminals of the comparator.

Abstract: A high voltage half-bridge driver circuit has a high voltage terminal and a floating node to be connected with a high side switch therebetween. When turning on the high side switch, a high voltage offset detection circuit detects a voltage related to the voltage at the floating node for triggering a zero voltage switching signal.

Abstract: An I/O circuit for use with an industrial controller provides a zero-crossing detector circuit with low power dissipation through the use of a zero-crossing circuit that activates a light emitting diode of a photo coupler only for a very brief period of time at the zero-crossing (as opposed to at all times other than the zero-crossing). The circuit is coupled with a power supply circuit that uses a reactive element for voltage dropping as opposed to a resistive voltage drop element further reducing power consumption possible with the low power consumption of the photo coupler.

Abstract: Embodiments of the present invention disclose a zero-crossing detection method and circuit. The zero-crossing detection method includes: detecting a time point t0 when a mains voltage jumps from a low electrical level to a high electrical level and an adjacent time point t1 when the mains voltage jumps from a high electrical level to a low electrical level at a port of a detection end; and determining, according to the detected time points t0 and t1, a time point t when the mains voltage crosses zero.

Abstract: An I/O circuit for use with an industrial controller provides a zero-crossing detector circuit with low power dissipation through the use of a zero-crossing circuit that activates a light emitting diode of a photo coupler only for a very brief period of time at the zero-crossing (as opposed to at all times other than the zero-crossing). The circuit is coupled with a power supply circuit that uses a reactive element for voltage dropping as opposed to a resistive voltage drop element further reducing power consumption possible with the low power consumption of the photo coupler.

Abstract: A voltage regulator for generating a housekeeping voltage in a high voltage power supply circuit includes a charging switch coupled to a high voltage node and to a storage device at an output node, and a control voltage regulation circuit coupled to the charging switch and configured to cause the charging switch to generate a current pulse for charging the storage device.

Abstract: Systems and methods of actively compensating for the input offset voltage of a comparator are provided. A compensation circuit may include a compensation comparator for comparing the comparison signal generated using the output signal of a comparator, to a reference voltage. A first voltage accumulator is coupled to the compensation comparator and produces a first voltage that is related to a first amount of time that the comparison signal spends above the reference voltage. A second voltage accumulator is coupled to the compensation comparator, and produces a second voltage that is related to the second amount of time that the comparison signal spends below the reference voltage. The first voltage and/or the second voltage may be used to provide one or more compensation signals to one or more of the two input terminals of the comparator.

Abstract: A system for detecting a Zero Crossing point is provided. The system includes: a coupling unit connected between a high voltage side and a low voltage side of the system; and a zero crossing detector connected to the high voltage side and configured to divide a filtered mains voltage signal and to generate an output signal that indicates a zero crossing point of the filtered mains voltage signal.

Abstract: Methods and systems for detection of zero crossings in a signal are described. For example, true zero crossings in an alternating voltage power source signal can be detected in the presence of noise pulses. The zero crossing detections are performed by establishing a value of a signal status counter, and at a repeating interval if the signal is a logic low value, the value of the signal status counter is decremented if the signal status counter is greater than a first value otherwise a flag is set to enable detection of a zero crossing in the signal. In addition, at the repeating interval, if the signal is a logic high value, the value of the signal status counter is incremented, and if after incrementing the signal status counter is equal to a second value and the flag is set, a zero crossing of the signal is declared.

Abstract: A zero-crossing gain control system is disclosed herein. The system comprises a gain control unit for amplifying an input signal to an output signal, a zero-crossing monitoring circuit for monitoring the input signal or output signal, and a register for latching the digital control signal and generating a gain control signal that controls the gain control unit. The system may further comprise a maximum write time setting circuit for generating a write signal. The digital control signal is written into the register when a zero-crossing state is monitored or a maximum write time since a change occurred on of the digital control signal is expired. An automatic gain control system is also disclosed herein and further comprises a peak detecting circuit for detecting the level of output signal, a logic circuit for lowering or restoring the digital control signal according to the result from the peak detecting circuit.

Abstract: An input buffer circuit for use in a semiconductor device includes a comparator configured to compare a reference voltage with a voltage of an input signal, and output the result of comparison, an activation unit configured to control an activation state of an input buffer in response to an enable signal, a skew adjusting unit configured to change an amount of a current flowing in the comparator in response to one or more skew adjusting signals, and a control signal generator configured to control the enable signal and the skew adjusting signal in response to one or more calibration codes and an input control signal.

Abstract: A circuit arrangement includes a reverse conducting transistor having a gate electrode and a load current path between an emitter and collector electrode. The transistor is configured to allow for conducting a load current in a forward direction and in a reverse direction through the load current path and activated or deactivated by a respective signal at the gate electrode. The circuit arrangement further includes a gate control unit and a monitoring unit. The gate control unit is connected to the gate electrode and configured to deactivate the transistor or prevent an activation of the transistor via the gate electrode when the transistor is in a reverse conducting state. The monitoring unit is configured to detect a sudden rise of a collector-emitter voltage of the reverse conducting transistor which occurs, when the load current crosses zero, while the transistor is deactivated or activation is prevented by the gate control unit.

Abstract: A high voltage H-bridge driver circuit has a high voltage terminal and a floating node to be connected with a high side switch therebetween. When turning on the high side switch, a high voltage offset detection circuit detects a voltage related to the voltage at the floating node for triggering a zero voltage switching signal.

Abstract: A circuit arrangement includes a reverse conducting transistor having a gate electrode and a load current path between an emitter and collector electrode. The transistor is configured to allow for conducting a load current in a forward direction and in a reverse direction through the load current path and activated or deactivated by a respective signal at the gate electrode. The circuit arrangement further includes a gate control unit and a monitoring unit. The gate control unit is connected to the gate electrode and configured to deactivate the transistor or prevent an activation of the transistor via the gate electrode when the transistor is in a reverse conducting state. The monitoring unit is configured to detect a sudden rise of a collector-emitter voltage of the reverse conducting transistor which occurs, when the load current crosses zero, while the transistor is deactivated or activation is prevented by the gate control unit.

Abstract: In at least one embodiment, the controller senses a leading edge, phase cut AC input voltage value to a switching power converter during a cycle of the AC input voltage. The controller senses the voltage value at a time prior to a zero crossing of the AC input voltage and utilizes the voltage value to determine the approximate zero crossing. In at least one embodiment, by determining an approximate zero crossing of the AC input voltage, the controller is unaffected by any disturbances of the dimmer that could otherwise make detecting the zero crossing problematic. In at least one embodiment, the controller approximates the AC input voltage using a function that estimates a waveform of the AC input voltage and determines the approximate zero crossing of the AC input voltage from the approximation of the AC input voltage.

Abstract: Methods and systems for detection of zero crossings in a signal are described. For example, true zero crossings in an alternating voltage power source signal can be detected in the presence of noise pulses. The zero crossing detections are performed by establishing a value of a signal status counter, and at a repeating interval if the signal is a logic low value, the value of the signal status counter is decremented if the signal status counter is greater than a first value otherwise a flag is set to enable detection of a zero crossing in the signal. In addition, at the repeating interval, if the signal is a logic high value, the value of the signal status counter is incremented, and if after incrementing the signal status counter is equal to a second value and the flag is set, a zero crossing of the signal is declared.

Abstract: Methods and systems for detection of zero crossings in a signal are described. For example, true zero crossings in an alternating voltage power source signal can be detected in the presence of noise pulses. The zero crossing detections are performed by establishing a value of a signal status counter, and at a repeating interval if the signal is a logic low value, the value of the signal status counter is decremented if the signal status counter is greater than a first value otherwise a flag is set to enable detection of a zero crossing in the signal. In addition, at the repeating interval, if the signal is a logic high value, the value of the signal status counter is incremented, and if after incrementing the signal status counter is equal to a second value and the flag is set, a zero crossing of the signal is declared.

Abstract: A circuit arrangement for identifying network zero crossings of a network voltage of an alternating current network is provided. A measurement current generated by the network voltage is supplied to a zero crossing detector in order to produce a network zero crossing signal. A current sink is arranged between a live conductor and a neutral conductor of the alternating current network, the current sink allowing the path of a current value of the measurement current generated by the network voltage to be defined.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: Methods and systems for detection of zero crossings in a signal are described. For example, true zero crossings in an alternating voltage power source signal can be detected in the presence of noise pulses. The zero crossing detections are performed by establishing a value of a signal status counter, and at a repeating interval if the signal is a logic low value, the value of the signal status counter is decremented if the signal status counter is greater than a first value otherwise a flag is set to enable detection of a zero crossing in the signal. In addition, at the repeating interval, if the signal is a logic high value, the value of the signal status counter is incremented, and if after incrementing the signal status counter is equal to a second value and the flag is set, a zero crossing of the signal is declared.

Abstract: A zero-crossing detecting device that detects a zero-crossing point of AC voltage, the device has a full-wave rectifier that rectifies the AC voltage and outputs a full-wave rectified voltage, a charger that is charged at a predetermined charging voltage by application of the full-wave rectified voltage, wherein the charger outputs a charging current when the full-wave rectified voltage falls below the charging voltage, and a signal output part that outputs a zero-crossing detecting signal. The signal output part outputs the zero-crossing detecting signal when the charging current flows to the signal output part.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal.

Abstract: A control system includes a zero crossing detecting circuit for detecting a zero crossing of an AC signal. The circuit includes a transformer having a primary portion and a secondary portion. The primary portion receives the AC signal. The secondary portion comprises first and second terminals. The first terminal is biased at a first DC voltage level. An output switch is operatively connected to the second terminal and has an on state and an off state. The output switch selectively activates an output signal of the zero crossing detecting circuit according to an activation voltage level sensed by the output switch and corresponding to the zero crossing. While in the off state, the output switch is biased at a second DC voltage level. A voltage difference between the first and second DC voltage levels substantially equals the activation voltage level. A controller monitors the output signal and controls an operation based on the output signal.

Abstract: A circuit arrangement for identifying network zero crossings of a network voltage of an alternating current network is provided. A measurement current generated by the network voltage is supplied to a zero crossing detector in order to produce a network zero crossing signal. A current sink is arranged between a live conductor and a neutral conductor of the alternating current network, the current sink allowing the path of a current value of the measurement current generated by the network voltage to be defined.

Abstract: A zero-crossing detecting device that detects a zero-crossing point of AC voltage, the device has a full-wave rectifier that rectifies the AC voltage and outputs a full-wave rectified voltage, a charger that is charged at a predetermined charging voltage by application of the full-wave rectified voltage, wherein the charger outputs a charging current when the full-wave rectified voltage falls below the charging voltage, and a signal output part that outputs a zero-crossing detecting signal. The signal output part outputs the zero-crossing detecting signal when the charging current flows to the signal output part.

Abstract: An amplifier stage or circuit for providing cross-point adjustment. The circuit may include a first input node configured to receive a first data signal and a second input node configured to receive a second data signal that is complementary of the first data signal. The circuit also includes a programmable first stage having a first node coupled to the first input node and a second node coupled to the second input node that is configured to adjust an amount of current provided to the first and second data signals to create a signal offset. The circuit further includes a second stage having a first node coupled to a third node of the programmable first stage and a second node coupled to a fourth node of the programmable first stage configured to provide the signal offset at a third and fourth node of the second stage to adjust the cross-point of the first and second signals.

Abstract: In-home communication systems 110 and 130 and an access communication system 120 that are capable of co-existing. The communication systems 110 and 130 and the access communication system 120 are able to co-exist by utilizing TDM that is in synchronization with a power cycle. Further, communication system that needs to secure AV-QoS assigns transmission timing to a slave station within itself by synchronizing a beacon cycle with a cycle of a power line.

Abstract: Current switching point determination devices use two comparators with fixed threshold values. According to an exemplary embodiment of the present invention, a power inverter control device for switching point determination is provided which comprises a filter circuit and a subsequent single comparator. By this arrangement, the time event is independent of the amplitude and for sufficiently small frequencies also of the frequency.

Abstract: In one embodiment, a zero crossing detector couples a plurality of comparators in parallel and operates at least a portion of the comparators at different time periods.

Abstract: A zero-crossing detector includes a pair of input terminals, the terminals being adapted to receive an AC input signal; a rectifier, the rectifier rectifying the AC input signal; a current source, the current source being powered by the rectified AC input signal; and an optoelectric coupler having a coupler input and a coupler output, the coupler input being driven by the current source and the coupler output providing a zero-crossing signal. The zero-crossing signal is galvanicly isolated from the AC input signal.

Abstract: A sampled-data analog circuit uses zero-crossing detector. A waveform generator produces a plurality of segments of ramp at the output. An output of a zero crossing detector controls a sampling switch, thereby causing a precise sample of the output voltage to be taken at the instant the zero crossing detector senses the zero crossing of the input signal. The waveform generator further includes a output hold function to maintain the output voltage.

Abstract: A sampled-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. The level-crossing detection may be a zero-crossing detection. An optional common-mode feedback circuit can keep the output common-mode voltage substantially constant.

Abstract: An improved zero crossing circuit includes a signal output circuit element for registering a sharply defined signal, and in one embodiment an isolation circuit element cooperating with the signal output element, and a delay-inducing circuit element cooperating with the signal output element for applying a substantially constant time delay to the signal. In particular, the delay-inducing element includes a switch circuit and a delay circuit. The switch circuit commences the time delay by the delay circuit upon a triggering voltage being reached. The time delay circuit is adapted so that the time delay equates to a time period required for the triggering voltage to change to zero so as to cross zero voltage substantially as the time delay expires.

Abstract: A detecting circuit for detecting an input signal crossing a ground level is disclosed. The circuit comprises two PMOS transistors and two NMOS transistors connected, respectively. The PMOS transistors have source terminals connected to a power voltage, the gate terminals connected together and the drain terminal of the second PMOS transistors. The first NMOS transistor has the source terminal as an input terminal to retrieve an input signal, and the drain terminal to be act as output terminal and the second NMOS transistor has the source terminal grounded. The gate terminals of the two NMOS transistors are connected together and to a biased voltage. The circuit can also be used to detect the power voltage if the input terminal is set at the source terminal of the first PMOS transistor and the source terminal of the first NMOS transistor grounded.

Abstract: A sampled-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. The level-crossing detection may be a zero-crossing detection. An optional common-mode feedback circuit can keep the output common-mode voltage substantially constant.

Abstract: A zero-crossing point detection circuit includes a hot line input, a neutral line input, a first zero-crossing point output, and a first optical coupler. The first optical coupler includes a first light-emitting diode (LED) and a first optical transistor. The hot line input and neutral line input are respectively connected to two terminals of the first LED. An emitter of the first optical transistor is grounded. A collector of the first optical transistor is connected to a direct current (DC) power source. The collector of the first optical transistor is also connected to the first zero-crossing point output.