Abstract: A semiconductor device capable of detecting a micro-short circuit of a secondary battery is provided. The semiconductor device includes a first source follower, a second source follower, a transistor, a capacitor, and a comparator. A negative electrode potential and a positive electrode potential of the secondary battery are supplied to the semiconductor device, a first potential is input to the first source follower, and a second potential is input to the second source follower. A signal for controlling the conduction state of the transistor is input to a gate of the transistor, and an output potential of the first source follower related to the potential between the positive electrode and the negative electrode of the secondary battery is sampled.

Abstract: A motor unit having a motor having a stator and an armature, the armature being arranged for relative driven motion with respect to the stator. A motor control unit has a supply circuit for providing a supply voltage at the motor to provide a set power level to the motor for driving the armature into motion. A measurement circuit is measuring a value of a physical variable indicative of a current flow through the motor, The motor control unit is arranged to interrupt the provision of the supply voltage by the supply circuit and to dynamically brake the motor during a braking time interval and further to measure the value of the physical variable during the braking time interval.

Abstract: A method for extracting a characteristic signal from a power frequency signal includes steps of: S1, detecting a voltage half-wave zero-crossing area in a single voltage cycle in the power frequency signal by a signal; superimposing a voltage modulation signal on the voltage half-wave zero-crossing area, and superimposing an instantaneous pulse on a current cycle in the power frequency signal corresponding to the voltage half-wave zero-crossing area; generating the characteristic signal with current cycles and voltage cycles; S2, demodulating whether there is the voltage modulation signal in the power frequency signal, if so, executing step S3; and S3, demodulating the characteristic signal to obtain the current modulation signal and the voltage modulation signal respectively; and determining whether data corresponding to the current modulation signal and date corresponding to the voltage modulation signal are predetermined data, wherein if so, the characteristic signal exists.

Abstract: Systems and methods include an analog-to-logic circuit and a digital processing component. The analog-to-logic circuit receives a first electrical signal, outputs a first logic signal indicating whether or not a voltage of the first pulse is greater than a first threshold voltage, and outputs a second logic signal indicating whether or not the voltage of the first pulse is greater than a second threshold voltage. The digital processing component receives the first logic pulse and the second logic pulse, determines, based on the second logic signal, if the first pulse is valid, and determines, based on the first logic signal, a first trigger time associated with the first pulse.

Abstract: A zero-crossing detector to be installed in a ceiling fan includes: a first terminal; a second terminal; and a rectifier, an adjustor and a feedback generator that cooperatively generate a current signal based on an AC voltage between the first and second terminals. The current signal has a non-zero magnitude when the AC voltage causes a potential at the first terminal to be greater than a potential at the second terminal, and has a zero magnitude when otherwise. An average of the non-zero magnitude of the current signal is greater when the adjustor is in a working state than when the adjustor is in a power saving state. The feedback generator generates a feedback signal based on the current signal.

Abstract: Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal.

Abstract: A control circuit for a wearable device includes: a power supply circuit, a DC blocking circuit, and a voltage comparison circuit. The power supply circuit is connected to a high voltage end, a low voltage end, a first signal input end, a second signal input end; the DC blocking circuit is connected to the first node, the second node, and a sensor in the wearable device; the voltage comparison circuit is connected to the first node, a reference voltage end and an output end, and configured to compare voltages of the first node and the reference voltage end; and output a first control signal through the output end when the voltage of the first node is smaller than the voltage of the reference voltage end, and output a second control signal through the output end when the voltage of the first node is larger than the voltage of the reference voltage end.

Abstract: A circuit device includes a comparator, a reference voltage generation circuit, and a coupling control circuit. The comparator is configured to output a power-on reset signal by comparing a monitoring target voltage generated from a power supply voltage with a reference voltage. The reference voltage generation circuit is configured to generate the reference voltage. The coupling control circuit is coupled between a power supply voltage node and a reference voltage node. The coupling control circuit couples the reference voltage node and the power supply voltage node in a predetermined period after the power supply voltage is supplied.

Abstract: A voltage comparator and an operation method thereof are provided. The voltage comparator includes an amplifying circuit, a reference current source, and a transient current source. A first input terminal and a second input terminal of the amplifying circuit respectively receive a first corresponding voltage corresponding to a target voltage and a reference voltage. The reference current source is coupled to the amplifying circuit to provide a reference current. The transient current source is coupled to the amplifying circuit to selectively provide a transient current. The transient current source detects a transition of a second corresponding voltage corresponding to the target voltage to dynamically adjust the transient current. Therefore, when a rapidly increasing voltage occurs in the target voltage, the transient current source may temporarily increase the current of the amplifying circuit, thereby accelerating the response speed of the amplifying circuit.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.

Abstract: A comparator includes: a first selector for selecting one of a first reference voltage and a first correction reference voltage, based on a first determination value of data at a past time of a first adjacent channel; a first comparator for comparing the difference between a voltage selected from the first reference voltage and the first correction reference voltage and a second reference voltage with an input voltage at a current time of a target channel; and a first output unit for determining an output voltage at the current time of the target channel, based on the comparison result of the first comparator.

Abstract: A voltage monitoring circuit for monitoring an output voltage of a power supply device. The power supply device includes a voltage conversion part that converts an input voltage to the output voltage according to a difference between a feedback voltage based on the output voltage and a first reference voltage. The voltage monitoring circuit includes: a threshold voltage generation circuit configured to generate a threshold voltage from the first reference voltage; and a comparator configured to compare the threshold voltage with the feedback voltage.

Abstract: A filter circuit includes a first rise delay circuit that delays a rising time of a first shifted signal by a predetermined time for output and a first fall delay circuit that delays a falling time of a second shifted signal by a predetermined time for output. The first rise delay circuit is configured so that a second rise delay signal does not follow a change in a first voltage toward a decreasing side and follows a change in the first voltage toward an increasing side. The first fall delay circuit is configured so that a second fall delay signal does not follow a change in the first voltage toward a decreasing side and follows a change in the first voltage toward an increasing side.

Abstract: An exemplary semiconductor memory includes a channel region disposed in a semiconductor body, a gate region overlying the channel region, a first and a second source/drain region disposed in the semiconductor body, where the first source/drain region is spaced from the second source/drain region by the channel region. The exemplary memory further includes a first contact electrically contacting the first source/drain region, a second contact electrically contacting the first source/drain region and spaced from the second contact, and a third contact electrically contacting the second source/drain region. The first and second contacts are configured so that a resistivity of the first source/drain region can be irreversibly increased by application of an electric current between the first and second contacts. The first contact extends over a first width, the third contact extends over a third width, where the first width is smaller than the third width.

Abstract: An integrated circuit is provided with a bandgap voltage reference circuit having a bandgap reference voltage output. A bandgap failure detection circuit is coupled to the bandgap reference voltage output. The bandgap failure detection forms a model value of the reference voltage from a first time, compares a present value of the reference voltage at a second time to the model value; and asserts a bandgap fail signal to indicate when the present value is less than the model value by a threshold value. The integrated circuit is reset by the bandgap fail signal. The detection circuit may be operated from a failsafe voltage domain that also allows a critical circuit to complete a pending operation during a reset.

Abstract: According to an embodiment of the present disclosure, a receiver of modulated signals comprises a signal sampling unit configured to sample a signal, a zero-crossing demodulator, and a timing offset tracking unit. The zero-crossing demodulator includes: a zero-crossing counter configured to determine a number of zero crossings for each pulse of the signal, and a symbol selector configured to decode a sequence of pulses as a symbol based on the number of zero crossings in the sequence of pulses. The timing offset tracking unit is configured to: calculate a metric based on an accumulation of the number of zero crossings and corresponding pulse values of the decoded symbol, compare the metric to a predetermined threshold value, and compensate a timing offset of the signal by causing the signal sampling unit to sample the signal at an earlier interval or a later interval in response to the comparison.

Abstract: A method of assembling a remote sensor system to detect a gas or chemical and a remote sensor system are described. The method includes fabricating a sensor, the sensor outputting a sensor signal that changes upon contact of the sensor with the gas or chemical and the sensor having an input port for a clock signal, coupling a capacitor to the sensor, the capacitor output voltage resulting from the sensor signal output by the sensor, and coupling a mixer to the capacitor and a low frequency oscillator, the mixer configured to mix the capacitor output voltage with the low frequency oscillator output to generate an output signal. The method also includes coupling an antenna to the mixer, the antenna configured to transmit the output signal indicating detection of the gas or chemical.

Abstract: A method of assembling a remote sensor system to detect a gas or chemical and a remote sensor system are described. The method includes fabricating a sensor, the sensor outputting a sensor signal that changes upon contact of the sensor with the gas or chemical and the sensor having an input port for a clock signal, coupling a capacitor to the sensor, the capacitor output voltage resulting from the sensor signal output by the sensor, and coupling a mixer to the capacitor and a low frequency oscillator, the mixer configured to mix the capacitor output voltage with the low frequency oscillator output to generate an output signal. The method also includes coupling an antenna to the mixer, the antenna configured to transmit the output signal indicating detection of the gas or chemical.

Abstract: A visual notification device in a fire-fighting system may include an input end, a booster circuit, an energy storage element, at least one flash element, and a flash control circuit, for causing energy in the energy storage element to be applied to the at least one flash element to make it flash. At least one of the booster circuit, the at least one flash element, and the flash control circuit is designed such that a residual voltage across the energy storage element in each flash operation is greater than or equal to the input voltage. The visual notification device may enable the occurrence of a repetitive inrush current to be suppressed effectively without the addition of a current-limiting circuit.

Abstract: Electronic modules with small and flexible interfaces are disclosed. One example electronic module includes a power supply terminal configured to receive power for the electronic module and circuitry configured to carry out various functions. The functions carried out by the electronic module circuitry include simultaneously receiving both of the following via the power supply terminal: a power signal for carrying out a mission mode operation of the electronic module, and a data signal.

Abstract: An encoder is configured for detection of rotational movement of a rotatable shaft in relation to a part of a machine, and a method is provided for generating a reference signal by an encoder.

Abstract: The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.

Abstract: A system for detecting a Zero Crossing point is provided. The system includes: a coupling unit connected between a high voltage side and a low voltage side of the system; and a zero crossing detector connected to the high voltage side and configured to divide a filtered mains voltage signal and to generate an output signal that indicates a zero crossing point of the filtered mains voltage signal.

Abstract: A power-on-detection (POD) circuit includes first and second comparators, a voltage divider, a detection circuit coupled to a first voltage source node and the voltage divider, and logic circuitry coupled to outputs of the first and second comparators. The detection circuit outputs a control signal identifying if a first voltage source node has a voltage potential that is higher than ground. The control signal turns on and off the first and second comparators, which are respectively coupled to first and second nodes of the voltage divider and to a reference voltage node. The logic circuitry outputs a power identification signal based on the signals received from the outputs of the first and second comparators.

Abstract: Disclosed is a low voltage detection circuit. The low voltage detection circuit includes, a voltage comparison circuit, an output stage, an electric current circuit, and a judgment circuit. When the voltage comparison circuit detects that the voltage of the detection target is a predetermined voltage value or less, an output state of the output stage is promptly changed. When the voltage comparison circuit detects that the voltage of the detection target is a predetermined voltage value or more, the output state of the output stage is changed after a delay time obtained by the electric current circuit.

Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.

Abstract: A comparator circuit, includes a first power source terminal having a first potential, a second power source terminal having a second potential different from the first potential, a detection voltage terminal, a reference voltage generator coupled between the first power source terminal and the second power source terminal, the reference voltage generator generating a middle potential which is a potential between the first potential and the second potential and outputting the middle potential at a middle potential node, the reference voltage generator further generating a reference voltage, a bias unit coupled between the first power source terminal and the middle potential node, the bias unit receiving the reference voltage and generating a corresponding reference voltage by using the first potential and the middle potential as energy sources thereof, and a comparator unit coupled between the first and second power source terminals and the detection voltage terminal.

Abstract: A method and apparatus for pulse pile-up rejection are disclosed. The apparatus comprises a delay value application constituent configured to receive a threshold-crossing time value, and provide an adjustable value according to a delay value and the threshold-crossing time value; and a comparison constituent configured to receive a peak-occurrence time value and the adjustable value, compare the peak-occurrence time value with the adjustable value, indicate pulse acceptance if the peak-occurrence time value is less than or equal to the adjustable value, and indicate pulse rejection if the peak-occurrence time value is greater than the adjustable value.

Abstract: A power-on reset circuit is disclosed. The power-on reset circuit includes a first resistor; a first transistor, including a first terminal coupled to a second terminal of the first resistor, and a control terminal for receiving a reference voltage; a second resistor, including a first terminal coupled to a second terminal of the first transistor; a second transistor, including a first terminal coupled to a second terminal of the first resistor, and a control terminal coupled to a second terminal of the second transistor and utilized for receiving an input voltage; and a comparator, including a first input terminal for receiving a comparison voltage, and a second input terminal for receiving the reference voltage, for generating a power-on reset signal according to the comparison voltage and the reference voltage.

Abstract: Methods and systems for detection of zero crossings in a signal are described. For example, true zero crossings in an alternating voltage power source signal can be detected in the presence of noise pulses. The zero crossing detections are performed by establishing a value of a signal status counter, and at a repeating interval if the signal is a logic low value, the value of the signal status counter is decremented if the signal status counter is greater than a first value otherwise a flag is set to enable detection of a zero crossing in the signal. In addition, at the repeating interval, if the signal is a logic high value, the value of the signal status counter is incremented, and if after incrementing the signal status counter is equal to a second value and the flag is set, a zero crossing of the signal is declared.

Abstract: Systems and methods of actively compensating for the input offset voltage of a comparator are provided. A compensation circuit may include a compensation comparator for comparing the comparison signal generated using the output signal of a comparator, to a reference voltage. A first voltage accumulator is coupled to the compensation comparator and produces a first voltage that is related to a first amount of time that the comparison signal spends above the reference voltage. A second voltage accumulator is coupled to the compensation comparator, and produces a second voltage that is related to the second amount of time that the comparison signal spends below the reference voltage. The first voltage and/or the second voltage may be used to provide one or more compensation signals to one or more of the two input terminals of the comparator.

Abstract: An input buffer circuit for use in a semiconductor device includes a comparator configured to compare a reference voltage with a voltage of an input signal, and output the result of comparison, an activation unit configured to control an activation state of an input buffer in response to an enable signal, a skew adjusting unit configured to change an amount of a current flowing in the comparator in response to one or more skew adjusting signals, and a control signal generator configured to control the enable signal and the skew adjusting signal in response to one or more calibration codes and an input control signal.

Abstract: Methods and devices for detecting single-event transients in combinational logic circuits and other circuits. A sensing circuit detects a voltage or current deviation at a bulk contact node of a transistor. Output of the sensing circuit is amplified and used to flip a latch. Output of the latch may be evaluated and used in possible error correction measures.

Abstract: A switched capacitor circuit includes a threshold detector to generate a threshold detection signal when a difference between first and second input signals crosses a predetermined level. A coarse current source produces a coarse ramp. A series sampling capacitor samples a coarse output voltage when the threshold detector indicates a first threshold crossing. The sampling capacitor is connected in series with a fine current source producing a fine ramp.

Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period.

Abstract: The present invention relates to a simple and small-sized circuit configuration (10) for significantly reducing resettling time of a peak or zero current comparator. This circuit configuration (10) provides the comparator input stage with an alternative current path at the comparator input submitted to a large voltage variation able to disturb the DC-settings. This circuit configuration (10) comprises a pair of small transistors (P3, P4) coupled to a differential pair of transistors (N1, N2) of the comparator input stage and having a polarity different from said pair of transistors (P3, P4). The gates of the transistors P3 and P4 share a common terminal connected to said comparator input. The currents and voltages across the comparator are always maintained close to the normal DC-setting values during the voltage transition phase. This circuit configuration (10) can be used in any current comparator for detecting a peak or a zero current, in particular, in DC-DC converters based on a switched operating mode.

Abstract: A data processing system (100), such as a System-on-Chip, includes a processor (120), a memory (140) that has an expected minimum data retention voltage, and a brown-out detector (160), which includes a brown-out detection circuit (201) that has an analog output, and an output circuit (248 and 252) that converts the analog output of the brown-out detection circuit to a digital brown-out flag. The brown-out detection circuit includes a self-biased current reference, current mirrors, and a current comparator. The brown-out detector monitors voltage of a power supply of the memory, and the brown-out detector asserts the digital brown-out flag to the processor when the voltage of the power supply is at, or slightly above, a highest expected minimum data retention voltage.

Abstract: Methods and systems for detection of zero crossings in a signal are described. For example, true zero crossings in an alternating voltage power source signal can be detected in the presence of noise pulses. The zero crossing detections are performed by establishing a value of a signal status counter, and at a repeating interval if the signal is a logic low value, the value of the signal status counter is decremented if the signal status counter is greater than a first value otherwise a flag is set to enable detection of a zero crossing in the signal. In addition, at the repeating interval, if the signal is a logic high value, the value of the signal status counter is incremented, and if after incrementing the signal status counter is equal to a second value and the flag is set, a zero crossing of the signal is declared.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals connected to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected in series with the first transistor, a fourth transistor of the second conductivity type connected in series with the second transistor, a fifth transistor of the second conductivity type through which a mirror current depending on a current flowing through the third transistor, a sixth transistor of the second conductivity type flowing a mirror current depending on a current flowing through th

Abstract: A data processing system (100), such as a System-on-Chip, includes a processor (120), a memory (140) that has an expected minimum data retention voltage, and a brown-out detector (160), which includes a brown-out detection circuit (201) that has an analog output, and an output circuit (248 and 252) that converts the analog output of the brown-out detection circuit to a digital brown-out flag. The brown-out detection circuit includes a self-biased current reference, current mirrors, and a current comparator. The brown-out detector monitors voltage of a power supply of the memory, and the brown-out detector asserts the digital brown-out flag to the processor when the voltage of the power supply is at, or slightly above, a highest expected minimum data retention voltage.

Abstract: When switching a power supply rail for a processing circuit from a first voltage level to a second voltage level, power level detection circuitry detects when the supply voltage level reaches a predetermined voltage level. The power level detection circuitry comprises a first transistor and a second transistor which compete with one another such that the first transistor pulls a signal node voltage level at a signal node towards the supply voltage level while the second transistor pulls the signal node voltage level towards an external power supply voltage level. When the supply voltage level on the power supply rail reaches the predetermined voltage level, the first transistor overcomes the second transistor to trigger a ready signal indicating that the supply voltage level has reached the predetermined voltage level.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected between the first transistor and the fourth terminal, and a fourth transistor of the second conductivity type connected between the second transistor and the third terminal, the fourth transistor flowing a mirror current depending on a current passing through the third transistor.

Abstract: There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider for generating detection voltage based on an inputted bulk voltage; and a CMOS circuit for generating a output signal having predetermined logic value determined by the detection voltage wherein the voltage divider includes a first transistor having a gate coupled to a ground voltage and a second transistor having a gate coupled to an internal power voltage and a bulk coupled to the inputted bulk voltage.

Abstract: A comparator generates lower and upper reference voltages to establish an amplitude hysteresis. A first comparator circuit generates a first comparison signal indicating whether an input signal is above the upper reference voltage. A second comparator circuit generates a second comparison signal indicating whether the input signal is below the lower reference voltage. Further, the first and second comparison signals may be low-pass filtered to establish a time hysteresis. A latch is set to a first state if the first control signal indicates the input signal is above the upper reference voltage. The latch is set to a second state if the second control signal indicates the input signal is below the lower reference voltage. In some embodiments, the comparator has a rail-to-rail common mode input voltage range, a low-power mode of operation, and is self-biased to compensate for temperature, voltage, and process characteristics.