Abstract: An integrated comparator circuit includes a first terminal and a second terminal for an operating voltage. An input stage has two complementary MOSFETS having main current paths connected in series defining a common connecting point therebetween. The two MOSFETS have gate terminals connected to the common connecting point. The series circuit of the MOSFETS is connected between the first terminal and a third terminal. An inverter stage has two complementary MOSFETS having main current paths connected in series defining a common connecting point therebetween forming an output terminal. The two complementary MOSFETS have gate terminals connected to the common connecting point of the input stage. The second terminal and the third terminal receive an input signal of the comparator circuit. A fourth terminal is provided for application of a reference potential to determine a switching threshold of the comparator circuit.

Abstract: An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions.

Abstract: A detection circuit includes a current mirror circuit that produces electric currents at first and second output terminals in response to a current supplied to its input terminal. A first active load is connected to the first output terminal and a second active load is connected to the second output terminal and an external output terminal. A control circuit controls the potential of the control electrode of the second active load according to the voltage or the current at the first output terminal. The control circuit can include a capacitive device that determines the voltage at the control electrodes of the active loads according to the peak value of current supplied to the current mirror circuit input terminal.

Abstract: The circuit, in accordance with the present invention is for detecting the presence at a signal input of a high voltage higher than a predetermined value and signaling it to a signal output through a logical type signal. The circuit comprises one or more first transistors of MOS type and of a predetermined conductivity type, each being diode-connected and having its body terminal connected to the source terminal, and having principal conduction paths connected in series for current conduction between a first node and a ground input. The circuit also includes two or more second transistors of the MOS type and of the same conductivity type, with each one being diode-connected and having its body terminal connected to the source terminal and having principal conduction paths connected in series for current conduction between the signal input and the first node.

Abstract: A semiconductor integrated circuit device is intended to prevent generation of an unnecessary leak current and hence to reduce power consumption.

Abstract: A comparator circuit includes a series circuit having a first MOSFET and a second MOSFET. An inverter has a third MOSFET and a fourth MOSFET. A node between the first and second MOSFETs is connected to a gate terminal of the fourth MOSFET. An input voltage is applied between ground and the second MOSFET. A series circuit of a fifth MOSFET and a Zener diode polarized in the blocking direction is connected parallel to the fourth MOSFET. A response threshold of the comparator circuit is defined by adjusting a resistance of the Zener diode occurring in the reverse direction. The resistance is adjusted through the use of a voltage pulse that can be applied to a terminal connected to a cathode of the Zener diode.

Abstract: A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

Abstract: A high voltage detection circuit implemented in an integrated circuit which is switchable between a normal operation mode and an alternative operation mode and having contact pads for electrically connecting the integrated circuit to an external environment. One of the pads functions to provide an interface between an external environment and the integrated circuit for signals having a maximum voltage magnitude, relative to a circuit common, when the integrated circuit is in the normal operation mode. The one pad further functions to receive an external test mode signal which will cause the integrated circuit to switch to the test mode of operation, with the test mode signal having a voltage magnitude which is greater than that of maximum voltage magnitude. The detection circuit includes a first MOS transistor having either the gate or source coupled to the one pad and a second MOS transistor having a source and drain connected in series with the drain and source of the first transistor.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge amplifiers with self trigger and calibration capabilities to provide timing information with better than 20 nanosecond precision. The trigger threshold can be adjusted to provide energy discrimination. The chip has a sparse readout function in which only the channels which have received signals greater than a preselected threshold value are readout, thus providing fast data acquisition capabilities.

Abstract: A data sensing apparatus particularly useful for sensing a ROM device. The apparatus can be used with various voltage level devices because it has an adjustable load. A first load element is connected to the voltage source applied to the ROM device. A second load element is connected in parallel with the first load element. A switching element is connected to the first load element and provides a path for a sensing current of the ROM device. An inverter, responsive to the sensing current, controls the switching element. An amplifier, connected to the switching element, provides a useful output indicative of the sensing current of the ROM device. A voltage level detector detects the voltage level of the voltage source. It disables the second load element so as to increase the load when the voltage level of the voltage source is higher than a predetermined value.

Abstract: A substrate potential detection circuit includes a substrate potential detection unit including a first transistor having a gate and a source connected respectively to a ground line and a reference voltage line, a second transistor having a gate receiving a substrate potential and a drain connected to the ground, and a third transistor having a source connected to the drain of the first transistor and a gate and a drain connected in common to the source of the second transistor to form a detection output node; and a buffer circuit having a drive transistor and a current source, a gate and a source of the drive transistor being connected respectively to the detection output node and the reference voltage line and outputting a substrate detection voltage.

Abstract: A Zener diode is used to simplify a circuit for detecting the level of an operating voltage with respect to a specified range of use. The semiconductor junction of this Zener diode is biased alternately by one voltage or another. Under these conditions, the avalanche voltage of this Zener diode changes. The operating voltage to be monitored is connected to the cathode of this Zener diode. If the monitored operating voltage is higher than the avalanche voltage of this Zener diode, the diode alternately conducts. If the operating voltage is outside this range, this diode is either permanently on or permanently off. The variations that result therefrom are detected to report whether the operating voltage is correct.

Abstract: A level shifting driver shifts a low magnitude logic signal to a high magnitude logic signal while preventing a high supply voltage as associated with the high magnitude logic signal from feeding back into logic devices associated with providing the low magnitude logic signal. An input terminal receives the low magnitude logic signal from a given low voltage logic device. An N-channel MOSFET has its channel disposed serially between the input terminal and an output terminal and its gate coupled to a low supply voltage of the low voltage logic device. A latch network biased by the high supply voltage has one node of its latch coupled to the output terminal for providing an output signal representative of the low magnitude logic signal but of a high magnitude established in accordance with the high supply voltage.

Abstract: An analog to digital converter comprises: first to n.sup.th comparators, having a tandem structure, for comparing an input voltage signal with first to n.sup.th reference voltages and outputting first to n.sup.th bit outputs respectively, said n being a natural number more than one, said first comparator outputting a most significant bit of said first bit output; a first reference voltage generation circuit for generating said first reference voltage; second to n.sup.th reference voltage generation circuits for generating said second to n.sup.th reference voltages, p.sup.th reference voltages being generated in accordance with outputs of said first to (p-1).sup.th comparators, said p being a natural number and l<p<n.

Abstract: This invention is a super voltage detection circuit that functions independent of power supply voltage. The circuit employs a reference node that is coupled to V.sub.CC through a current-limiting device. The node is also coupled to ground via a plurality of series-coupled N-channel diodes. The current-sinking capability of the series-coupled diode path is greater than the current passing capability of the current-limiting device. Thus, a reference voltage is established at the node. The reference voltage is applied to the gate of a P-channel field-effect transistor which acts as a comparator device. The source region of the comparator device is coupled to an input terminal through a plurality of series coupled N-channel diodes. A super voltage may be selectively applied to the terminal.

Abstract: An MOS transistor 3 conducts when a potential of a pseudo GND line 33 exceeds a threshold Vth3 of MOS transistor 3. A current mirror circuit CM1 supplies a current Ib which is .alpha. times a current Ia flowing through MOS transistor 3. A current mirror CM2 lets a current Ib according to the output current Ib from the current mirror circuit CM1 flow out from the pseudo GND line 33 to a ground line 32. Without providing a separate reference potential generating circuit 35, the potential of the pseudo GND line 33 can be maintained to a constant value.

Abstract: A low voltage indicator circuit including a self-biased driver circuit. A voltage at the output terminal is used to create a bias voltage to operate the driver when less than a threshold voltage is present on at least one voltage supply line. A transistor for supplying base drive current to the driver has a base coupled to the at least one voltage supply line in one embodiment and to the bias circuit in other embodiments. The transistor in the one embodiment provides base drive current to the driver when voltage on the at least one voltage supply line is less than the voltage on the output terminal by at least a predetermined amount. In other embodiments, the bias circuit may include a FET or resistor coupled between the output terminal and the base of a bias circuit transistor. The bias circuit transistor has a terminal connected to a bias resistor for providing current through the bias resistor when the bias circuit transistor is turned on.

Abstract: A semiconductor integrated circuit includes memory cell blocks having memory cells arranged in matrix, sense amplifiers, each located adjacent to the memory cells, and sense amplifier control circuits, each of the sense amplifier control circuit being located on outside of the memory cell block. The sense amplifier control circuit has a standard voltage generating circuit and a control circuit for receiving the standard voltage and for transferring a driver signal to the sense amplifier to control the charging ability of the sense amplifier. The source voltage has three voltage regions, first, intermediate, and second regions. In the first voltage region, the potential of the driver signal increases with the increase of the source voltage. In the intermediate voltage region (2.7 to 3 Volt), the potential of the driver signal is changed oppose to the change of the source voltage, and in the second voltage region, the potential of the driver signal decreases with the increase of the source voltage.

Abstract: A power efficient transistor (11) which operates in or near saturation having a base (16), a collector (17), and an emitter (18). A first transistor (12) having a base, collector, and emitter coupled to the base (16), collector (17), and emitter (18) of the transistor (11). The first transistor (12) is biased to operate in or near saturation under quiescent conditions. A plurality of transistors (13) are incrementally enabled or disabled to maintain the transistor (11) in or near saturation under all operating conditions. Each of the transistors (13) have a base, collector, and emitter coupled to the base (16), collector (17), and emitter (18) of the transistor (11). A plurality of drive transistors (14), enable or disable a corresponding one of each transistor of the transistors (13). Each drive transistor of the drive transistors (14) is enabled at a different voltage thereby incrementally enabling and disabling each transistor of transistors (13) maintaining transistor 11 in or near saturation.

Abstract: A circuit and method for sensing and limiting current. A resistor (R1) is used to generate a voltage (V1) proportional to the current flowing in an output transistor (M1). A comparator is formed in a cross coupled quad configuration from bipolar transistors (Q11, Q12, Q13 and Q14) and is coupled to the resistor (R1). When the current in the resistor (R1) generates a voltage in excess of a threshold voltage for the cross coupled quad circuit, the cross coupled quad generates an output indicating the threshold has been reached. In a current limiting configuration, the output of the cross coupled quad is used to reset a flip-flop (FF1) that drives the gate terminal of the output transistor (M1), thus shutting down the output transistor before it is damaged due to excess current. The threshold voltage that triggers the cross coupled quad is proportional-to-absolute-temperature.

Abstract: A low power integrated current source (ICS) for monitoring the voltage at an input terminal includes a current source and a network of current mirror circuits coupled to the current source, to the input terminal and to an output terminal. The circuit monitors the input voltage by comparing the input current with a reference current determined by the current source. The current mirror network responds to a predetermined voltage (current) at the input terminal to switch the output voltage at the output terminal from a first voltage level to a second voltage level. The ICS voltage monitor circuit limits the maximum value of the input current as the input voltage increases beyond a given voltage level thereby limiting the power dissipation. The trip voltage can be reset by merely changing the reference current supplied by the current source or by changing the value of an input resistor whose purpose is to convert the input voltage into an input current.

Abstract: A comparator circuit (31) for sensing a voltage difference between a battery voltage and a power supply voltage is coupled to a switch (39). The comparator circuit is capable of accurately sensing a voltage near the power supply voltage. The comparator circuit (31) comprises a first amplification stage (32-36), a second amplification stage (37), and a Schmitt trigger (38). The first amplification stage (32-36) includes a first source follower (32) and a second source follower (33) for generating a differential voltage corresponding to a difference voltage between the battery voltage and the power supply voltage. The first amplification stage (32-36) reduces problems in amplifying voltage near the power supply voltage by level shifting the voltage through the use of source followers and insuring transistors operate in a saturation region of operation. The second amplification stage (37) further amplifies the difference voltage between the battery voltage and the power supply voltage.

Abstract: A signal detector circuit in a data receiver including a programmable hysteresis circuit for setting and detecting the presence of both a threshold minimum data signal level and a reset signal level higher than the minimum signal level.

Abstract: An improved sense amplifier is disclosed employing bleeder and dampening devices coupled in a robust feedback configuration for maintaining a relatively narrow and stable voltage level above the high threshold of the sense amplifier.

Abstract: A semiconductor integrated circuit device includes an aging mode control circuit, which detects the times of toggle of an external supply voltage (external Vcc) with a predetermined amplitude and generates an aging mode enable signal, and an internal voltage reduction circuit transmitting a voltage, which changes in accordance with change of the external supply voltage (external Vcc), onto an internal supply line in response to the aging mode enable signal. The semiconductor integrated circuit device enters an aging mode only when the external supply voltage oscillates a predetermined number of times with an amplitude not less than the predetermined amplitude. The semiconductor integrated circuit device does not unnecessarily enter the aging mode for an aging test, and facilely and surely enters the aging mode without utilizing a special timing relationship of external control signals.

Abstract: A circuit for connecting a first circuit node to either a second or a third circuit node relative to the voltage potential on the third circuit node includes two bipolar transistors connected in series. The collectors of both transistors are connected to the first circuit node. The emitter of the first transistor is connected to the second circuit node and the emitter of the second transistor is connected to the third circuit node. Means are provided for maintaining the base of the second transistor at a constant, preset bias voltage.